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2020-05-08soc/intel: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: I468d2ba85033c41ba53333ebbfd6f4108a36e407 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-08sb/intel/i82371eb: Replace GPLv2 long form headers with SPDX headerElyes HAOUAS
Change-Id: If54234ec2d80d5a6502400eb1c6f02dd9bba73c5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-08vboot: Provide declaration for verstage_mainboard_early_init()Furquan Shaikh
Similar to bootblock, provide declaration for verstage_mainboard_early_init() to support early mainboard initialization if verstage is run before bootblock. BUG=b:155824234 TEST=Verified that trembyle still builds Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I106213ecc1c44100f1f74071189518563ac08121 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-08soc/intel/skl: Drop `acpi_mainboard_gnvs`Angel Pons
Literally nobody else uses it and it does nothing. Change-Id: I7e6466137b5069a7f785972205bd43f3cb25d378 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41112 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08mb/google/reef: add G2 TS support for snappyKevin Chiu
Add G2 GTCH7503 HID TS support spec from G2: G7500 / Ver.1.2 (3, April, 2018) BUG=b:155827595 BRANCH=master TEST=emerge-snappy coreboot Change-Id: I151bf141148f4f00b3dadd9c44ab3a6b7731cde1 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41090 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08tests: Add proper license headersJan Dabros
Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: Id8ca7c53122632c674e6bf952046ea22c0408e55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-07memrange: constify memranges_is_empty()Aaron Durbin
memranges_is_empty() doesn't need to manipulate the object. Mark the parameter as const. Change-Id: I89f4ec404c144eac8d2900945a1ccaf5cc4f88bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41102 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-07arch/x86: unexpose postcar_frame_common_mtrrs()Aaron Durbin
The only caller is contained within the postcar_loader compilation unit. Therefore, remove postcar_frame_common_mtrrs() from the global symbol namespace. Change-Id: I90d308669d13eb2bebf1eca4d47e3f3b4f178714 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-07payloads/external/Makefile.inc: Pass hardware IRQ option to SeaBIOS MakefileMichał Żygowski
The hardware IRQ option was not passed to SeaBIOS Makefile and resulted in HARDWARE_IRQ being permanently disabled regardless of Kconfig selection in coreboot. On platforms that need the hardware IRQ it caused hangs at boot menu or iPXE prompts. TEST=enter SeaBIOS boot menu on Libretrend LT1000 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iafcfd743177bbcd1ee23e227c74dd8268c4c23c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-07mb/x9scl/early_init: Remove unused includesElyes HAOUAS
Change-Id: I455a43ab6c4931a4fb1f717a65013b6b7cefb777 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-07soc/intel/tigerlake: Add PMC to platform ACPI name entryJohn Zhao
PMC device name string "PMC" is added to platform soc_acpi_name() for pmc driver. BUG=b:151646486 TEST=Built and booted to kernel successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ida7fc7e2340f2a809464ca66fd1922f3229e2e18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-07util/sconfig: Drop use of ref_count for chip_instanceFurquan Shaikh
chip_instance structure currently uses a ref_count to determine how many devices hold reference to that instance. If the count drops to zero, then it is assumed that the chip instance is a duplicate in override tree and has a similar instance that is already overriden in base device tree. ref_count is currently decremented whenever a device in override tree matches the one in base device tree and the registers from the override tree instance are copied over to the base tree instance. On the other hand, if a device in override tree does not match any device in base tree under a given parent, then the device is added to base tree and all the devices in its subtree that hold pointers to its parent chip instance are updated to point to the parent's chip instance in base tree. This is done as part of update_chip_pointers. However, there are a couple of issues that this suffers from: a) If a device is present only in override tree and it does not have its own chip (i.e. pointing to parent's chip instance), then it results in sconfig emiiting parent's chip instance (which can be the SoC chip instance) in static.c even though it is unused. This is because update_chip_pointers() does not call delete_chip_instance() before reassigning the chip instance pointer. b) If a device is added under root device only in the override tree and it does not have its own chip instance (i.e. uses SoC chip instance), then it results in sconfig emitting a copy of the SoC chip instance and setting that as chip_ops for this new device in the override tree. In order to fix the above issues, this change drops the ref_count field from chip_instance structure and instead adds a forwarding pointer `base_chip_instance`. This is setup as per the following rules: 1. If the instance belongs to base devicetree, base_chip_instance is set to NULL. 2. If the instance belongs to override tree, then it is set to its corresponding chip instance in base tree (if present), else set to NULL. State of base_chip_instance is then used when emitting chips and devices using the following rules: 1. If a chip_instance has non-NULL base_chip_instance, then that chip instance is not emitted to static.c 2. When emitting chip_ops for a device, base_chip_instance is used to determine the correct chip instance name to emit. BUG=b:155549176 TEST=Verified that the static.c file generated for base/override tree combination is correct when new devices without chips are added only to override tree. Change-Id: Idbb5b34f49bf874da3f30ebb6a6a0e2d8d091fe5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41007 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-07util/sconfig: Move chip instance id assignment to emit_chips()Furquan Shaikh
This change moves the assignment of id for chip instance from new_chip_instance() to emit_chips(). This is similar to the previous change for moving dev id assignment to happen much later. This ensures that the same ID gets assigned to a chip when adding support for device trees which makes it easier to compare static.c files. BUG=b:155549176 Change-Id: I3efa9af5ed91123675be42bce1cb389bad19cb62 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-07util/sconfig: Drop id from struct device maintained by sconfigFurquan Shaikh
This change drops the id field from struct device as used by sconfig. It was primarily used for generating unique device names. This was maintained within device structure so that the order in which the device tree entries were parsed is clear. Since the ids are assigned in parsing order, it is problematic when a device is moved from base devicetree to override tree. The entire parsing order changes which makes it really difficult to compare what really changed in static.c file. By moving the dev name assignment to happen later when doing pass0 of static.c generation, the difference in static.c file is minimized when adding support for override trees. BUG=b:155549176 Change-Id: I31870ace5a2fd7d5f95ab5e30d794c3bc959ed46 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-07soc/amd/common/block/lpc: Use standard pci_dev_ops_pciFurquan Shaikh
AMD common block LPC driver does not really need a custom ops_pci structure. This change drops the lops_pci and instead set .ops_pci to the default pci_dev_ops_pci. BUG=b:154445472 Change-Id: Ia06eed04097739c3e21dc13e056a2120ff5eb382 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-06treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi
This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: move copyrights and authors to AUTHORSPatrick Georgi
Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi
That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-06soc/intel/tgl: Synchronize GPIO ASL table with Linux kernelShaunak Saha
Kernel pinctrl driver changed for Tiger Lake and went to old scheme. Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2116670 BUG=b:151683980 BRANCH=none TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl verify INTC34C5:00 listing all the pins. Cq-Depend:chromium:2116670 Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06soc/intel/tigerlake: Print HPR_CAUSE0 registerderek.huang
In addition to GBLRST_CAUSE0 and GBLRST_CAUSE1, print the value of HPR_CAUSE0. Change-Id: Idc57c3cd6a8d156c5544640898e8e7147d34c535 Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-06elog: Add new elog types for CSME-initiated host resetderek.huang
Change-Id: Iddae1c7cbc71ce10b126a1e05abf9269e8187a38 Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40687 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetreeKarthikeyan Ramasubramanian
BUG=None TEST=Build and boot the mainboard. Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41037 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06mb/purism/librem_skl: select DRIVERS_GENERIC_CBFS_SERIALMatt DeVillier
This driver was previously added for another out-of-tree Librem device, but forgot to switch over the librem_skl boards to use it. Remove duplicate functionality from mainboard.c and delete the empty file. Test: build/boot Librem 13v2 and verify serial number read from CBFS via dmidecode. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Ide952197335c6bfbad846c6d6f62be5c4c57e2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-06mb/purism/librem_{bdw,skl}: select MAINBOARD_HAS_TPM1Matt DeVillier
Current model Librems all have a TPM 1.2 module, so select it at the board level to avoid having to do so in .config. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Iab8b39c39aef2a3fc182f1a50091f84f2151a394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-05sconfig: Allow `register` entries below devices, tooNico Huber
Every device belongs to a chip. And we already keep that relation by inheriting the `.chip_info` pointer if downstream devices don't have another chip specified. So we can also allow to specify `register` settings at the device level. Change-Id: I44e6b95d0cd708fef69b152ebc46b869b2bb9205 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40803 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-05mb/intel/jasperlake_rvp: Configure IP specific GPIOsMaulik V Vaghela
This patch configures all IP related GPIOs as per mainboard schematics. Till now, we were relying on FSP to do IP specific GPIO programming but now we'll program all GPIOs from mainboard. This will remove ambiguity of GPIO programming done by FSP and coreboot will do full GPIO programming Programming GPIOs of following IPs - I2C - Emmc - Display - CPU specific gpio (SLP lines) - Cnvi - SD BUG=None BRANCH=None TEST=compile coreboot and checked that all IP functionality working. Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-05-05soc/intel/jasperlake: Correct the EMMC PCR Port IDRonak Kanabar
Updating EMMC PCR PID from 0x52 to 0x51 for Jasperlake BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP from emmc Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: I17d4e7b7e0fe5e0b18867b6481b5bc9227ae19e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-05soc/intel/jasperlake: Allow SD card power enable polarity configurationRonak Kanabar
SdCardPowerEnableActiveHigh is a UPD which controls polarity of SD card power enable pin. Setting it 1 will set polarity of this pin as Active high. This patch will allow to control it from devicetree so that it can be set as per each board's requirement. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD value from FSP log Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: Id777a262651689952a217875e6606f67855fc2f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41027 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-05superio/fintek/f81216h: Drop supportKeith Hui
No mainboards use this anymore. Change-Id: I2d58d73eca0be1f4daf9106a1258274486f803a5 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-05soc/intel/tigerlake: Add PMC mux controlJohn Zhao
PMC supports messages that can be used for configuring the USB Type-C Multiplexer/Demultiplexer. BUG=b:151646486 TEST=Booted to kernel on volteer board and verified PMC and Mux agent devices identification. Change-Id: I00c5f929b2eea5de3f8eba794dbe9b36c8083c52 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-05soc/amd/picasso: add Kconfig option to disable rom sharingAaron Durbin
Add a knob for mainboards to request disablement of the SPI flash ROM sharing in the chipset. The chipset allows the board to share the SPI flash bus and needs a pin to perform the request. If the board design does not employ SPI flash ROM sharing then it's imperative to ensure this option is selected, especially if the pin is being utilized by something else in the board design. BUG=b:153502861 Change-Id: I60ba852070dd218c4ac071b6c1cfcde2df8e5dce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146445 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-05soc/amd/common/block/lpc: Add lpc_disable_spi_rom_sharingRaul E Rangel
If a Picasso platform wants to use GPIO 67 it must disable ROM sharing. Otherwise ROM access is incredibly slow. BUG=b:153502861 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia9ab3803a2f56f68c1164bd241fc3917a3ffcf2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-04soc/intel/tigerlake: Update interrupt settingWonkyu Kim
Update interrupt setting based on latest FSP(3163.01) Reference: https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/ ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/ PeiItssPolicyLibVer2.c BUG=b:155315876 BRANCH=none TEST=Build with new FSP(3163.01) and boot OS and login OS console in ripto/volteer. Without this change, we can't login due to mismatch interrupt setting between asl and fsp setting. Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ibf70974b8c4f63184d576be3edd290960b023b1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/40872 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-MSrinidhi N Kaushik
Due to refactoring of Serial IO code in FSP v3163 onwards we need to set SerialIoUartDebugMode UPD in FSP-M to SkipInit so that SerialIoUart initialization is skipped in FSP. This makes sure that SerialIo initialization in coreboot is not changed by FSP. BUG=b:155315876 BRANCH=none TEST=build and boot tglrvp/ripto/volteer and check UART debug logs Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I8ba4b9015fa25a84b6b99419ce4d413c9d9daa44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40899 Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based FSP version 3163. Which includes below additional UPDs: FSPM: -BootFrequency -SerialIoUartDebugMode FSPS: -PcieRpPmSci -PchPmWoWlanEnable -PchPmWoWlanDeepSxEnable -PchPmLanWakeFromDeepSx BUG=b:155315876 BRANCH=none TEST=build and boot ripto/volteer Cq-Depend: chrome-internal:2944102 Cq-Depend: chrome-internal:2939733 Cq-Depend: chrome-internal:2943140 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ida87ac7dd7f5fd7ee0459ae1037a8df816976083 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40898 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04libpayload/drivers/usb/xhci: Allow xHCI v1.2 in libpayloadDossym Nurmukhanov
The latest Intel FSP advertises xHCI v1.2 chipset support, so update libpayload to include that version. No critical changes were identified in review of the xHCI v1.2 spec, and booting from USB works with the included change as expected. BUG=b:155315876 TEST=booting from multiple USB sticks/hubs with the latest Intel FSP that advertises xHCI v1.2 Change-Id: I236fed9beef86ff5e1bf7962d882fdae5817a1ff Signed-off-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41039 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04mb/purism/librem_skl: disable serial console outputMatt DeVillier
Librem SKL/KBL boards do not have an exposed serial port interface. Set board Kconfig so that a default built image with Tianocore payload is bootable and doesn't hang due to trying to send data over a non-existant serial port. Test: build/boot librem 13v4 with board defaults + Tianocore Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I4c3f8a3c1726f804957b06b437b399291854a3f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-04mb/purism/librem_skl: Clean up KconfigMatt DeVillier
Reorder Kconfig selects alphabetically, and select the correct SoC for each variant (even though it currently makes no difference). Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I46f651a530ef0ed617dd1f3eee077e84279a40f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40913 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04mb/purism/librem_skl: rename variant directoriesMatt DeVillier
Since the same variant dirs are used by multiple versions of the same board, drop the v2/v3 labels. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Id913e31ab52043e49769be9d3ebf6e71ecb0c856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-05-04mb/purism/librem_skl: Convert to use override devicetreeMatt DeVillier
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I3dac62a649e12ea2498d3ecafe03fd0d62af5f2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-04payloads/external/GRUB2: Makefile: fix check for changed files againMichael Niewöhner
This fixes the missing closing brace introduced in CB:40953. Change-Id: I295c67ab8d7596bf54cc69d088ef1df906f58d5f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41036 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04Documentation: Update vboot on lenovoPatrick Rudolph
Update the documentation now that CB:32705 is merged. Change-Id: I9845c0750ec4016188478154610400d1b8556793 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40775 Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMeMatt DeVillier
Per the schematics, SRCCLKREQ2# is used for the NVMe and should be enabled. Enable CLKREQ for PCIe RP9, and adjust comments to indicate correct value used per schematic. Test: build/boot Librem 15v3 with NVMe drive, verify drive identified properly and no errors in boot log. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I159cb7ce1f5195d95c0229490c3bbde26edbd375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-04mb/purism/librem_skl: drop SataSpeedLimit restrictionMatt DeVillier
SataSpeedLimit was set to 3Gbps to work around issues which are now known to be the result of incorrect FSP behavior. Since SataPwrOptEnable is now set at the SoC level and ensures the SIR registers are correctly programmed, we can re-enable 6Gbps operation without errors. Test: build/boot Librem 13v2 with both m.2 and 2.5" SATA drives, check dmesg for errors. Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40909 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04soc/intel/skl: always enable SataPwrOptEnableMichael Niewöhner
For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization Registers) when SataPwrOptEnable=0, which currently is the default in coreboot and FSP. Even if FSP's default was 1, coreboot would reset it. This can lead to all sorts of problems and errors, for example: - links get lost - only 1.5 or 3 Gbps instead of 6 Gbps - "unaligned write" errors in Linux - ... At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and purism/librem13v2) SATA is not working correctly and showing such symptoms. To let FSP correctly initialize the SATA controller, enable the option SataPwrOptEnable statically. There is no valid reason to disable it, which might break SATA, anyway. Currently, there are no reported issues on CML and CNL, so a change there could not be tested reliably. SKL/KBL was tested successfully without any noticable downsides. Thus, only SKL gets changed for now. Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04soc/intel/cannonlake: Add DisableHeciRetry to configChristian Walter
Add DisableHeciRetry to the chip config and parse it in romstage. Change-Id: I460b51834c7de42e68fe3d54c66acd1022a3bdaf Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-05-04mb/up/squared: Fix eMMC speed for UP2 with EDK2Patrik Tesarik
Since commit 402fe20e (mb/up/squared: Add mainboard) the UP2's eMMC maximum host speed was reduced to DDR50, because HS200 showed I/O errors in the host kernel. We found out that with EDK2 master the correct Host Speed could not be set properly during EDK2 platform init. Therefore eMMC would not show up for boot device selection. This commit sets the eMMC MaxHostSpeed to the designed max value of the used eMMC on the UP2 board and furthermore drops the override from the ramstage.c. It's already set in the devicetree.cb. Though CRC errors are still visible in EDK II debug logs, no other negative effects have been observed. Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de> Change-Id: I8d53204d8a776efd560fbdea918f83e180813179 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-04soc/intel/common/block/cse: Add boot partition related APIsSridhar Siricilla
In CSE Firmware Custom SKU, CSE region is logically divided into 2 boot partitions. These boot partitions are represented by BP1(RO), BP2(RW). With CSE Firmware Custom SKU, CSE can boot from either RO(BP1) or RW(BP2). The CSE Firmware Custom SKU layout appears as below: ------------- -------------------- --------------------- |CSE REGION | => | RO | RW | DATA | => | BP1 | BP2 | DATA | ------------- -------------------- --------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either RO(BP1) or RW(BP2)). GET_BOOT_PARTITION_INFO - Provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets CSE's next boot partition to boot from. With the HECI API, firmware can notify CSE to boot from RO(BP1) or RW(BP2) on next boot. As system having CSE Firmware Custom SKU, boots from RO(BP1) after G3, so coreboot sets CSE to boot from RW(BP2) in normal mode and further, coreboot ensure CSE to boot from whichever is selected boot partition if system is in recovery mode. BUG=b:145809764 TEST=Verified on hatch Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-04security/vboot: Limit vboot verification code access to only verstageSridhar Siricilla
Make vboot verification code accessible in only verstage. Vboot verification code in vboot_logic.c is being used in verstage. Due to support function vboot_save_data(), so core functionality in vboot_logic.c is made available in romstage. The patch decouples the support function frm vboot_logic.c to limit itself to verstage. BUG=b:155544643 TEST=Verified on hatch Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Id1ede45c4dffe90afcef210eabaa657cf92a9335 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-05-04payloads/external/GRUB2: Makefile: fix checkout hintMichael Niewöhner
The git checkout hint introduced in cb:36343 does not get printed but executed instead. Escape the single-quotes to fix this. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I1277c3788a141b25cd9f22ec0476ee56b64aea4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/40954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-11 06:31:45 +0000