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2021-03-16cbfs: Remove prog_locate() for stages and rmodulesJulius Werner
This patch removes the prog_locate() step for stages and rmodules. Instead, the stage and rmodule loading functions will now perform the locate step directly together with the actual loading. The long-term goal of this is to eliminate prog_locate() (and the rdev member in struct prog that it fills) completely in order to make CBFS verification code safer and its security guarantees easier to follow. prog_locate() is the main remaining use case where a raw rdev of CBFS file data "leaks" out of cbfs.c into other code, and that other code needs to manually make sure that the contents of the rdev get verified during loading. By eliminating this step and moving all code that directly deals with file data into cbfs.c, we can concentrate the code that needs to worry about file data hashing (and needs access to cbfs_private.h APIs) into one file, making it easier to keep track of and reason about. This patch is the first step of this move, later patches will do the same for SELFs and other program types. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16cbfstool: Move alignment/baseaddress handling into cbfs_add_component()Julius Werner
The --alignment flag is currently only handled by cbfstool add, but there seems little reason to not handle it for all file-adding commands (the help text actually mentions it for add-stage as well but it doesn't currently work there). This patch moves the related code (and the related baseaddress handling) into cbfs_add_component(). As a nice side effect this allows us to rearrange cbfs_add_component() such that we can conclusively determine whether we need a hash attribute before trying to align the file, allowing that code to correctly infer the final header size even when a hash attribute was implicitly added (for an image built with CBFS verification enabled). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Idc6d68b2c7f30e5d136433adb3aec5a87053f992 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47823 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Drop invalid MP table filesKyösti Mälkki
If we spot any error in the file, treat it as untested and broken copy-paste. Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16AGESA,binaryPI boards: Move IRQ table programmingKyösti Mälkki
IRQ programming should be done outside (obsolete) MP table generation. Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38564 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16util/cbfstool/ifittool: Remove dead codeArthur Heymans
The 'x' option is not set up in the getopt options. Change-Id: Ib4aa10b0ea2a3f97e8d2439152b708613bcf43db Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-16mb/google/dedede/var/storo: Add USB Port ConfigurationZanxi Chen
Add USB Port into devicetree for storo BUG=b:177389444 BRANCH=dedede TEST=built firmware and verified USB3.0 function is OK Change-Id: I4d5160ff23d2bd386cb33164b580e6d6f3bf30fd Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16vendorcode/mt8192: change to short log macro namesXi Chen
Originally, log macro names are too long, and they use double parentheses style: ((...)), which causes compile or runtime error easily. Now, change them to single parenthesis mode (...), and use shorter name. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: I2959dc1ba0dd40a8fb954406072f31cf14c26667 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16soc/mediatek/mt8192: adjust i2c "tLOW" and "tSU,STO"Daolong Zhu
The i2c actiming with the default reg setting cannot meet spec, so we need to set some regs. 1. adjust the ratio of SCL high and low level, to adjust "tLOW". 2. modify ext_conf reg to adjust "tSU,STO". BUG=b:179000159 TEST=Test on asurada (MT8192), boot pass, timing pass. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51024 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16Update chromeec submodule to upstream masterMartin Roth
Updating from commit id a2390f3c5: 2020-12-01 08:35:44 +0000 - (servo_v4/usb_pd_policy: Reject SNK->SRC power swap if CC_ALLOW_SRC not set) to commit id 1e800ac83: 2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD) This brings in 188 new commits. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c276d7839e0bdbf14ac56f16c231d75a6ea4c3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-16Update arm-trusted-firmware submodule to upstream masterMartin Roth
Updating from commit id a4c979ade: 2020-08-26 14:59:05 +0000 - (Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration) to commit id 7ad39818b: 2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration) This brings in 222 new commits. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id186df36d90563f94f17cc210a6f634adc4ec61e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-16mb/google/dedede/var/blipper: Add camera supportZanxi Chen
Add camera support in devicetree and associated GPIO configuration. BUG=b:181729304 BRANCH=dedede TEST=built blipper firmware and verified camera function is OK Change-Id: I806ec207a454d4383aca093159553b7e618e16b2 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Add codec and speaker amplifier supportZanxi Chen
Add audio codec and speaker amplifier support into devicetree BUG=b:181732574 BRANCH=dedede TEST=built blipper firmware and verified audio function is OK Change-Id: Id4633649b5e0595ed99a40ae35eb54b005154604 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/blipper: Enable touchscreen for blipperZanxi Chen
Add G2 and ELAN touchscreen into devicetree for blipper. BUG=b:181098785 BRANCH=dedede TEST=built blipper firmware and verified touchscreen function is ok Change-Id: Ie0bfc2972fc1a33a6f02495d3976b816209e956b Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16mb/google/dedede/var/sasuke: Configure GPP_B7 as GPO_HIGHSeunghwan Kim
Configuring GPP_B7 as GPO_HIGH. Sasuke doesn't have SAR sensor, GPP_B7 is routed to the LTE module and is kept high so that the LTE module uses the default emission power. BUG=b:180492044 BRANCH=firmware-dedede-13606.B TEST="FW_NAME=sasuke emerge-dedede coreboot" Change-Id: Ib38c649830db2291b3a2a771f5c884acf37dcbeb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51049 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16vendorcode/mt8192: fix fast-k gating PI P1 initializationXi Chen
In RX Gating flow, PI P1 delay is missing, so re-add the initialization. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ic72ccecd205062ee79f6928993fac772fc10f880 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16vendorcode/mt8192: limit fast-k frequency count from 7 to 3Xi Chen
For bootup faster, fast-k elapsed time is improved by ~400ms. Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ifa945012aa66df4433fe63aab75a1e785d343d9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51406 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16mb/google/asurada: fix boot failure when reading SKU IDHung-Te Lin
The SKU IDs also need mapping table when reading voltages. BUG=None BRANCH=asurada TEST=emerge-asurada coreboot Change-Id: Ice91961d6c33cfa27254221663edca1547c9ddcc Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16mb/google/guybrush: Add initial fch irq routingMathew King
BUG=b:181972598 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-15mb/google/guybrush: Enable eSPI VW SCI eventsMathew King
Guybrush does not have a dedicated SCI pin so it uses VW. BUG=b:181134664 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/magolor: Fix DPTF passive and critical policiesKarthikeyan Ramasubramanian
Some of the temperature sensors defined in baseboard do not exist in magolor. With the format the DPTF policies are defined in magolor, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=None BRANCH=dedede TEST=Build and boot to OS in magolor. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I43f0b188e49e24657db055ce898ce159d499a22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15mb/google/dedede/var/madoo: Fix DPTF passive and critical policiesKarthikeyan Ramasubramanian
Some of the temperature sensors defined in baseboard do not exist in madoo. With the format the DPTF policies are defined in madoo, all the entries from the baseboard are included and then the overrides applied. This causes the non-existent DPTF devices to be exported in the ACPI table and in turn OS reading invalid temperatures. Fix the format for DPTF passive and critical policies. BUG=b:182513022 BRANCH=dedede TEST=Build and boot to OS in madoo. Ensure that the DPTF entries look correct in both static.c and SSDT tables i.e. passive and critical policies for applicable devices only are present. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Idc5d0b357d61b9346b4d20ec8322b124c9655b4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Ben Kao <ben.kao@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-FAlexander Couzens
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in difference to the X11SSH-F which only has 2 NICs. The two additional NICs aren't populated on the X11SSH-F. Enable the PCIe root ports connected to the two additional Intel NICs. Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-15mb/prodrive/hermes: Drop AZALIA_PLUGIN_SUPPORTPatrick Rudolph
Already selected by SoC. Change-Id: I1d941881f50350b6b581416a2e722ea2e7485a1c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-15mb/google/dedede/var/sasukette: Add USB2 PHY parametersTao Xia
This change adds fine-tuned USB2 PHY parameters for sasukette. BUG=180753635 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I5612e7dcca15b340763dee1475e979ee551a2146 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15soc/intel/alderlake: Drop 100ms delay and do not poll Link ActiveJohn Zhao
Drop the 100ms delay in the _PS0 method because kernel already adds this 100ms. This change also drops polling TBT PCIe root ports Link Active State because this scheme is not applicable for SW CM. BUG=None TEST=Built Alderlake coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/volteer/variant/lindar: Disable SA GV for Samsung memory with ↵Kevin Chang
wrong date code MB Disable SA GV, because factory used Samsung memory with wrong date code. So we need to use board version to identify build MB phase to disable SA GV. Disable SA GV when board version equal one. BUG=b:179747696 BRANCH=firmware-volteer-13672.B TEST=Built and booted into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15vc/intel/fsp/fsp2_0/cooperlake_sp: Update memory map hob for WW06 FSPJohnny Lin
Change-Id: Id534e1b73e73bbb9d944c988d1ef66bc1f463eff Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50867 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Deomid "rojer" Ryabkov <rojer9@fb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/intel/tglrvp: Enable RTD3 for WWANBora Guvendik
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root Port 4 and provide the reset GPIO / src clk pin. BUG=none TEST=Boot to OS, verify the link is in L2 state during S0ix. Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-03-15mb/google/dedede/var/storo: Support LTE modulechenzanxi
Add LTE module support into devicetree and associated GPIO configuartion. BUG=b:177955524 BRANCH=dedede TEST=LTE function is OK Change-Id: I9aff9608e08eae00ab5ac8547f63bc83b62fea78 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15mb/google/dedede/var/storo:Add P-sensor for storochenzanxi
Add P-sensor into devicetree for storo according to configuration information provided by the vendor. BUG=b:177392203 BRANCH=dedede TEST=built storo firmware and verified P-sensor function Change-Id: Iced4ab7d94b38ef8b1807955cbb887454accb1e8 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-15mb/google/dedede/var/storo: Add codec and speaker amplifier supportchenzanxi
Add audio codec and speaker amplifier support into devicetree BUG=b:179057895 BRANCH=dedede TEST=audio function is OK Change-Id: Ia864ac47223adb80463966209f6ff3640b715378 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51003 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/dedede/var/storo: Add camera supportchenzanxi
To support mipi camera. 1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU 2. add IPU/VCM/NVM/CAM1 into devicetree To support usb camera. add camera support in devicetree and associated GPIO configuration. BUG=b:177393430, b:177388006 TEST=Build and boot to OS. Camera function is OK. Change-Id: I98d5708d1955406c2e46db972903057bb3d12dcc Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50995 Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/lenovo/t440p: update VBT to version 2179Da Lao
Update T440p's VBT from version 1215 to version 2179. Extracted using VBiosFinder (https://github.com/coderobe/VBiosFinder) from the latest bios update file: https://download.lenovo.com/pccbbs/mobiles/gluj42us.iso The new version solves the problem that DP output was broken under Windows. Test: boot t440p with both SeaBIOS and Tianocore payloads, verify dp output and backlight control all works under both Linux and Windows. Signed-off-by: Da Lao <dalao@tutanota.com> Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jamal Wright <Crabstorage@getbackinthe.kitchen>
2021-03-15security/intel/stm/Makefile.inc: Fix typoBenjamin Doron
In both the Kconfig and Makefile in this directory, "STM_TTYS0_BASE" is used. Therefore, fix the typo. Change-Id: Ie83ec31c7bb0f6805c0225ee7405e137a666a5d3 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51206 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang
There is no PCI host interface for this version of CNVi BT. CNVi BT on Tigerlake is an USB device. Change-Id: Ib71a827c36dfac55c3e5ce586b00a26fc6264464 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50900 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flagCliff Huang
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is enumerated. Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/volteer/variants: Disable non-existing BT PCI interface and add BT ↵Cliff Huang
flag Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is enumerated. Change-Id: Ic700021d7a09be63ffc2715f31992257e2e893af Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50898 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/hatch: Update DPTF parameters for genesisKenneth Chan
update the DPTF parameters received from the thermal team. BUG=b:181627614 TEST=emerge-ambassador coreboot Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ied6b71d9285662a70446af2e781b630e184c3b19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joe Tessler <jrt@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang
There is no PCI host interface for Cnvi BT in Alderlake. CNVi BT on Alderlake is an USB device. Change-Id: I3e08c6d6f00e81267dc28c9b37b2dfff5cd75db1 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51352 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/google/brya: Remove BT PCI interface and add BT flagCliff Huang
Remove the CNVi BT PCI config and add Bt flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: I7e8ca1bb6a57721a72478137612d7a9c391ca0b2 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flagCliff Huang
Remove the CNVi Bt PCI config and add Bt flag. There is no PCI host interface in this version of CNVi. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang
This change adds the corresponding CNVi BT Core enabling flag. TEST: BT is checked using 'lsusb -d 8087:0026' from OS. Change-Id: Iecc10c8946a450350adb34b984cf48ad988097ca Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51350 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang
FSP has added the Cnvi BT Core enabling in addition to the existing CnviMode. This change adds the flag at the soc config side (i.e. soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host interface for BT. Therefore, BT core should not use the pci port status to turn on/off. TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make sure BT is turned on. Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d Signed-off-by: Cliff Huang <cliff.huang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15sc7180: make symbols common accross multiple targets.Ravi Kumar Bokka
making the symbols common accross targets to avoid duplicates for each soc. Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: Ic60f46891dfadc7db5ece02756cb449aacdd63c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2021-03-15drivers/generic/alc1015: Change HID name for driverEric Lai
From ALSA reviewer suggest to change the name to RTL1015. Details in below threads: https://www.spinics.net/lists/alsa-devel/msg123395.html BUG=b:177971830 TEST=: ALC1015P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2762852bdc3164346e3618c373aa4d3336415653 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-15drivers/generic/alc1015: Fix missing _DSD and correct property nameEric Lai
Missing acpi_dp_write and correct the name from sdb to sdb-gpios for driver. BUG=b:177971830 TEST: ALC1015P driver can get sdb-gpio properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2728a7dad695d5c97e85c5d86b1effea1595da65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51379 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15mb/ocp/deltalake: Override uart base address via VPD variableBryant Ou
Use VPD of "coreboot_uart_io" to select uart io if OVERRIDE_UART_FOR_CONSOLE is selected. Tested=On OCP Delta Lake, console messages correctly output to uart port which is defined in VPD. Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/45408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-03-15mb/google/volteer: Create collis variantFrankChu
Create the collis variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:182227204 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_COLLIS Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ibcf8b59b38d02517cea0a3ee474ff82fc0a2a958 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-15mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUsMeera Ravindranath
Add support to pick the right vbt from cbfs according to SKU-ID. Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15mb/ocp/deltalake: Override SMBIOS type 2 feature flagsTim Chu
Override SMBIOS type 2 board feature flags. For Delta Lake, board is replaceable and is a hosting board. Tested=Execute "dmidecode -t 2" to check info is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I4469360ec51369dbf8179b3cbac0519ead7f0382 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 11:42:42 +0000