summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2010-03-21drop dead code.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-21fix "make" after "rm -rf build"Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-21Don't abuse LDFLAGS and fix linking with -Wl,--as-needed.Christian Ruppert
Signed-off-by: Christian Ruppert <idl0r@gentoo.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-19I ran into a couple of errors while building a mahogany_fam10 target;Ed Swierk
CONFIG_CAR_FAM10 was renamed some time ago to CONFIG_NORTHBRIDGE_AMD_AMDFAM10, and l3Cache() is actually defined as l3_cache(). Signed-off-by: Ed Swierk <eswierk@aristanetworks.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-19The parameters of memset() should beZheng Bao
memset(addr, value, size), right? It is an obvious bug created at r5201. I am wondering why it doesnt trouble you. I took a quick look at other files and didnt find other calling error. Trailing white spaces are also deleted. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-19Get rid of a few warnings:Myles Watson
1. Add some more prototypes to lib.h 2. Include console.h when not using romcc 3. Eliminate an unused function 4. Set a default for SSE2, since it is just for ramtest performance Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Remove remaining uses ofPatrick Georgi
HAVE_FAILOVER_BOOT HAVE_FALLBACK_BOOT USE_FAILOVER_IMAGE USE_FALLBACK_IMAGE Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Rework boolean expression (DeMorgan and all) forPatrick Georgi
better readability. Also remove failover.c files in mainboards, as they're not used anymore (and useless, too) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18Remove fallback/normal handling in mainboards'Patrick Georgi
romstage.c like r5255 did for failover/fallback/normal mainboards. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18trivial. Delelte double blank line.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17Remove failover/fallback/normal handling in mainboards'Patrick Georgi
romstage.c. That's newconfig stuff. 1. In failover_process(), I removed the fallback/normal selection logic and kept the remaining hardware init in. The if-clauses' conditions are reverted to match. Remove #if failover||fallback guard. 2. Change cache_as_ram_main() to first call failover_process, then real_main unconditionally. 3. Move failover_process's code to the beginning of real_main, remove failover_process and its call in cache_as_ram_main. 4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same arguments, so no problem with that) Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17more warnings gone...Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17revert the faulty part of r5252Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17fix HPET on some ICH southbridgesStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17trivial warning fixes, mostly for ACPI codeStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17drop shadow variable from hypertransport code.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17Actually enable HPETStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17Clean up warnings in yabel vbe code. No more warnings on the IP1000Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17clean up shadow variables in jpeg decoder.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17fix minor warnings in RTC code when HAVE_OPTION_TABLE is disabled.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17bug fix for IOAPIC on i82801dx.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5245 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17This patch fixes up the i82801dx_lpc.c code post transition.Joseph Smith
Boot Tested (bootlog attached) Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17This is kind of a pre CAR patch to properly allocate "shared" graphics memoryJoseph Smith
area. CONFIG_GFXUMA is used in src/cpu/x86/mtrr/mtrr.c which is called by the cpu. Attached is a revised patch which works well. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> See boot snips below: Root Device assign_resources, bus 0 link: 0 8MB IGD UMA Available memory: 581632KB PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 ---------------------------- Adding high table area Adding UMA memory area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 0000000000100000-00000000237effff: RAM 3. 00000000237f0000-00000000237fffff: CONFIGURATION TABLES 4. 0000000023800000-0000000023ffffff: RESERVED git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5243 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17more warning fixes.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17fix HPET base addressed.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5241 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17The SB600 also has the BootFailTimer. We should disable it,Zheng Bao
otherwise it will keeps reboot. The comment was also added in detail to make less confusing when we debug SB600/SB700. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17remove more warnings, and fix some boards (watchdog.h)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17From Keith Hui:Keith Hui
This patch implements a full SDRAM buffer strength programming algorithm in set_dram_buffer_strength(), checked against my P2B-LS factory BIOS. With this in place, I now have 133MHz (!) stability with three 256MB PC133 modules, and can boot Fedora 11 all the way to the init daemon (actually upstart, but that's another story). Not to login prompt yet. We'll find out why later. This again assumes a 4-DIMM board because that's all I have. I need someone with a 3-DIMM board to test it. As a bonus, there's a big comment block within that illustrates the algorithm. :-) Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17fix dell s1850, ROMCC didn't seem to like SSE2 memtest here.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17fix a couple of warningsStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17clean some more files in make cleanStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17remove warnings from cs5530 driver. (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17make clean: delete failover.inc and romstage.inc, drop auto.inc (obsolete)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17drop unused variableStefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17Source all Kconfig files for Intel® CPU models..Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17Catch non-static arrays in romcc. Not allowed.Eric W. Biederman
Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16pci drivers should be const.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5229 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16it was reason for workaround rules already, and it's somewhat ugly:Stefan Reinauer
util/x86emu is the only part of coreboot that is linked into coreboot itself that lives in util/. It's not a utility and it does not really belong where it lives. ---> svn mv util/x86emu src/devices/oprom plus necessary Makefile changes to get it building again Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5228 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Left over strip_quotes definition. Top level MakefilePatrick Georgi
already provides this. Thanks Myles for catching this. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5227 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Strip quotes from COREBOOT_ROM_DEPENDENCIESPatrick Georgi
Macro-ify stripping quotes Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Improve dependency tracking for coreboot.romPatrick Georgi
Improve handling of problems while building coreboot.rom Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Various changes to the buildsystem:Patrick Georgi patrick.georgi
- Single instance of the CC build rule in Makefile, instantiated as necessary - Remove manual static.o and option_table.o rules, they're now covered by those instances of the CC build rule - Normalize object file paths, so it can be $(obj)/option_table.o instead of $(obj)/arch/i386/../../option_table.o now - Add -pipe to compiler flags. It might be detrimental on rare scenarios (building with extremly high disk bandwidth, eg. RAM disk), but it significantly helps on win32 (which seems to cache less aggressively than most unix-alikes) - Silence stderr on hostname and domainname invocations (cosmetic fix for cygwin) - Test for -Wa,--divide functionality of the target compiler (taken from abuild). It might be possible to remove most patches in crossgcc with that. - Report build of failover.inc and romstage.inc Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Delete Config.lb in new southbridge folders.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Add entries of RS780, SB700, Mahogany, Mahogany_fam10 into theZheng Bao
Makefile and Kconfig. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16The code can run on the Mahogany board, which is one of sample boardsZheng Bao
made by AMD. Its major features are: CPU: * AMD AM2+ * AMD Athlon 64 x2 * AMD Athlon 64 FX * AMD Athlon 64 * AMD Sempron CPUs System Chipset: * RS780E * SB700 On Board Chipset: * BIOS - SPI * Azalia CODEC - Realtek ALC888 * LPC SuperIO - ITE8718F(GX). * LAN - REALTEK 8111C * TPM - SLB9635TT1.2 Main Memory: * DDR II * 4 (Max 4GB) Expansion Slots: * PCI Express X16 slot*2 (PCI-E X8 Bus) * PCI Express X4 Slot*1 Intersil PWM: * Controller - Intersil 6323 Note: 1. The only difference to mahogany is the CPU is changed to K8 family 10. 2. The main structure of the code is based on serengeti_cheetah_fam10. I am a rookie to fam10. I am still confused about CONFIG_HT_CHAIN_UNITID_BASE and CONFIG_HT_CHAIN_END_UNITID_BASE. I set them as the way dbm690t does. And I have to modify the some fam10 code (see the patch ht_chain_unitid_base.patch). I dont know how to solve this. Please help. Updated findings: In h3finit.c, the code goes the AMD_CB_ManualBUIDSwapList(). The swaplist is {0x00, 0x00, 0xFF, 0x00, 0xFF}. I am trying to find the meaning of the list. The amdht wrapper needs to modify definitely. 3. With fam10 processor, the HT link can work in HT3. 4. The ACPI _PSS table is set staticly. The auto configuaration process doesnt seem to work correctly. 5. Currently the fam10 code in coreboot doesn't support DDR3. If you happen to get a board with DDR3 and you don't have the patience to wait, please find another board with DDR2. 6. It will take "Uncompressing image to RAM" about 1 minute. I know it is a issue for a long time. I disable the compressing currently. When the problem is fixed, we can re-enable it. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-161. Features of mahogany.Zheng Bao
The code can run on the Mahogany board, which is one of sample boards made by AMD. Its major features are: CPU (only K8 system): * AMD AM2+ * AMD Athlon 64 x2 * AMD Athlon 64 FX * AMD Athlon 64 * AMD Sempron CPUs System Chipset: * RS780E * SB700 On Board Chipset: * BIOS - SPI * Azalia CODEC - Realtek ALC888 * LPC SuperIO - ITE8718F(GX). * LAN - REALTEK 8111C * TPM - SLB9635TT1.2 Main Memory: * DDR II * 4 (Max 4GB) Expansion Slots: * PCI Express X16 slot*2 (PCI-E X8 Bus) * PCI Express X4 Slot*1 Intersil PWM: * Controller - Intersil 6323 2. The ACPI feature is already added. I suggest that firstly we can test the board without the ACPI by setting the HAVE_ACPI_TABLE as 0. With Rev F processor, the HT link can only work in HT1, whose max frequency is 1GHz. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Features supported in RS780 code:Zheng Bao
* PCIe initialization. * Internal Graphics initialization. * HT Link initialization. It works in HT1 or HT3 mode. Note: 1. I tried to add the description of every step to the code. For example, if it is made based on rpr, section 2.4.5, I will pasted the words from 2.4.5 to the c code. But the document I worked with might be different with the most updated one. A new section has been added and the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I correct every comment if I met one. But I have to confess that I am so reluctant to find out everyone. I believe it will be correct in the long run. 2. The interanl graphics part is done by Libo Feng <libo.feng@amd.com>. 3. There is a conflict between RPR and our CIM code. Please see the comment in switching_gppsb_configurations in rs780_pcie.c. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Features supported in SB700 code:Zheng Bao
* SATA initialization. * USB initialization. * HDA initialization. * LPC initialization. * IDE initialization. * SMBUS initialization. Note: 1. I tried to add the description of every step to the code. For example, if it is made based on rpr, section 2.4.5, I will pasted the words from 2.4.5 to the c code. But the document I worked with might be different with the most updated one. A new section has been added and the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I correct every comment if I met one. But I have to confess that I am so reluctant to find out everyone. I believe it will be correct in the long run. 2. I only test the SATA port 0-3. The ports 4, 5 are "PATA emulations". I am confused about it. 3. This patch is not only about SB700. Actually it should be SB7x0. But I dont think it is nice to change everything to SB7x0. It is ugly, isn't it. As far as I know, they all use the same code with revision checking. If you guys think it is appropriate, please modify it to sb7x0. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-161. This patch is about the pci header of RS780 and SB700. It is madeZheng Bao zheng.bao
seperatedly because both RS780 and SB700 will modify the pci_ids.h. It maybe will cause conflict if the sequence the patches are applied is different with the one they are created. 2. Dev 0-10 of RS780 has AMD's Vendor ID. So we think it is better to define the Device ID as XXX_AMD_RS780_XXX. Does anyone think it is better to move this definition to the AMD zone? That will split the RS780 into two parts. Is it inappropriate? Signed-off-by: Zheng Bao <zheng.bao@amd.com Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5217 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-16Make CLANG selectable in KconfigPatrick Georgi
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5216 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-12 04:11:20 +0000