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2011-10-30crossgcc: Fix colors with dashPatrick Georgi
Ubuntu (and probably other distros) have dash as /bin/sh, which doesn't display colors by itself. If /usr/bin/printf is found, it's used instead of the internal printf to re-enable colors. Change-Id: I3e6d413cd0c8a46ef91821d8c07e88166de58af4 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/352 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-30Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9Rudolf Marek
It is meant to be a address and not a dereference. Otherwise MTRR is filled with code and not with the address. This is what I hate at most on the AT&T syntax. Instead of taking the address, it was a dereference. Not greatly visible, except I wondered why opcode is not 0xb4 but 0xa1 and it took another half an our to see it. Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/358 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2011-10-30Fix gcc 4.6.1 breakage of southbridge/amd/sr5650/pcie.c.Stefan Reinauer
Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/360 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-10-30inteltool: Add Intel i63xx I/O Controller HubSven Schnelle
Change-Id: Iaea7e4d1b206d43661ecb61d2ae517723fb8d008 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/356 Tested-by: build bot (Jenkins)
2011-10-30remove usbdebug.h include from mainboard/romstage codeSven Schnelle
No romstage is supposed to use usbdebug functions/defines directly, so remove all those includes. The usb code is now called and setup from console code. Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/354 Tested-by: build bot (Jenkins)
2011-10-30Update coreboot cross toolchain to gcc 4.6.1Stefan Reinauer
- Tested on Mac OS X 10.7.1 - Tested on Ubuntu 10.04 LTS (Lucid Lynx) - Tested on Ubuntu 11.10 (Oneiric Ocelot) Please test on Windows and other Linux distributions Change-Id: I132c01293fc0cff0cfb84556a93c0b8de8e57230 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/250 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-10-30asus/m5a88-v: Fix buildPatrick Georgi
We added some new flag for certain AMD boards after support for this board was submitted. Also integrate the mptable refactorings that happened in the meantime. Change-Id: I50cf50f343a740832fd1a14a2a1ef5b903315675 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/353 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-10-29Fix coreboot updatesPatrick Georgi
The rule to prepare a new coreboot.pre1 was ignored in the "update image" scenario because a perfectly fine file exists. Mark it phony to fix it. Change-Id: Ie7f8b36b71015a593958cd6e19602bad6b854320 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/351 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28w83627hf: add method to retrieve wake event source register to ASL includeChristoph Grenz
Add a method WAKS to devtree.asl which returns the wake-up source register to simplify retrieving the wake source e.g. in \_WAK. Change-Id: Ia258f8fc9ff79b18391c55464da73863889e2255 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/297 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Add ASUS M5A88-V mainboard supportQingPei Wang
it's a AMD 880+800 mainboard. I port the code based on the AMD reference code. update: 1.use CIMX instead of pmio 2.fix some whitespace 3.fix subsystemid of devicetree.cb Change-Id: I9725ccdbb25365c4007621318efee80b131fec29 Signed-off-by: QingPei Wang <wangqingpei@gmail.com> Reviewed-on: http://review.coreboot.org/205 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Get rid of the old romstage-as-bootblock ROM layoutPatrick Georgi
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n. This might break a couple of boards on runtime, but so far, fixes were quite simple. There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be adapted. Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/320 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Get rid of AUTO_XIP_ROM_BASEPatrick Georgi
That value is now generated from a code address and CONFIG_XIP_ROM_SIZE. This works as MTRRs are fully specified by their size and any address within the range. Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/348 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28sb600: Implement EHCI workaroundPatrick Georgi
Linux implements it itself, but older Linuxes and other systems might not. Without this, the host controller might not respond to drivers. Change-Id: I4ff0e3683c02e7aa00d188428847c64c4c5d589d Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/345 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28siemens/sitemp_g1p1: Add more devices to PIR and MP tablePatrick Georgi
Linux 2.4 is happier that way Change-Id: I016609ae1e004ec856e8223893352dcdd061b291 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/346 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Clear improper use of CONFIG_CACHE_AS_RAMKyösti Mälkki
Choice between printk/print_ is related to CAR, but really depends whether we compiled with GCC or ROMCC. Change-Id: I9fe831a215736462e8b3f4b96ffe231133ecf79b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/347 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28T60: remove redundant usbdebug_init call()Sven Schnelle
called from console code, no need to call it here. Change-Id: I4c34f89c82cc2478db8de4e98584e69d7ab0ca82 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/350 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28copy e7501 component to e7505Stefan Reinauer
Change-Id: Ie69a6b6a040a8b0e7693083b3a2d13c327a165b3 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/310 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-28Prevent multiple inclusions of object files and rulesPatrick Georgi
This removes 54 make warnings from the build Change-Id: I94ac9875526febe2f95334c1c3971641c1d27f8f Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/338 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28Fix checksum calculation both in romstage and ramstage.Stefan Reinauer
The earlier fix for CMOS checksums only fixed the function rtc_set_checksum, which would fix the checksum, but then coreboot would no longer honor the settings because it assumed the checksum is wrong after this. This change fixes the remaining functions. Change-Id: I3f52d074df29fc29ae1d940b3dcec3aa2cfc96a5 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/342 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-27Add support for AMD IMC controller.Rudolf Marek
This patch adds support to dump SIO like interface of AMD Embedded Controller in the SB7xx and SB8xxx southbridges. Parts of the register interface are documented in SBxxx RRG BDG. Change-Id: Ib2ccaa3dfe33cfa8e7cba19d8ab0798286ad2f92 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/343 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-10-27Added smbus block read/write for amd8111Oskar Enoksson
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Change-Id: I86c80a27fd13c9a2be4034fdfb63be4ab2fadbfc Reviewed-on: http://review.coreboot.org/281 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27Move linux 2.6.11 workaround to generic codePatrick Georgi
Linux 2.6.11 seems to require a certain order in CPUs listed in mptable, so enforce it. This was only done on arima/hdama, but now is generic. Unfortunately this is somewhat slow. Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/280 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27X60/T60: enable AHCI modeSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Change-Id: I2166ae9ee9e7e0e431583249f015d130d15fac61 Reviewed-on: http://review.coreboot.org/341 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27i82801gx: Fix port status in AHCI modeSven Schnelle
The code used PCI register 0x92 to enable sata ports, which is wrong. The ICH7 documentation states: "This register is only used in systems that do not support AHCI. In AHCI enabled systems, bits[3:0] must always be set (ICH7R only) / bits[2,0] must always be set (Mobile only), and the status of the port is controlled through AHCI memory space." Writing 0x0f to ICH7-M doesn't seem to hurt, so lets write 0x0f for both variants. This patch makes sata_ahci work on my Thinkpad T60 and X60s. Change-Id: If3b3daec2e5fbaa446de00272ebde01cd8d52475 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/340 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-27Add -Werror to xcompile's testccStefan Reinauer
If -Werror is not specified, tests for certain compiler flags will emit a warning, which makes the build break since we compile with -Werror. Change-Id: I7be56530ff9f94e5500bad226c83e47145a808d7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/336 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-27Fix libpayload speaker driverStefan Reinauer
The frequency for the PC speaker has to be specified as 1193180 / frequency according to http://wiki.osdev.org/PC_Speaker Change-Id: Iaca9d45807e080efe834611e719b350680b5fb90 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/337 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25X60: enable Cx power saving modesSven Schnelle
Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/331 Tested-by: build bot (Jenkins)
2011-10-25T60: add _CST tableSven Schnelle
Used by power management code to enable Cx powersaving modes. Change-Id: I02c6b10762245bc48f21a341286236e203421de0 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/322 Tested-by: build bot (Jenkins)
2011-10-25T60: enable C4onC3 modeSven Schnelle
It is safe to enable this setting on these Boards. Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/330 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25T60: use ICS954309 clock driverSven Schnelle
Change-Id: I3f30fe601215784e1688c5ec51108dc0cf03e320 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/328 Tested-by: build bot (Jenkins)
2011-10-25Add driver for ICS954309 clock generatorSven Schnelle
Change-Id: Iac7e91cdd995dad1954eaa2d4dd52bffa293fc95 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/327 Tested-by: build bot (Jenkins)
2011-10-25i82801gx: Add setting for C4onC3 modeSven Schnelle
If this bit is set, ich7 will enter C4 mode if possible instead of C3. See ich7 specification (LPC controller, Power management control registers) for more details. Change-Id: I352cccdbc51ff6269f153a4542c7ee1df0c01d22 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25SPEEDSTEP: write _CST tablesSven Schnelle
Change-Id: Idb4b57044808918de343d31519768d0986840f01 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/321 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25ACPI: Add function for writing _CST tablesSven Schnelle
Change-Id: I4e16a0d37717c56a3529f9f9fdb05efec1d93f99 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/312 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25w83627hf: correct typo in ASL include, correct indexed registers and remove ↵Christoph Grenz
unneccesary _PR0 defs Correct a typo in devtree.asl which causes AML processors to fail executing the DSDT with AE_NO_MEMORY or (in case of acpiexec) Divide By Zero. Also removes an superfluous item in the register IndexField and removes unneccessary _PR0 definitions which could confuse AML processors. Change-Id: I02cb9ce4e8f2101cfff8cec4abba7e070fd66364 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/296 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25Lenovo H8: Fix h8_set_audio_mute()Sven Schnelle
Logic is inverted (if argument is true, one would expect that mute is enabled) and the wrong bit was used (1 instead 0) Change-Id: I71133ba639f1fb0d3c3582f16211dd266a11cc64 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/334 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25X60/T60: remove superflous h8_set_audio_mute()Sven Schnelle
muting is handled by h8 code, no need to do it here. Change-Id: I3f152e99f30701cd032b03105cbe3ae778865305 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-25i82801gx: Add write and read/write block functionsSven Schnelle
Change-Id: Icbfc47a8d7bfe1600e4212b26e99b2a604de9ef7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/326 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-24Various fixes to cbfstool.Stefan Reinauer
- add ntohll and htonll (as coreboot parses 64bit fields now) - use the same byte swapping code across platforms - detect endianess early - fix lots of warnings - Don't override CFLAGS in Makefile Change-Id: Iaea02ff7a31ab6a95fd47858d0efd9af764a3e5f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/313 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-23i82801gx: Don't set I/O base address to static valueSven Schnelle
Doing it this way will break all subsequent smbus calls, because the smbus code still uses res->base, which points to the old base address. Fix this by allocating a proper resource. Change-Id: I0f3d8fba5f8e2db7fe4ca991ef2c345aff436ea4 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/325 Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2011-10-23FILO: Pass LIBCONFIG_PATH variable to FILOs makeThomas Gstädtner
This fixes the build for HEAD/master. Current stable will not work, because it is too old for recent corboot. Change-Id: I9dfd5de472d4f58f07147cb9b9bb0b543f228561 Signed-off-by: Thomas Gstädtner <thomas@gstaedtner.net> Reviewed-on: http://review.coreboot.org/311 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-23Allow XGCCPATH to be set on the make command line.Marc Jones
The xgcc toolchain may be moved by the user and passed in on the commandline. Updates the Makefile and the xcompile script. Change-Id: I05797b2cabce39bdd7868c2515f30d34043fc8cc Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/318 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-23console: support integrated 7-segment displays for POST codesChristoph Grenz
Add a configuration option POST_PORT which defaults to 0x80 and can be redefined by boards which have integrated POST displays on another I/O port. Change post.c to output POST codes to this port instead of 0x80 hardcoded. Change-Id: I8f8e820f8c75641b35e7249bf622b63a3604b9f3 Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de> Reviewed-on: http://review.coreboot.org/221 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-23SB800: Hide unused gpp portsKerry Sheh
Add configure option SB_GPP_UNHIDE_PORTS for mainboard to hide/unhide the unused sb800 gpp ports. Certain gpp port should be hidden, if no device was detected and hotplug feature is disabled for such port. Hidden unused ports makes lspci -vvv get more accurate information under Linux. Test on avalue/eax-785e mainboard. Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-22Fix CMOS checksum calculation in libpayload.Stefan Reinauer
Change-Id: I64ea53fa098fbcfc76e0ebd5f049a2ee3d0a1024 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/314 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-22Add ifdtool, utility to read / modify Intel Firmware Descriptor imagesStefan Reinauer
Change-Id: Ie78b97bf573d238d0dff9a663e774deb1b7dea44 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/272 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-22nvramtool: Fix CMOS checksum to match coreboot (and /dev/nvram)Stefan Reinauer
Change-Id: I28b0dbad36403a31be83581107f40b3ca1332dcc Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/287 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-21Extend coreboot table entry for serial portsStefan Reinauer
Add information about memory mapped/io mapped base addresses. and fix up libpayload to use the same structures Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb Reviewed-on: http://review.coreboot.org/261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-21Remove redunancy in KconfigKyösti Mälkki
Socket Kconfig unconditionally selects CPU_INTEL_CORE. Change-Id: I5eb7dd17047a2a031dd7345390d7f5f756055e18 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/307 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-21FILO: Change FILO Makefile.inc from SVN to GITThomas Gstädtner
This commit replaces the old svn checkout code for the external FILO payload with a git checkout for the new repo on gerrit. The stable checkout is implemented similarly to the former SVN variant, it checks out a specific commit (same commit as svn r136 which was checked out before). The HEAD checkout gets the master branch from http://review.coreboot.org/p/filo.git In future this should probably be changed to a stable tag or repo. It is necessary to remove the old svn checkout by hand (or run distclean), because I did not include code to remove an existing svn FILO checkout. Change-Id: I08a703f3428ae7b987f7079a4901be4cf6d7e505 Signed-off-by: Thomas Gstädtner <thomas@gstaedtner.net> Reviewed-on: http://review.coreboot.org/308 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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