summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2016-10-16soc/intel/skylake: Enable HECI BAR for ME communicationSubrata Banik
This patch programs and enables BAR for ME (bus:0/ device:0x16/function:0) device to have early ME communication. BUG=none BRANCH=none TEST=Verified Global Reset MEI message can able to perform platform global reset during romstage. Change-Id: I99ce0ccd42610112a361a48ba31168c9feaa0332 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-16soc/intel/skylake: Select VBOOT_EC_SLOW_UPDATE if EC_GOOGLE_CHROMEEC is selectedNaresh G Solanki
VBOOT_EC_SLOW_UPDATE should be selected if EC_GOOGLE_CHROMEEC is used as building coreboot with Chrome OS support & without Chrome EC gives a build error in coreboot. Change-Id: I77eed0e1bdc1ba49381b72e21b0e18f573cadff0 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17020 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-16soc/intel/apollolake: clear PMC registersAaron Durbin
The clearing of the PMC registers was not being called resulting in state persisting across reboots. This state is queried and events are added to the eventlog like 'RTC reset' events. However, the RTC reset event is a one time thing so it should only be logged once. Without the clearing of the state the event was logged on every boot. BUG=chrome-os-partner:58496 Change-Id: I60aa7102977c2b1775ab8c54d1c147737d2af5e2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17027 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-15nb/i945/gma.c: correct VSYNC end offsetArthur Heymans
According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" the VSYNC end should start at bit 16. This is also how Linux (at least 4.4) sets this register, which can be seen with intel-gpu-tools. TESTED on Lenovo thinkpad X60 (it does not change anything). Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17015 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-15MAINTAINERS: Add Jonathan Neuschäfer as RISC-V co-maintainerJonathan Neuschäfer
Change-Id: I53ba5ba790ae683082e712dc0b92f1ac5bf27ddb Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16990 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-15MAINTAINERS/RISCV: Cover mb/emulation/spike-riscvJonathan Neuschäfer
Change-Id: Id5f3f7f25041189d137ef4daa9f63a3b478763bc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16988 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-15RISCV: change make-spike-elf to use the coreboot toolchain.Ronald G. Minnich
Change-Id: I81ced8c6e02b00a3835e3b42c9cf2669b1b2bd3e Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> [jn: Added XGCC_BIN variable to avoid requiring the tools in $PATH] Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16955 Tested-by: build bot (Jenkins)
2016-10-15arch/riscv: Visually align trap frame informationJonathan Neuschäfer
The pointers printed on unaligned memory accesses are now aligned to those printed at the end of print_trap_information. Change-Id: Ifec1cb639036ce61b81fe8d0a9b14c00d5b2781a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16983 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-15[WIP] console/Kconfig: Calculate COM port base addresses only on x86Jonathan Neuschäfer
On other architectures, the serial ports aren't mapped at 0x3f8. WIP: I'm not sure how exactly the dependency should be encoded in Kconfig. Change-Id: Ia1de545325a53607f62d08e76b2f61b25edbe6ef Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16982 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-15riscv: Use the generic src/lib/bootblock.cJonathan Neuschäfer
TEST=Compiled for and ran on spike; it booted as before. Change-Id: Id173643a3571962406f9191db248b206235dca35 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16995 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-15arch/riscv: Remove unused bootblock_simple.cJonathan Neuschäfer
Change-Id: Id30463d1809d0a31c9d3825642dce66f3ab2750d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16986 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-15riscv: Clean up {qemu,spike}_utilJonathan Neuschäfer
spike_util.h: - (LOG_)REGBYTES and STORE are already defined in arch/riscv/include/bits.h. - TOHOST_CMD, FROMHOST_* are helper macros for the deprecated Host-Target Interface (HTIF). qemu_util.c: - mcall_query_memory now uses mprv_write_ulong instead of first translating the address and then accessing it normally. Thus, translate_address isn't used anymore. - Several functions used the deprecated HTIF CSRs mtohost/mfromhost. They have mostly been replaced by stub implementations. - htif_interrupt and testPrint were unused and have been deleted. spike_util.c: - translate_address and testPrint were unused and have been deleted. After this commit, spike_util.c and qemu_util.c are exactly the same and can be moved to a common location. Change-Id: I1789bad8bbab964c3f2f0480de8d97588c68ceaf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16985 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-15riscv and power8: Convert printk/while(1) to dieJonathan Neuschäfer
Change-Id: I277cc9ae22cd33f2cd9ded808960349d09e8670d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-13vboot: Stop creating backup space in TPMDaisuke Nojiri
There is no code which uses the backup space in TPM created for vboot nvram. All chromebooks currently supported at the trunk store vboot nvram in flash directly or as a backup. BUG=chrome-os-partner:47915 BRANCH=none TEST=emerge-samus coreboot Change-Id: I9445dfd822826d668b3bfed8ca50dc9386f2b2b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5cee2d54c96ad7952af2a2c1f773ba09c5248f41 Original-Change-Id: Ied0cec0ed489df3b39f6b9afd3941f804557944f Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/395507 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://review.coreboot.org/16997 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-13gitconfig: Allow user name and email to be in includesDaisuke Nojiri
This patch adds '--includes' option to 'git config --global' command to allow user name and email to be defined in a file included from the global gitconfig (~/.gitconfig) file. BUG=none BRANCH=none TEST=make gitconfig with ~/.gitconfig including another file which defines user.name and email. Change-Id: I4fe61078b143c3a2e26b0be69c3ca8e6f069d8b0 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/16912 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-13coreinfo: make the CBFS list scrollableBen Gardner
This enables viewing more than ~20 files in the file list on the left. Arrows are added to indicate that more items are available off-screen. This mimics what was done in pci_module. Change-Id: Idd1363e1abe98ba51c795879db061cc54808da8e Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14546 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-13x60,t60: do not add etc/ps2-keyboard-spinup for non-seabios payloadsArthur Heymans
Regardless of the payload chosen a file etc/ps2-keyboard-spinup is added to cbfs. With this fix this file is only added to cbfs when seabios is choses as a payload. Change-Id: I37cf4c998856db2d297356776752643dba46a8f8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16146 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-12i945/gma.c: Only init LVDS if it is detectedArthur Heymans
Some devices have no LVDS output but if no VGA is connected or no EDID can be found, it will try to init LVDS. This patch detects the presence of an LVDS panel and makes sure that LVDS is not initialized when it is absent. Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16513 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11src/cpu: Fix location for cpu_microcode_blob.bin in COREBOOT CBFS onlyBarnali Sarkar
The CPU_MICROCODE_BLOB_CBFS_LOC should only be specified for COREBOOT CBFS, not for other CBFS. BUG=none BRANCH=none TEST=Built and boot kunimitsu Change-Id: I58bb289e6c9add2647876ef817b7920f6e7b427a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16932 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11nb/gm45/gma.c: use linux code to compute LVDS dotclock divisorsArthur Heymans
This reuses linux code (at least 4.1) to compute the graphic clock divisors for LVDS displays on the gm45 northbridge. The divisors m1, m2, n, p1, p2 need to be such that "BASE_FREQUECY * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / (p1 * p2)" is as close as possible to the target_frequency. On g4x hardware the BASE_FREQUENCY is 96000kHz. This potentially increases LVDS display compatibility. Change-Id: I2323af5756431e89769f95059790f5a922af14b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16741 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-11nb/intel/*/graphic_init: use sizeof instead of hardcoding edid sizeArthur Heymans
Change-Id: I2b8c4ef75cca9f9d5251789cda4187a02076b69d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16964 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11lenovo/x60: CST table: use MWAIT requests instead of P_LVLx I/O readsArthur Heymans
Requesting low power acpi cpu c-states has two software interfaces: Using P_LVLx I/O reads or using equivalent MWAIT requests. This change makes it more consistent with newer targets that use MWAIT requests. There also exists extended intel acpi c-states which can be enabled in two ways: - using a substate hint to the mwait request (defined in bios); - setting a model specific register (msr) Currently this is done by setting the right msr bits but with this change one can experiment by adding substate hints. Change-Id: I9eeb5b008e2ddc2193725667f2c13582a4877e3c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14801 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-11southbridge/nvidia: Remove commented codeElyes HAOUAS
Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16899 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11mainboard/apple: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I81c32c618627507cc3a83f60f565a73e5e6d7a13 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16913 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11mainboard/aopen: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I0014fc030888d71f7951c97bccc7cef0e1c45186 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16922 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11i945/raminit.c: correctly write CLKCFG for 945GCArthur Heymans
MHCBAR(CLKCFG) was previously incorrectly written by the sdram_program_memory_frequency function which required falsely limiting the max dram frequency for 945GC. TESTED on Intel d945gclf (memclock 667 and fsb 533) and Gigabyte ga-945gcm-s2l (memclock 667 and fsb 1067) Change-Id: I520efd69fa09fc9fde87c5301fd81121fde6a700 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2016-10-11cpu/intel/smm: Use CONFIG_SMM_TSEG_SIZENico Huber
An epic battle to fix Nehalem finally ended when we found an odd mask set in SMRR. This was caused by a wrong calculation of TSEG size. It was assumed that TSEG spans the whole space between TSEG base and GTT. This is wrong as TSEG base might have been aligned down. TEST: On X201, copied 1GiB from usb key to sd-card and verified. Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7 Found-by: Alexander Couzens, Nico Huber Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16939 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-10intel/i945: Use "IS_ENABLED" for fsbclk & memclkElyes HAOUAS
Change-Id: I3213a8664955239b10bcf1784ce1ba5e0d95688b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16958 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2016-10-10util/scripts: add gerrit-rebase scriptPatrick Georgi
gerrit-rebase is a gerrit-context aware rebase script. Given a source and a target branch (that need to have a common ancestor), it prepares a rebase todo list that applies all commits from source that aren't already found on target. It matches commits using Reviewed-on lines in the commit message that are added by gerrit when submitting commits using the "cherry-pick" strategy. This has been shown to be the best preserved meta data to work from in existing data (Change-Id was mangled in all kinds of ways). Change-Id: I9618c1b66ebc1fb7ed006efbc1665fb08386e1a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16695 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10gigabyte/ga-g41m-es2l: add VESA mode to KconfigArthur Heymans
This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and vesamode in menuconfig. Change-Id: I84b61118fa0419d49d2498b66029711cdce97576 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16501 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10x4x/gma.c: Add VESA native resolution modeArthur Heymans
This patch implements native resolution, VESA mode, on the VGA output of x4x. It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ 60Hz) if this is no EDID could be found. This fallback mode only works in textmode since in VESA mode some payloads (grub2) rely on VBE info, which is being generated from an EDID. Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16498 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10ifdtool: don't write unused regions into a layout fileAlexander Couzens
flashrom treats them as invalid because start > end. Change-Id: I1c8b4563094823ebd9b1193b91e7b4a748955228 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16936 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10mainboard/advansus: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: Ib44bc66e02901dbde14361091a049f71c3ecb840 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16921 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-10-10mainboard/avalue: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I416d3c212653260a28cb07ed86fda34b736ba4ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16926 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-10-10google/reef: update timing of sdmode togglingSathyanarayana Nujella
Maxim98357a speaker amp requires BCLK & SFRM to be active and stable before it is unmuted. If there is a BLCK and no SFRM, it results in a pop sound. sdmode_delay property already exists which facilitates this configuration. This patch updates "sdmode_delay" to avoid pop sound. BUG=chrome-os-partner:58356 BRANCH=None TEST=while audio playback via headset, remove headset. Audio will be switched playback to speaker. Observe if pop sound comes from speaker. Change-Id: I7ad68caa88d7b3ff52ac1379fe6564de27d97777 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/16933 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-10Makefile.inc: Fix make gitconfig for blobs repoNico Huber
It's `.git/modules/3rdparty/blobs` now. Change-Id: Ief12bb934332375a20f150afb568aef266924c9f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/16946 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-10northbridge/intel/nehalem: Remove commented codeElyes HAOUAS
Change-Id: I2d40049a27f725f14acbc16438f0e6ea7cdd7329 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16879 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10northbridge/intel/i440bx: Remove commented codeElyes HAOUAS
Change-Id: I0dd8c32f1b9165fe8c449cee1c21a155a725c04f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16878 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09mainboard/kontron: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I53a0344686921012f4e031842b5108aa4a7b79b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16908 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09mainboard/artecgroup: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: Ia1e7f558bbc44001358339a522e59a2ef7c420fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16923 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4EArthur Heymans
The datasheets "Intel® Core™ Duo Processor and Intel® Core™ Solo Processor on 65 nm Process" mentions cpu C-states substates which can either be attained by adding a substate hint to the MWAIT/P_LVLx request or automatically by setting some msr bits correctly. This just sets the same msr bits as model_6fx to enable dynamic L2 cache, C2E and C4E acpi cpu states. The result is that when limiting a thinkpad x60 with a yonah T2400 cpu to the acpi cpu C2 state, the idle power usage drops from 18W to 14W. When the lowest C-state is set to C4 the idle power usage seems to remain similar. Change-Id: I6c422656ace04659f32082a5944617eda6c79ec3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16901 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09src/northbridge/via: Remove commented codeElyes HAOUAS
Change-Id: Ic589b26c6c94df12e1fe218d079018db8b38fbd9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16898 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family15*: Remove commented codeElyes HAOUAS
Change-Id: If372655700c18340d51368a39392560f664f4a45 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family14: Remove commented codeElyes HAOUAS
Change-Id: I04fe6b7a8798d0f3cb54130283ce5a50eb9ac5b4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16895 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdk8: Remove commented codeElyes HAOUAS
Change-Id: Ifd6aefa6c046d100a5388a24a7d23cbd77905a85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16893 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09libpayload: mvmap2315: Introduce timer driverHakim Giydan
Testing: booted successfully. Change-Id: I4a50c9fb7aec929ea29a3cf2eec3e424e3629c92 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16692 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-09northbridge/amd/lx: Remove commented codeElyes HAOUAS
Change-Id: I37c1674ee380936aba797e24897593fcca3b0269 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16891 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/pi/00730F01: Remove commented codeElyes HAOUAS
Change-Id: I930c761b9a2422590af3a0a5008b4ff2abe3fd96 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16890 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/amdmct/mct_ddr3: Remove commented codeElyes HAOUAS
Change-Id: I2a52db28353f8575d11218af936b4a233fd05f77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16889 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09northbridge/amd/agesa/family16kb: Remove commented codeElyes HAOUAS
Change-Id: Ic22f8a00e6009e104df8c4374067369ebbf90ee2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16888 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 07:35:26 +0000