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2015-03-23chromeos: rename for easier patch mergingAaron Durbin
In order to more cleanly apply upcoming changes some files will need to do a dance. Change-Id: Ib50670743c10221785447490190ecdbff8c764fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8654 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-23vboot2: read secdata and nvdataDaisuke Nojiri
This code ports antirollback module and tpm library from platform/vboot_reference. names are modified to conform to coreboot's style. The rollback_index module is split in a bottom half and top half. The top half contains generic code which hides the underlying storage implementation. The bottom half implements the storage abstraction. With this change, the bottom half is moved to coreboot, while the top half stays in vboot_reference. TEST=Built with USE=+/-vboot2 for Blaze. Built Samus, Link. BUG=none Branch=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I77e3ae1a029e09d3cdefe8fd297a3b432bbb9e9e Original-Reviewed-on: https://chromium-review.googlesource.com/206065 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Original-Reviewed-by: Luigi Semenzato <semenzato@chromium.org> (cherry picked from commit 6b66140ac979a991237bf1fe25e0a55244a406d0) Change-Id: Ia3b8f27d6b1c2055e898ce716c4a93782792599c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-23libpayload: usb: xhci: set ENT flag in last Normal TRBSourabh Banerjee
If a TD is comprised of one or more Normal TRBs and terminated with an Event Data TRB, then the transition to the Idle state (and associated Stream state save) could occur after all the data for the TD has been moved (e.g. after Transfer Event TRBs have been executed), but before the Event Data TRB is executed. Under these conditions, the execution of the Event Data TRB is necessary to complete the TD, otherwise it does not occur until the next time the Stream is scheduled. This could lead to the lock up. The Evaluate Next TRB(ENT) flag provides a means of forcing the execution of a terminating Event Data TRB. Setting ENT flag in last Normal TRB makes the xHC to evaluate the Even Data TRB. BUG=chrome-os-partner:29375 TEST=Verified kernel boot-up on storm from previously failing USB stick. USB stick model: Sandisk Ultra USB 3.0 Pen Drive 32 GB Strontium Jet USB 3.0 Pen Drive 32 GB Change-Id: I092e2109c55c2274239c493cb67b47d730304ed2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7eefb3b2858c841165ae839d349d2a0be50fbcc8 Original-Change-Id: I4e123577ec5a5996d87d2fc52cb6cf5c571c9fae Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220123 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8736 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23libpayload: EHCI: Support root-hub TT featureJim Lin
If EHCI controller has TT (Transaction Translator) support in root-hub, then we need to keep control over this controller when USB keyboard (low-speed device) is connected to root-hub port. Need to add "CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT=y" to config file (e.g. payloads/libpayload/configs/config.nyan_big) to support this feature. BUG=chrome-os-partner:32355 TEST=Tested on nyan_big platform. Press ESC+REFRESH+POWER keys on internal keyboard to power up. Press Left Arrow or Right Arrow on USB keyboard to switch between "English" and "Default Locale" in coreboot UI. Or unplug and plug in device and try again. Root hub <- low-speed USB keyboard Root hub <- full-speed hub <- low-speed USB keyboard Root hub <- high-speed hub <- low-speed USB keyboard Change-Id: Iaa2823f64c8769fc808ee7a316c378f18f004e63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4ad57fd673d6dc8814fe99a4ac420566bb17e77b Original-Change-Id: Id86a289bc587653b85227c1d50f7a4f476f37983 Original-Signed-off-by: Jim Lin <jilin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220125 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23Enable publishing of board ID where supportedVadim Bendebury
These boards are supposed to be able to determine the board ID at run time based on GPIO settings. BUG=chrome-os-partner:30489 TEST=verified that all boards build. Checked that storm proto0 reports board ID of 0 on the console Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210119 (cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733 Reviewed-on: http://review.coreboot.org/8722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23storm: Add board ID calculation functionVadim Bendebury
storm uses three GPIOs in tertiary mode, such that proto0 returns value of 8 when the GPIOs are interpreted as a single tertiary number. Adjust the calculated value to return board ID of 0 on proto0, and monotonously incrementing values on newer boards. BUG=chrome-os-partner:30489 TEST=when enabled, the board ID value of zero is reported on the console. Original-Change-Id: I2ff8fd5cbc8d568877b6f8bf220e146893f1e4be Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210118 (cherry picked from commit 6ba24f31583933f02be111c8767ae9df56537011) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I35ee218df35a0924d4bb8fcbc6c875450a609f24 Reviewed-on: http://review.coreboot.org/8721 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23Include board ID calculations only when necessaryVadim Bendebury
For the majority of Chrome OS boards there is no need to include board ID calculation in any stage but ramstage, where the ID should be available for inclusion into the coreboot table. BUG=chrome-os-partner:30489 TEST=build only, no other tests yet Change-Id: I1451d52382bc48cc126d40267e0f61712f4a6d4b Original-Change-Id: Ib9c06698a399d31e79a9b14143343ba2ad46d0fb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210117 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 27dd40e85bfcd0a38f388bad4d79f5fbb77a7566) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8720 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23Publish the board ID value in coreboot table, when configuredVadim Bendebury
Board ID value is usually of interest to bootloaders. Instead of duplicating the board ID discovery code in different bootloaders let's determine it in coreboot and publish it through coreboot table, when configured. BUG=chrome-os-partner:30489 TEST=none yet Change-Id: Ia1e36b907ac15b0aafce0711f827cb83622e27bb Original-Change-Id: Iee247c44a1c91dbcedcc9058e8742c75ff951f43 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210116 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit b2057a02db9391e2085b138eea843e6bb09d3ea2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8719 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23ipq806x: implement GPIO APIVadim Bendebury
Add implementation of the GPIO API defined in src/include/gpiolib.h. Also, clean up the GPIO driver, make it use pointers instead of integers for register address. This requires a touch in the SPI driver, where the CS GPIO is toggled and in the board function where it enables USB interface. BUG=chrome-os-partner:30489 TEST=tested with the following patches, observed proto0 properly read the board ID. Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210115 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2 Reviewed-on: http://review.coreboot.org/8718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-23Generalize revision number calculation functionVadim Bendebury
Some platforms use tertiary interpretation of GPIO input state to increase number of distinct values represented by a limited number of GPIOs. The three states are - external pull down (interpreted as 0) - external pull up (1) - not connected (2) This has been required by Nvidia devices so far, but Exynos and Ipq8086 platforms need this too. This patch moves the function reading the tertiary state into the library and exposes the necessary GPIO API functions in a new include file. The functions are still supposed to be provided by platform specific modules. The function interpreting the GPIO states has been modified to allow to interpret the state either as a true tertiary number or as a set two bit fields. Since linker garbage collection is not happening when building x86 targets, a new configuration option is being added to include the new module only when needed. BUG=chrome-os-partner:30489 TEST=verified that nyan_big still reports proper revision ID. Change-Id: Ib55122c359629b58288c1022da83e6c63dc2264d Original-Change-Id: I243c9f43c82bd4a41de2154bbdbd07df0a241046 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209673 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c79ef1c545d073eaad69e6c8c629f9656b8c2f3e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8717 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23build: mips: add default compilation optionsVadim Bendebury
MIPS targets should be compiled with no position independent code allowed, as the generated image often does not support short range components reference. BUG=chrome-os-partner:31438 TEST=with the rest of the patches included MIPS board urara builds successfully Change-Id: I8ac2a2f6979d3b468159c9e29d07e022f48ab18a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e932b203db3e7cb510a7bf862d4538d55b6c7271 Original-Change-Id: I637dd44eb565447c18b2c3cdb022d0933c52fd20 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215677 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8822 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23console: Allow bootblock console on MIPSPaul Burton
In addition to ARM based systems, allow MIPS based systems to select bootblock console support. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I40e5d8b651102709118878a317f7e983a617f433 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1a41853273ef9ae716d5645379fcef79c5771b87 Original-Change-Id: I41f03ea8c8104ba2dd9f532b084696385d29636c Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/207973 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/8769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23mips: fix bootblock stack definitionsVadim Bendebury
Bootblock stack on Danube should be SRAM and defined separately from the rest of the coreboot stack. The actual coreboot stack will be defined later. The top of the stack should be above the bottom, as the stack grows towards lower addresses. BUG=chrome-os-partner:31438 TEST=ran bootblock on simulator under codescape, observed stack properly initialized. Change-Id: I43d2bae5f85a09a95ca0103b253399bd92555aef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e02724cb4b30990ebaa631dabb45917af29d6437 Original-Change-Id: I3c37c8b5a1c0e7fd19411558a8f6d899fc283191 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218732 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8767 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-23imgvp-danube: Support for the ImgTec Danube Virtual PlatformPaul Burton
Add basic board support for the ImgTec Danube Virtual Platform, which emulates a system built around the Danube SoC. Run this by loading coreboot.bimg into a flash device connected to SPFI1 chip select 0 & then executing the Danube boot ROM. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: Ia62af62804bab261f3cabf7c2e62f5bb08a4a1a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6cb1017f5e2fec85f7f5c60cd2cfec63cc886b49 Original-Change-Id: I7a2b52f304bcb4b614440ec38975e05f38b0e590 Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207976 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8766 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23danube: Use the generic timer interfaceVadim Bendebury
Actual timer support is not yet available for Danube, it will be added soon. For now, just to make the target build, modify it to use GENERIC_UDELAY and HAVE_MONOTONIC_TIMER configuration option. BUG=none TEST=the target builds again Change-Id: Iad1ceb966d5dbc8687b966be4d2506c8f92eba5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 261837539fb5a31f96e682edbcbbbc0e588f2750 Original-Change-Id: Ie3289eace9d2baadd01bd641b5dffc635ac80c0f Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220395 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8765 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23danube: use SOC specific rom stage codeVadim Bendebury
Romstage initialization code does not need to be board specific, keep it in the SOC directory. Should there be a need for the board specific code, it can be added later. BUG=chrome-os-partner:31438 TEST=with upcoming patches, the urara board coreboot builds fine Change-Id: Ib619fa9313d463ded13e9259e50bb5aeaab4fb05 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c08977aaa5e9b5da29359d1920d7d8b61ce86d3 Original-Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215992 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8764 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23t132: Change romstage base addressFurquan Shaikh
Romstage was overflowing. So move the base address lower BUG=chrome-os-partner:31032 BRANCH=None TEST=Compiles successfully Original-Change-Id: Ia05034477b51b149c87347ed1880f8e85ecbfbf8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210434 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 14af527a5d7cbb250e2358340196a9d749ec1683) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ib261fdd8b4c7eb4a1660c5d02fbcd3e0e3f34b22 Reviewed-on: http://review.coreboot.org/8723 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23rush: Add MMC supportFurquan Shaikh
BUG=None BRANCH=None TEST=Compiles successfully. Depthcharge is able to see mmc. Original-Change-Id: Ia0c9b432fa447c64fa13e5fae5a66a26bbc86360 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210002 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 4cb05ffa95a2a36c5b4606d2f0efe9e574b84e1d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7f9a27a4c0f0553e78fc1a289bffebbebd37c099 Reviewed-on: http://review.coreboot.org/8716 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23t132: Add support for tpm i2cFurquan Shaikh
Iniitialize I2C bus required for TPM operation. Problem observed was that if frequency is raised above 20KHz, TPM starts responding with NAKs either for address or for data. Need to look into that. BUG=None BRANCH=None TEST=Compiles successfully and TPM success messages seen while booting. Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210001 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2 Reviewed-on: http://review.coreboot.org/8715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23libpayload arm64: Allow board to define upper address limit on DMAFurquan Shaikh
Instead of forcing boards to have DMA region below 4GiB, provide Kconfig option DMA_LIM_EXCL that a board can use to set the upper limit in MiB units on the address range reserved by DMA. By default, this value is 0x1000 i.e. 4GiB limit on the DMA upper address. BUG=None BRANCH=None TEST=Compiles successfully for rush. Default value is seen as 0x1000. Change-Id: Ie35d3844a0989486ae022f8922fdd4c9d7d57fb4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6716cf312a103bc0440a558fc43c8c77869816e3 Original-Change-Id: I3ecbb4ec90995ab1568cb0924d5ce9467492697d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245250 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8800 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-23PCIe: Revise L1 Sub-State supportKenji Chen
BRANCH=None BUG=None TEST=Confirmed build pass only Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: Ic0e845436614e63ad5ace7fb74400f7ea295571c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3670b92e40d8757a48add6116a0edcec18074d8 Original-Change-Id: I5e029b0f82a771149d4c6127e30b9062e8eaba89 Original-Reviewed-on: https://chromium-review.googlesource.com/244514 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Kenji Chen <kenji.chen@intel.com> Original-Tested-by: Kenji Chen <kenji.chen@intel.com> Reviewed-on: http://review.coreboot.org/8833 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23PCIe: Add L1 Sub-State support.Kenji Chen
Enable L1 Sub-State when both root port and endpoint support it. [pg: keyed the feature to MMCONF_SUPPORT, otherwise boards without that capability fail to build.] Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092 Original-BUG=chrome-os-partner:31424 Original-TEST=Build a image and run on Samus proto boards to check if the settings are applied correctly. I just only have proto boards and need someone having EVT boards to confirm the settings. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a Original-Reviewed-on: https://chromium-review.googlesource.com/221436 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload: whitespace cleanupPatrick Georgi
Align struct members with tabs. Change-Id: Ie8bdbd718c7217a3f3768dd037fa7c10badbc05e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/8854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21tegra132: convert to stopwatch APIAaron Durbin
Simplify the timed operations by using the stopwatch API. BUG=None BRANCH=None TEST=Built and booted to kernel. Analyzed logs. Output as expected. Change-Id: Ia49bccccc412f23bb620ed386b9174468a434116 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a877020c6d8ba12422c9c2c487122b7eb4a1967b Original-Change-Id: Iffc32fcb9b8bfdcfbef67f563ac3014912f82e7f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219494 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8831 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21exynos: convert to stopwatch APIAaron Durbin
Instead of open coding monotonic timer usage, use the stopwatch API. BUG=None BRANCH=None TEST=None Change-Id: I1c541c1c9f3fde0dec9163ad6cc94322538ac7f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46ede0897687da6bcf730a8904f25e5a4485d6cd Original-Change-Id: Ia63a05850a1b6afdc42c2422332f77af516d27e3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219716 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21tegra132: fill out udelay() implementationAaron Durbin
There was an empty udelay() implementation result in 0 waits. Provide an actual implementation. BUG=None BRANCH=None TEST=Built and ran through to depthcharge on rush. Change-Id: Ia7060566a71c36bb7e4543c2fe4ee49d168518c7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c8832e73de238358ea801ccd7c2330de35a7b40e Original-Change-Id: I201f2fdc4e4f5c88d48e4002839b03e808a5a1bc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210827 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21tegra124: switch to stopwatch APIAaron Durbin
Instead of using rela_time use the stopwatch API as the semantics fit perfectly with the expiration usage. BUG=None BRANCH=None TEST=Built, but similar usage tested on tegra132. Change-Id: I1147f2bed84b93d1b776205df9ae04d1db9c98a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c38e054dd166d5eb53f692833b5ce88a230816e3 Original-Change-Id: I6d3f3da4e035e872890d8b67947b17a981673dba Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219712 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8819 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21device: convert to stopwatch APIAaron Durbin
Instead of open coding the monotonic timers use the stopwatch abstraction. BUG=None BRANCH=None TEST=Booted and noted timings work as expected. Built with software_i2c and no compilation failures. Change-Id: Ie5ecdd5bc764c1ab8ba4a923e65a1666aacd22f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7bffb5aeb41e9b88cd2c99edd6abc38f1dc90af Original-Change-Id: I0170fe4b93d9976957a2dcb00a6ea41ddc0320ce Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219495 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/8817 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21ramstage: remove rela_time useAaron Durbin
mono_time_diff_microseconds() is sufficient for determining the microsecond duration between 2 monotonic counts. BUG=None BRANCH=None TEST=Built and booted. Bootstate timings still work. Change-Id: I53df0adb26ae5205e2626b2995c2e1f4a97b012e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: deab836febea72ac6715cccab4040da6f18a8149 Original-Change-Id: I7b9eb16ce10fc91bf515c5fc5a6f7c80fdb664eb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219711 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8818 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21chromeec: use stopwatch APIAaron Durbin
Simplify the SPI timeout by using the stopwatch. BUG=None BRANCH=None TEST=Built nyan. Confirmed stopwatch works independently. Change-Id: Ida26a0748d4b5a6a28aa8f6e2b92fe2ee4cbe17f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 900d7ac826b76d49290033c87849bf776684f2c1 Original-Change-Id: I84b7949060326b7c6cc1872420b93bd44604c4d3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219493 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8816 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21timer: add stopwatch constructAaron Durbin
There's a lot of places where expiration and running time are open coded. Allow for those places to be simplified by adding a stopwatch construct. The stopwatch can have an expiration or just be used to accumulate time. BUG=None TEST=Built and verified API works as expected by using implementation. Change-Id: Ibd636542b16d8554f1ff4512319a53dce81c97e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc623a1b36eb08c5877591c4509cd61131c62617 Original-Change-Id: I53604900fea7d46beeccc17f1dc7900d5f28518b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219492 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/8815 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21Allow for different BFD elf formats per architectureVadim Bendebury
The upcoming MIPS toolchain inside chroot generates elf images of elf32-tradlittlemips format, whereas readily available tools outside of chroot generate images of elf32-littlemips format. Both of these formats are perfectly fine, but xcompile accepts only one format per CPU architecture. This patch allows to specify multiple formats per architecture, any matching format will suffice. BUG=chrome-os-partner:31438 TEST=emerged arm, x86 and mips targets inside chroot Change-Id: I2c6b8e46b9299059b8e099b93c8c3dcf0a569899 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7f2f1d51643f33b72ac5e4091669f38662e5b9ce Original-Change-Id: I22405e71ac72b985fad51e2f5d7cc014107b8a9e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214599 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8823 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21imgtec/danube: Build BIMG boot imagesPaul Burton
Add a new utility named bimgtool, a simple tool which generates boot images in the BIMG format. This is the format the Danube boot ROM expects the user supplied code to be wrapped in, it is described by struct bimg_header in the code. This utility will be used to wrap the coreboot bootblock when building Danube targets. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I08ddb1b70d0b1feb1ffb3d62c4e5e6f07f4acdb7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7fe6a9f383b79120f9ae231453d4b3a0f85b4fa7 Original-Change-Id: I63b9f5e09cd1f12765317b38e2a0dd033cdd6d39 Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8768 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21danube: prepare SOC directory for uraraVadim Bendebury
These modules are necessary to resolve external names when building the board image. These are just skeletons for now which will be filled later. BUG=chrome-os-partner:31438 TEST=when config is enabled, emerge-urara coreboot succeeds. more extensive testing to come later Change-Id: I0fcb5d33187172ecac77041425402b33e89e8944 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94ec79b0ab872f5c5fe7db5bef5fdabf77d6b3b6 Original-Change-Id: I69cc178976a910ebf8031ed9ac9ad67b4cc0878a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215678 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21imgtec/danube: Add support for ImgTec Danube SoCPaul Burton
Add build infrastructure and basic support code for the ImgTec Danube SoC. This support is sufficient to run on a simulator. BUG=chrome-os-partner:31438 TEST=none yet Change-Id: I59e36589765bf06b075fd4850215a0ef71246bb1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 881278d7fbb8e6803bc8f6f9e84c64640b097401 Original-Change-Id: Ia7ed7288b13085db7ff37b5ad75d978b6137f958 Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207974 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8762 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21mips: no need in architecture specific implementation of do_printkVadim Bendebury
With the proper configuration flags enabled, do_printk is available from src/console, no need to define it elsewhere. BUG=chrome-os-partner:31438 TEST=with upcoming patches, the urara board coreboot builds fine Change-Id: I82071b4ca1686639c0bd39c63a06b61cb5bf5571 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 69c655537c50274a61cf123b7fc387ec60dd29c7 Original-Change-Id: Ib1e3e5750cdc1adc509b4580a4f24d3ff3b105ee Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215862 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8761 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21arch/mips: Add base MIPS architecture supportPaul Burton
Add the build infrastructure and basic architectural support required to build for targets using the MIPS architecture. This is sufficient to run on a simulator, but will require the addition of some cache maintenance and timer setup in order to run on real hardware. BUG=chrome-os-partner:31438, chromium:409082 TEST=none yet Change-Id: I027902d8408e419b626d0aab7768bc564bd49047 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcc0d934d7223922c878b1f87021cb5c2d7e6f21 Original-Change-Id: If4f99554463bd3760fc142477440326fd16c67cc Original-Signed-off-by: Paul Burton <paul.burton@imgtec.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207972 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8760 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21mips: Add mips/ashldi3.c from LinuxVadim Bendebury
As MIPS toolchain does not provide adequate support for 64 bit division and shift operations, the missing functions are required to be provided by the user. This patch brings in the Linux implementation of the 64 bit arithmetic shift borrowed from arch/mips/lib/ashldi3.c (eg. Linux v3.14). BUG=chromium:406038 TEST=With the upcoming patches coreboot successfully builds for MIPS targets in chroot (coming later). Change-Id: I2168f69352a9b9e3c5d197489f701a442e65703c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8ec616161be8ad3aeb6494e7121615e3329b414d Original-Change-Id: Ia1ccb29d4c9f3c95e04e06f6af7ce8a00e2e7455 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214156 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8759 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-21libpayload arm64: fix mmu_disable() cache problemHC Yen
The raw_write_sctlr_current() cannot be used in mmu_disable() because it pushes some registers to cached stack, and then just after cache disabled, the value was gone. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: I512405b7917f27d16bdd3c51d9459827ad714e67 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aafe64922cc4cd01ecb099db106d04538e3e57ff Original-Change-Id: I0dda8518d14c46fae1fe76e3629bd4ee81c1e0ee Original-Signed-off-by: HC Yen <hc.yen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240323 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8799 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add helper functions with el argumentHC Yen
Allow read/write to registers at a given el. Also, make read/write registers at current el call this newly added function. BRANCH=none BUG=none TEST=build and boot on mt8173-evb Change-Id: Id69f0fdc07193c5c7e997712f0cd99de6f41510b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c091917babc39d9ab997f51f81b486c9aa900c24 Original-Change-Id: I0944946642066b88331e497a92388e74e86902d0 Original-Signed-off-by: HC Yen <hc.yen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/240322 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8798 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: don't modify cbtable entriesAaron Durbin
The framebuffer structure lives in the coreboot tables. Those tables have a checksum calculation applied over all the entries. Therefore, one shouldnot be modifying fields within the coreboot table entries because the calculated checksum would be wrong. BRANCH=none BUG=chrome-os-partner:31936 TEST=On ryu, confirmed dev screen still works as well as cbmem utility once booted. Change-Id: I93830a8efe98aa848f2b0f8388688de0e93b2f82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6026ca5ad0254c14c30412882dc63550656c7d16 Original-Change-Id: Ic9c164ded03d10d6f6f3ce15e9b38b1f6ce61a91 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/230471 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8797 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Allocate framebuffer rangeJimmy Zhang
Allocate noncacheable memory for frame buffer and save base address to sys_libinfo. BRANCH=none BUG=chrome-os-partner:31936 TEST=build and test on ryu Change-Id: I19a8079616376dc7c1a8ecdbd7499c2553b8c6c3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cebb5650167264902548339bb1a2b428f3b7f4ed Original-Change-Id: I7bfbfefb92001632ce3d572a50e46188795c4ab8 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/226404 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8796 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Move console_init after post_sysinfo_mmu_setup callFurquan Shaikh
This is important since mmu is disabled during the post_sysinfo_mmu_setup call and calling printf can cause unaligned access. BUG=None BRANCH=None TEST=Compiles successfully and boots to kernel prompt with console_init Change-Id: I5ef72ee449fdcf30186f97485cc532d6c56b2c5d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 688ef3856d0502d057c9543ee7763601156e6385 Original-Change-Id: Ie376e394d084edd6c999fc9edde79f15a0264e7b Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222664 Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8795 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add function to get new range from available memrangesFurquan Shaikh
Provide a function to obtain a new memrange with requested properties (type, size, alignment, max_addr and other restrictions) from the set of available memranges passed in coreboot table. One user of this function would be getting memrange for dma, another one would be framebuffer. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ic5a63ca2dca6c71f4ca2d77e2e2c8180d32a38e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3cd75756e1405e044c029f2878bfcc9c8c962bdf Original-Change-Id: I187d73a4d55d3c6f49afbe9852901672d25de8dc Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/222110 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8794 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: fix mmu bugsAaron Durbin
1. keep functions and objects used entirely within mmu.c as static. 2. DMA region finding needs to terminate. Therefore, the next address to be attempted needs to be less then the current end address. 3. Ensure mmu_ranges passed to mmu_init_ranges_from_sysinfo() has 0 entries marked as used. BUG=chrome-os-partner:31634 BRANCH=None TEST=Booted ryu with RAM hole above cbmem tables below 4GiB. Change-Id: I71a9cb89466978aa63fca5d8bee97b8af75ea206 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 66518fd86e676bbddf52e9d9afdd76d72c8e2222 Original-Change-Id: I5cb4e5009359cb04c4e1b5fe60845f80fbdff02c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/221725 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8793 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Initialize and enable MMUFurquan Shaikh
What this change does: 1) Initialize limited page tables as soon as we jump into libpayload. Basically two ranges are initialized. One is for the BASE_ADDRESS and other is for the coreboot_tables. With page tables initialized and MMU enabled, we jump into code to parse coreboot tables. 2) Once coreboot tables are parsed and we have complete picture of the memory, we perform a complete page table initialzation and enable MMU and then jump to payload. Additionally, we also: 1) Initialize DMA memory on our own depending upon the memory map. It ensures that the DMA buffer is placed in 32-bit memory. CQ-DEPEND=CL:216826 BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and we are able to start execution of libpayload in EL2 and reach kernel login prompt Change-Id: I8a6203e465868bc2a3e5cc377e108f36cc58e2fa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7695bb7afe34ea460282125a0be440e8994b01e4 Original-Change-Id: Ie0f47b7759d4ac65a6920f7f2f7502b889afda6d Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216824 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8792 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add support for read and write registers at current EL in ↵Furquan Shaikh
assembly In order to ease the process of reading and writing any register at current EL, provide read_current and write_current assembly macros. These are included in arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow the same header file to be included by .c and .S files. BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully for ryu Change-Id: I79241a944b68ebb24865e745a9835f54ab6d1a8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2b55fbde466126c4de7f5f7bb2d1427196be842f Original-Change-Id: I678ab89c4aa1b08898166e135b5ab2d6453bb5e8 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/214576 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8801 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add support for mmuFurquan Shaikh
Adds support for initializing mmu, setting up dma areas and enabling mmu based on the memranges passed on in the coreboot tables. CQ-DEPEND=CL:216826 BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: Id41a4255f1cd45a9455840f1eaa53503bd6fef3f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2c6676bf51fcd85b61e9e08a261634a78137c4c Original-Change-Id: I217bc5a5aff6a1fc0809c769822d820316d5c434 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216823 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8791 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Remove dependency on coreboot tables for dma areasFurquan Shaikh
Libpayload should be able to setup its own dma areas and not depend on coreboot tables for passing this information. This patch and next allow libpayload to setup dma areas while performing mmu_init BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and dma areas are setup properly with the mmu init patch Change-Id: I5f6fd19a957c7626a2bbe6b826c8987e64ed248f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4f3552b8d3439a8b12d1e0b15ef67dcb14b8c96a Original-Change-Id: I44d9f394fa349abd7182c4ba10f1eaefd6e4fdaa Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216822 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8789 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-21libpayload arm64: Add functions for reading memrangesFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully Change-Id: I12e7cdaf07c1bc4802a04dadd85384939b5a67e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c454a3d60b0e087df79de4fd9cff09596ae12ca5 Original-Change-Id: Iec82d56ae4a5f1ac6243afef1f453de3905d869c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216821 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8788 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 07:55:09 +0000