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2020-06-18ACPI,drivers/: Do not guard <acpi/acpi.h>Kyösti Mälkki
Header was moved outside arch/. Change-Id: Id96c2bdcee49cddab6610c7e2cd6f07638279256 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18ACPI: Clean up some S3 related leftoversKyösti Mälkki
With RELOCATABLE_RAMSTAGE the backing up of low memory on S3 resume path was dropped. We forgot some things behind. Change-Id: I674f23dade0095e64619af0ae81e23368b1ee471 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18soc/intel,chromeos: Fix EC RO/RW status in GNVSKyösti Mälkki
For baytrail and braswell, explicitly initialise it to ACTIVE_ECFW_RO without ChromeEC. For broadwell and skylake, fix it to report actual google_ec_running_ro() status. Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18mb/bap/ode_e21XX: Drop left over unmaintained ROMCC boardElyes HAOUAS
Remove unmaintained and unsupported old ROMCC board. This board wasn't hooked up for build. Change-Id: Idd907311dde187aa62d29a9d3943b6d5c08a1f71 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-18soc/intel/tigerlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZ4 compression technique to compress FSP-S. This provides some SPI ROM space savings (~36 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZ4 is chosen over LZMA since the decompression saves ~25 ms for an extra overhead of ~1KiB. LZ4 Compression: fsps.bin 0xe6fc0 fsp 254262 LZ4 (290816 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 712,361 (1,072) 18:finished LZ4 decompress (ignore for x86) 750,695 (38,334) LZMA Compression: fsps.bin 0xe6fc0 fsp 253415 LZMA (290816 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 707,696 (1,150) 16:finished LZMA decompress (ignore for x86) 767,763 (60,067) BUG=b:158034451 TEST=Build and boot volteer mainboard. Change-Id: I91e33eb7b688b5383f3a0075a28ac21250314973 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42444 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/intel/jasperlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZ4 compression technique to compress FSP-S. This provides some SPI ROM space savings(~60 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZ4 is chosen over LZMA since the decompression saves ~50 ms for an extra overhead of ~1.5 KiB. LZ4 Compression: fsps.bin 0xa9fc0 fsp 203423 LZ4 (262144 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 433,550 (1,154) 18:finished LZ4 decompress (ignore for x86) 461,620 (28,069) LZMA Compression: fsps.bin 0xa9fc0 fsp 202132 LZMA (262144 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 478,448 (1,174) 16:finished LZMA decompress (ignore for x86) 557,725 (79,277) BUG=b:158034451 TEST=Build and boot waddledoo mainboard. Change-Id: I416b1d91d7f4836b1e9c641b0fe07b39876364ba Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18soc/intel/cannonlake: Enable FSP-S compressionKarthikeyan Ramasubramanian
Use LZMA compression technique to compress FSP-S. This provides some SPI ROM space savings(~27 KiB) in each CBFS. FSP-M is XIP and hence not compressed. LZMA is chosen over LZ4 since it provides extra space savings of ~1 KiB for the decompression overhead of ~7 ms. LZMA Compression: fsps.bin 0xd1fc0 fsp 190132 LZMA (217088 decompressed) LZMA Decompression: 15:starting LZMA decompress (ignore for x86) 343,289 (417) 16:finished LZMA decompress (ignore for x86) 373,922 (30,632) LZ4 Compression: fsps.bin 0xd1fc0 fsp 191310 LZ4 (217088 decompressed) LZ4 Decompression: 17:starting LZ4 decompress (ignore for x86) 345,676 (581) 18:finished LZ4 decompress (ignore for x86) 369,101 (23,424) BUG=b:158034451 TEST=Build and boot helios mainboard. Change-Id: Ic0d0d81c81eaa365f3dbfdd2e00ac76cea287387 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42446 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18vendorcode/intel/fsp: Update MemInfoHob header for Jasper LakeAamir Bohra
Jasper Lake has been using the incorrect MemInfoHob header. Updating the header to align it with Jasper Lake MRC code. BUG=b:158722318 TEST=Verify memory info is populated for channnel 0 and 1 on wadddledoo. Change-Id: Icca3e3b4cda9ca257f3b725823facf52ceec37b7 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-06-18mb/google/dedede: Add support for 16 MiB flash map descriptorKarthikeyan Ramasubramanian
Upcoming variant boards will use 16 MiB SPI ROM. So add support for 16 MiB flash map descriptor. BUG=b:155107866,b:152981693 TEST=Build different variant boards. Ensure that waddledoo which is using 32 MiB SPI ROM boots. Cq-Depend: chrome-internal:3107306 Change-Id: I8a6868da3280a662ff3a30623804ff135e6cbfbc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42322 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-18lint: convert checkpatch_json.py to python 3Stefan Reinauer
Align all coreboot scripts on one python version. Tested by running the original suggested test: $ nice -n 20 git diff HEAD~ | util/lint/checkpatch.pl \ --no-signoff -q - | tee checkpatch.txt $ util/lint/checkpatch_json.py checkpatch.txt \ comment.json checkpatch.txt Change-Id: Iec2bb0be23b27a3eaf92f293c962a8e6bfb03af0 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-06-18soc/intel: remove unused dptf.asl file and other definesSumeet R Pawnikar
Remove unused cannonlake dptf.asl file and cleanup defines from apollolake dptf.asl file as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on the system Change-Id: I4c8bf2bd5da9d5881e7690bff34816b19dd96072 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18mb/google: remove cannonlake dptf.asl include file from dsdt filesSumeet R Pawnikar
Remove cannonlake dptf.asl include file from all the dsdt files as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on the system Change-Id: I961a3ecb27e7bb7bb0b98c8630900bada0531639 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-18soc/intel/common: make dptf acpi device ids configurableSumeet R Pawnikar
Make dptf acpi device ids configurable for thermal functionality as per soc/intel/common/acpi code changes for dptf. BUG=None BRANCH=None TEST=Build and boot on volteer system Change-Id: I5161d19dc663cdb9a7b004bb681059c9af2aaf4f Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-18mb/google/hatch: fix variants' selection of CHROMEOS_DSM_CALIBMatt DeVillier
CHROMEOS_DSM_CALIB requires/selects CHROMEOS, so only select if CHROMEOS already selected, otherwise building for non-ChromeOS targets fails. Test: build HELIOS for non-ChromeOS target (Tianocore payload) Change-Id: Ic0fd3b0a0efbc5a1f6896eb379569a55cb0f67f8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-18mb/google/volteer/variants/terrador: Disable EC SW syncDavid Wu
It is the reference board of TGL-Y platform, we want to disable EC SW sync for Proto stage, it would be re-enabled before EVT stage. BUG=b:156435028 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie7999e24e9c173d4870b35ce1728f3dcc8dcac29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18MAINTAINERS: Organize contentsAngel Pons
Group entries by categories, and sort the groups alphabetically. Also, separate different mainboard vendors with two extra spaces for clarity. Change-Id: I43df8c24a40433357760827777497cbac4b6a919 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-18soc/intel/common: Introduce ASL2.0 syntaxAlexey Buyanov
Fix last legacy ASL syntax match in acpi/pcr.asl BUG=none TEST=Deltan coreboot binary remains the same after the changes are applied Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ia1021851b42b8fad52b3197d9003056d3dd2db04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42437 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17security/tpm: Change wording of variable namesDuncan Laurie
Change the name of these variables to 'allowlist'. Change-Id: I9d5553988a1c9972b8f1ebaeee20878b23a8aa9b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42316 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17lib/reg_script: Add guards for <arch/io.h>Kyösti Mälkki
Header and implementation only present for ARCH_X86 stages. Change-Id: I4b28e666a8a60bd0365cda8d7affa1eb063c4690 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42416 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17treewide: Replace CONFIG(ARCH_xx) testsKyösti Mälkki
Once we support building stages for different architectures, such CONFIG(ARCH_xx) tests do not evaluate correctly anymore. Change-Id: I599995b3ed5c4dfd578c87067fe8bfc8c75b9d43 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17Revert "soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run"Furquan Shaikh
This reverts commit d5f1e0f9734273f79ebd313bb6a17eda04c22c11. Reason for revert: FSP-S is now fixed to not touch the SPI configuration registers. Thus, coreboot does not need to reconfigure SPI after FSP-S has run. BUG=b:153506142 TEST=Verified that SPI configuration registers look the same before and after FSP-S has run. em100 works fine without any additional changes in coreboot to reconfigure SPI. Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-17ec/google/wilco: Suppress UCSI events in S0ixDuncan Laurie
If a UCSI event comes in when the EC is in S0ix mode then the kernel driver attempts a transaction but fails and this can leave the system in an unexpected state where the only wake source is the power button. This change will not notify the UCSI driver if the EC is in S0ix mode and instead keep track of the event and send it on resume. BUG=b:157923800 TEST=tested on drallion system: 1. Put drallion system into suspend 2. Attach power supply 3. Ensure the system can wake with keypress Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I43acb089385d9b41ac955f053e409daad67423f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-17mb/google/volteer: remove unused GPP_H23Nick Vaccaro
BUG=b:157567939 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer to kernel. Change-Id: I3046cf3a359e833a5d204f78ab84312e8665061f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42411 Reviewed-by: Jes Klinke <jbk@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/volteer: Set IomTypeCPortPadCfg default to 0x09000000Brandon Breitenstein
Temporary workaround for S0ix issues related to FSP's handling of 0 value. When IomTypeCPortPadCfg is 0 FSP completely skips any flow related to this value which seems to be causing issues with s0ix. This is still being debugged and a final solution will be made when available BUG=b:159151238 TEST=flash image with workaround to volteer and verify that s0ix cycles correctly. Change-Id: Id79dd1c49958389cdb666b3760abd821bc1973a8 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42268 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17soc/amd/picasso: rename PICASSO_UART Kconfig optionFelix Held
The PICASSO_UART Kconfig option is about using the internal MMIO UART controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-17soc/amd/picasso: fix build if PICASSO_UART is unsetFurquan Shaikh
This change includes uart.c in bootblock, romstage, ramstage and verstage unconditionally because this file is handling more than just the UART console configuration. This allows boards to take advantage of picasso_uart_mmio_ops even if PICASSO_UART is not selected. uart_platform_base and uart_platform_refclk mustn't be provided if PICASSO_UART is unset, so add an #if around those functions. BUG=b:158346697 TEST=Mandolin builds again. Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17device/pnp_ops.h: Use pnp.h functionsAngel Pons
With BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I3ca080e700cf7b7f5b76cadddc7e41960413433c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42133 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17crossgcc: Upgrade GDB to version 9.2Elyes HAOUAS
Change-Id: I30dae356ec3b373ac036c7eced7d6e89ddd08246 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38787 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17crossgcc: Remove "Make"Elyes HAOUAS
In its current state, it draws more dependencies in than it solves which makes it useless. Change-Id: I08f592731c3da2ac19e1f93682256f559a067fc4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-17soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPDWonkyu Kim
This patch adds support for enabling/disabling PCIe hot-plug via a chip config option PcieRpHotPlug, which is copied to the corresponding FSP-S UPD. BUG=b:156879564 BRANCH=none TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17mb/google/hatch: mushu: Add F75303 temp sensor to dptfPuthikorn Voravootivat
Update the following in dptf.asl - Add support for TSR3 - Change TSR0/TSR1/TSR2/TSR3 From: Charger, 5V, GPU , None To: Charger, GPU, F75303_GPU, F75303_GPU_POWER - Adjust fan/cpu trip point accordingly - Fix formating in dptf.asl - Throttle charger when TSR0 (charger) is hot instead of throttle CPU BUG=b:158676970 BRANCH=None TEST=grep . /sys/class/thermal/thermal_zone5/{type,temp} /sys/class/thermal/thermal_zone5/type:TSR3 /sys/class/thermal/thermal_zone5/temp:50800 Change-Id: Iedbb6bc7c1e59a027119c70791b9bc8a4d83ff87 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42270 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17smmstore: Verify userspace-provided pointer to protect SMMPatrick Rudolph
Use the introduced functions and verify pointers in the SMMSTORE. Make sure to not overwrite or leak data from SMM and update the documentation as well. Change-Id: I70df08657c3fa0f98917742d8e1a6cb1077e3758 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41085 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17cpu/x86/smm: Add helper functions to verify SMM accessPatrick Rudolph
* Add a function to check if a region overlaps with SMM. * Add a function to check if a pointer points to SMM. * Document functions in Documentation/security/smm To be used to verify data accesses in SMM. Change-Id: Ia525d2bc685377f50ecf3bdcf337a4c885488213 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41084 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17soc/intel/cannonlake/vr_config: Add CFL defaults to TDC powerlimitPatrick Rudolph
Add CFL defaults for VR TDC config and provide Iccmax for additional Xeon CPUs tested on the Prodrive/Hermes board. Based on the following Intel documents: * Document Number 570805 (XEON E EDS Vol 1) * Document Number 337344 (CFL Datasheet Vol 1) * Document Number 571264 (CFL CNP PDG) Change-Id: I681de076318fb647c44cc8b8c42eb297018cc540 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17soc/intel/cannonlake: Use table instead of switch-casePatrick Rudolph
This makes future changes easier to review. Change-Id: I5d67801a46a1613fbc7f813e94933fa30c1b92df Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17ifdtool: Improve PCH strap handlingPatrick Rudolph
Read the PCH Strap Length field in FLMAP1 as described in the "SPI Programming Guide" and print the number of fields specified there. This code dumps the following straps: * Intel GM45: 8 straps * Intel C216: 72 straps * Intel C240: 360 straps Add a new function to easily set PCH straps, which is useful for debugging. Change-Id: Ieb7891b214d82c984379794de9b3fe1a6d0d3466 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17mb/google/puff: add MST and LSPCON details to variants devicetreeShiyu Sun
Added device hid info to the MST and LSPCON devices on kaisa, duffy and noibat. BRANCH=None BUG=b:156546414 TEST=None Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I7b54512cd88e7280374c188315cabc2fba197f69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-16Revert "x86/lapic: Set EXTINT on BSP only"Angel Pons
This reverts commit aac79e0b8f4777f8a912ccdfc483755b7a4da52c. Reason for revert: This massively slows down the boot process because the LAPIC delivery mode for the APs is not set anymore. Plus, not all review comments were fully addressed, yet this got merged in anyway. Change-Id: If9bae6aae0d4d1f21b067a7d970975193c2b16d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16superio/winbond/w83977tf: Add suspend related fieldsKeith Hui
Add two fields for the ACPI logical device to the ACPI code. They are used for taking asus/p3b-f board out of suspend by keyboard or mouse. Change-Id: Icaadfea6a4dce7a2d665e8d89a024359975f8b2c Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41096 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16x86/lapic: Set EXTINT on BSP onlyZheng Bao
When Linux is booted, the kernel reports "do_IRQ: 1.55 No irq handler for vector" So far it comes with payloads SeaBIOS and depthcharge, not with Grub. We assume Grub does something to avoid this problem. AMD bug tracker system (JIRA PLAT-21393) says the APs can not be set EXTINT delivery mode. In Intel 64 and IA-32 Architectures Software Developer’s Manual volume 3A, see chapter 10.5.1 Local Vector Table, it says: "The APIC architecture supports only one ExtINT source in a system, usually contained in the compatibility bridge. Only one processor in the system should have an LVT entry configured to use the ExtINT delivery mode." Tested on mandolin (Picasso) board, the error in dmesg is gone. The bug 153677727 has two parts. 1. Soft lockup 2. do_IRQ 1.55. The soft lockup issued has been fixed by https://review.coreboot.org/c/coreboot/+/41128 BUG=b:153677727 TEST=mandolin Change-Id: I2956dcaad87cc1466deeca703748de33390b7603 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42219 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16mb/pcengines/apu2/mainboard.c: unify hexadecimal notation using capital lettersPiotr Kleinschmidt
mainboard_intr_data table mixed hexadecimal notation with both small and capital letters. Now, it is unified to capitals only. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Change-Id: Icd8cf4324e72e87e7e98869872785523fb4e1809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42388 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16sb/intel/common/pmutil: Add dump_all_status()Kyösti Mälkki
Change-Id: I10582941afd68425603f6c4cadd228797cd098e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16lib/malloc: Drop <cpu/x86/smm.h> includeKyösti Mälkki
Change-Id: I39b8dc37219195e88ea6396aa7e987e5e244bbab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16soc/amd/picasso/include/soc/memmap.c: Add missing <stdint.h>Elyes HAOUAS
include <stdint.h> for 'uint32_t'. Change-Id: I8768b7f0692ed703a060dc0406b517dc001cc25d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-16cpu/x86: Define MTRR_CAP_PRMRRKyösti Mälkki
Followups will remove remaining cases of PRMRR_SUPPORTED and SMRR_SUPPORTED in the tree. Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb/intel/i82801dx: Drop smm_setup_structures()Kyösti Mälkki
The only board that builds this does not have ACPI S3 support. Also the code is wrong. Change-Id: Ifb8e0ae5b6d862fa6a52b8e08197a84e7da4be36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16soc/amd: Replace enable_smi_generation()Kyösti Mälkki
Change-Id: I9846df34fd2b6b15549fa33d3eda137544fa4219 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb/amd/x/hudson: Replace hudson_enable_smi_generation()Kyösti Mälkki
Change-Id: I08b2d1af16c247e66bf1a352887b0f9387055225 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16sb,soc/intel: Replace smm_southbridge_enable_smi()Kyösti Mälkki
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)Kyösti Mälkki
Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 09:30:17 +0000