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2018-05-04cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELFPatrick Rudolph
In preparation of having FIT payloads, which aren't converted to simple ELF, rename the CBFS type payload to actually show the format the payload is encoded in. Another type CBFS_TYPE_FIT will be added to have two different payload formats. For now this is only a cosmetic change. Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-04superio/ite/common: Add options to enable beepsVagiz Trakhanov
Add device tree options to enable beeps when exceeding temperature, voltage, and fan limits. As of this commit, setting voltage and fan limits is not implemented. Change-Id: I57ce622ee4498b75f00e678c2e6d72e499925bce Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org> Reviewed-on: https://review.coreboot.org/22141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/ricoh/rce822: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I6f6c4330ad88e013b24761a3aa1c29bc869da39d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/uart/oxpcie.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: If2b9cbf130f963bc1bedef16b7951e9546054743 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/drivers/lenovo/wacom.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Idb139d5cb2ac10f4051407137242ccee1a09b785 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/intel/i210.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: If9c122efbb7dbab7d834372da3c1c70463be7a77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04drivers/intel/gma/opregion.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Idff2ec30f0b8c9a49f4369e231be92cbc8070dc0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/root_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Ia25c5097d4cfa979c18a855e656ad794c2f0260c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/pci_class.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I839533a33aa54df4efed3f372c6f88e79b0b559b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/pcix_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I14c0db71ffa5faa8321c88c9c75c0c18a70910e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04device/smbus_ops.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I5eb858df7b69a7177564c883b81177ffadc63691 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/cardbus_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I6f3efd8c9be7f9fb83b373fbee311b06cde54181 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/pciexp_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I82b73e1698d8d44e32ad9f21e575a7fce35baa1c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04src/device/pnp_device.c: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Ic25d1eb3c7f0ed5b65aa1cf9e16c39415b7cd3c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04console/vtxprintf.c: Add required spaces around '>'Elyes HAOUAS
Change-Id: I2e1e494f40bf2316e02a96759a92c933ee11fbab Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04arch/x86/cpu.c: Remove unneeded headersElyes HAOUAS
Change-Id: I35fcf25906bf7fe5af133618654bb121404743fc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04arch/x86/cpu_common.c: Remove unneeded headersElyes HAOUAS
Change-Id: I4f57376138725804133059c785e89e095fd6a759 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04lib/bootmem: Add method to walk OS POV memory tablesPatrick Rudolph
Add method to walk memory tables from OS point of view. The tables don't change when modifiying bootmem entries and doesn't contain bootmem specific tags. Change-Id: Iee332a9821d12a7d9a684063b77b0502febd8d7d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04lib/bootmem: Add method to walk memory tablesPatrick Rudolph
Add a method to walk bootmem memory tables and call a function for each memory range. The tables might not match with OS sight of view. Return true if the callback function returned false. Required for FIT support in coreboot to find a usable RAM region. Tested on Cavium SoC. Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04lib/bootmem: Add more bootmem tagsPatrick Rudolph
Introduce new bootmem tags to allow more fine grained control over buffer allocation on various platforms. The new tags are: BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that should not be touched by bootmem (by example: stack, TTB, program, ...). BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should not be touched by bootmem. Starting with this commit all bootmem methods will no longer see memory that is used by coreboot as usable RAM. Bootmem changes: * Introduce a weak function to add platform specific memranges. * Mark memory allocated by bootmem as BM_TAG_PAYLOAD. * Assert on failures. * Add _stack and _program as BM_MEM_RAMSTAGE. ARMv7 and ARMv8 specific changes: * Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE. ARMv7 specific changes: * Add _ttb_subtables as BM_MEM_RAMSTAGE. Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04mainboard/hp/dl145_g1: Remove commented codeElyes HAOUAS
Change-Id: I4528eb064e8b9c5ebb235ca16e13582df9efd4cd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-04mainboard/google/kahlee: Pass oscout system clk to da7219Akshu Agrawal
Using da7219 mclk-name property, oscout system clock is linked to da7219 mclk. da7219 then handles enabling/disabling of the clk. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: I298b0ce5d2c40daadeb5d68f9cb595a965272021 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04drivers/i2c/da7219: Add mclk-name propertyAkshu Agrawal
Non-dts based systems can pass mclk to da7219 driver by this property. BUG=b:74570989 TEST=Enabled clock in kernel driver using the property Change-Id: I2e10769e5b3c6b3aa30f340fe0e88c29b87430cb Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04soc/amd/stonyridge: Add misc deviceAkshu Agrawal
oscout system clock is present in FCH misc device. The kernel acpi misc driver will use the resource to register oscout system clock. BUG=b:74570989 TEST=Tested clock enable/disable in kernel driver Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04ifdtool: Add a list of known platforms that support IFD_VERSION_2Furquan Shaikh
ifdtool has relied on one of the fields within FCBA(read_freq) to determine whether a platform supports IFD_VERSION_1 or IFD_VERSION_2. However, newer platforms like GLK and CNL do not have read_freq field in FCBA and so the value of these bits cannot be used as an indicator to distinguish IFD versions. In the long run, we need to re-write ifdtool to have a better mapping of SoC to IFD fields. But until that is done, this change adds a list of platforms that we know do not support read_freq field but still use IFD_VERSION_2. This change also updates GLK and CNL to pass in platform parameter to ifdtool. BUG=b:79109029, b:69270831 Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04commonlib: Add descriptions for new AGESA timestampsMartin Roth
When the latest AGESA timestamp values were added, the descriptions weren't added along with them. Because of this, the cbmem tool just shows them as "<unknown>". Bug=b:79153552 TEST=None Change-Id: Iad7bcd53bc6136b74d4d933d1a290feac6a0de56 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/26001 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04google/kahlee: Revert "Resume on AC insertion"Martin Roth
This reverts commit edf2f59b1d93a1bc9161a67d3c00a9a05fa8519a. (google/kahlee: Resume on AC insertion) The requirement to wake on AC insert is just to wake enough to charge, not to wake the entire system. BUG=b:77602394 TEST=None Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26014 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-04soc/amd/stoneyridge: Remove USB30PortInit settingMartin Roth
This bitmask sets the USB PORTSC.DR bit for each XHCI port. This is mainboard specific, and only for non-removable devices attached to the XHCI port. BUG=b:72859972 TEST=Boot grunt Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/26015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-05-04mainboard/google: Comment variant names in KconfigMartin Roth
It's very confusing trying to find the google platform names, because they seem all unsorted in Kconfig. They're actually sorted according to the variant name, but previously, that was impossible to tell. - Add a comment to the top of variants in Kconfig.name - Inset each variant name. If you start a prompt with whitespace, it gets ignored, so after trying various ways to indent, the arrow was the option I thought looked the best. It now looks like this: *** Beltino *** -> Mccloud (Acer Chromebox CXI) -> Monroe (LG Chromebase 22CV241 & 22CB25S) -> Panther (ASUS Chromebox CN60) -> Tricky (Dell Chromebox 3010) -> Zako (HP Chromebox G1) Butterfly (HP Pavilion Chromebook 14) Chell (HP Chromebook 13 G1) Cheza *** Cyan *** Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-03mainboard/google/kahlee: Update grunt touchscreen in devicetreeMartin Roth
- Add raydium controller - Update elan controller with reset and enable GPIOs. - Enable 'probed' so Linux will check which controller is being used. BUG=b:78929054 TEST=Both elan and raydium touchscreen controllers work Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03vendorcode/amd/agesa: Fix variable length array declarationKyösti Mälkki
Fix (assumed) regression with commit ac63b41 vendorcode/amd/agesa: Fix variable length array declaration The code used sizeof() on the struct where array length was previously adjusted, but only f14 case was fixed accordingly. Change-Id: Ib83660d5e102e13b4ffad19fb78f695ac4a871dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26036 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03pci: Add dummy file for ARM64Patrick Rudolph
Add stub files to support compiling the PCI driver on ARCH_ARM64. Change-Id: Iaff20463375d1e3ec573d9486a859a0514b0b390 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-03pci: Fix function prototypePatrick Rudolph
Fix a function prototype to support PCI on non x86. The function itself does have the correct argument already. Change-Id: I564fcfe9b85ed4f841a48fe17a3f5bf80e16560b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-03vendorcode/amd/agesa: Fix variable length array declarationPaul Menzel
Definition of S_PSTATE only allowed PStateStruct[0], while it is effectively used as a flexible array. Since sizeof(S_PSTATE) is reduced here by sizeof(S_PSTATE_VALUES), we have to account for that when calculating PStateLevelingSizeOfBytes. In S_PSTATE context, PStateStruct[PStateMaxValue] is valid reference. GCC 7.2.0 warns about an out of bounds array subscript. ``` CC libagesa/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.o src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c: In function 'PStateLevelingMain': src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c:524:65: error: array subscript is above array bounds [-Werror=array-bounds] PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html Change-Id: If9598a951c6b882432689b677a956c44650c7083 Found-by: gcc (Debian 7.2.0-2) 7.2.0 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21297 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03board_status: Remove sudo when checking for cbmem with commandMatthias Gazzari
I get the error below when using the following command in combination with sudo: sudo command -v $SOME_COMMAND sudo: command: command not found Detection of the cbmem path is working fine without sudo. Change-Id: I8788c190ffebde117e2abd3df924c48d8f6fd05d Signed-off-by: Matthias Gazzari <mail@qtux.eu> Reviewed-on: https://review.coreboot.org/25989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-03cpu/x86: Add infinite timeout support into run_ap_work() functionSubrata Banik
There might be certain requirement in user function where user might not want to pass any timeout value, in those cases run_ap_work() should consider infinity as timeout and perform all APs initialization as per specification. Set expire_us <= 0 to specify an infinite timeout. BRANCH=none BUG=b:74436746 TEST=run_ap_work() is running successfully with 0 expire_us. Change-Id: Iacd67768c8a120f6a01baaa6817468f6b9a3b764 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25622 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03mainboard/winent: Remove unnecessary braces {}Elyes HAOUAS
Fix coding style Change-Id: I48a7bd4bd98d1a9d7b0ce4c12e09284fa4be6c7a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03southbridge/broadcom: Remove spaces before/after parenthesisElyes HAOUAS
Change-Id: Ic43b5ddaa395658ab7c34cdd004516884a20b005 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03mainboard/msi/ms9185: Fix coding style and remove commented codeElyes HAOUAS
Change-Id: I3cca4adbf04edfd88a9b8ae52cf4d62d429e6c45 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03mainboard/hp/dl145_g1: Fix coding styleElyes HAOUAS
Change-Id: I8cfddbf49b3042d46956985425990360f0903b1f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-03arch/x86: Relocate GDT in verstage, romstage, and postcarHannah Williams
In each stage keep GDT in the code region. This accommodates platforms, such as glk, that are executing out of CAR. The gdt is small and loading it is trivial so just do it unconditionally instead of introducing another Kconfig. BUG=b:78656686 Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-05-03arch/x86: reduce complexity in assembly_entry.SAaron Durbin
Now that VBOOT_STARTS_IN_BOOTBLOCK depends on C_ENVIRONMENT_BOOTBLOCK, remove the complications in assembly_entry.S. There's no platform utilizing romcc bootblock and needing to handle verified boot after bootblock as well as not using verified boot. That combination makes things very complicated. Clean up the complication as it's not a combination that needs to be supported. BUG=b:78656686 Change-Id: Ie2960790d60ccb8d5b75dab507fe70a6563b3d34 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25968 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03security/vboot: make vboot starts in bootblock depend on c envAaron Durbin
coreboot on skylake originally did ship with romcc bootblock and verstage running after it. However, that configuration makes boot flows very complicated. No platform in the current code base uses this combination. Make VBOOT_STARTS_IN_BOOTBLOCK depend on C_ENVIRONMENT_BOOTBLOCK. BUG=b:78656686 Change-Id: Ia9446f209521f71c91b83d579b9e2d89744292bc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-05-03ec/google/chromeec: Update Tablet event callMartin Roth
The tablet event handler method TPET is defined as an extern, then defined again in skylake, the only platform that supports it. In newer versions of IASL, this generates an error, as the method is defined in two places. Remove the extern and the CondRefOf check. That's not needed if we only set the EC_ENABLE_TABLET_EVENT define on platforms that have a TPET handler. Change-Id: I8bee069fc95637446593dfaaae1254e931421517 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-03mainboard/google/reef: Remove tablet mode switch supportMartin Roth
The _SB.DPTF.TPET ACPI code attached to EC_ENABLE_TABLET_EVENT doesn't exist in the apollo lake code. Remove it from reef as part of the cleanup to update to the new version of IASL. This was in commit 4f803ac28f4 (mainboards/google/reef: Add support for tablet mode switch.) Change-Id: Ic10c418ddc708c1aed87ad4a9861f04d32445116 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02google/kahlee: Set SPI 100 MHz and SPI Dual Read IO modeMarc Jones
Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up the boot process by over a half second. Also, increase the Normal Read speed to 33MHz as supported by the W25Q128FW. BUG=b:70558952 TEST=Run cbmem -t to get boot times. Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-02soc/amd/stoneyridge: remove sb_set_readspeed functionMarc Jones
The sb_set_readspeed() was touching the wrong register and the read speed settings are handled by sb_set_spi100(). Nothing was using the function, so remove it. Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-02mb/google/kahlee/variants/grunt: Enable BayHub720 driverSimon Glass
Enable this driver along with power saving. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: I850e923f73e01fe629d66ad61b65afa58035845c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02drivers/generic/bayhub: Add driver for BayHub BH720Simon Glass
Add a driver which puts the device into power-saving mode. BUG=b:73726008 BRANCH=none TEST=boot and see this message: BayHub BH720: Power-saving enabled 110103 From linux: $ iotools pci_read32 2 0 0 0x90 0x00110103 Change-Id: Idbfb114f3782c9386ce9b487c3abdb0afbc4a0d9 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-02mb/google/poppy/variants/nami: Enable touchscreen through ACPIShelley Chen
Currently, we've set TOUCHSCREEN_DIS gpio to disabled. Enabling through ACPI. Set reset/enable/stop_off_ms variables to get timings of power off sequence correct. BUG=b:78311818 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: Ib1543f41f24cbe8c33aeb02e6aa43fd3dd977ed4 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/25754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-03 14:16:44 +0000