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2020-01-10src/security: Fix typosElyes HAOUAS
Change-Id: I238fce2d48cf62003a701f972a87974415419538 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10mb/google/hatch/variants/helios: Modify DPTF parametersKane Chen
Modify DTRT CPU Throttle Effect on TSR0 change to TSR3. BUG=b:131272830 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I5b4645d7552e795a33c1b86d95c4061da71c65bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38299 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10asus/am1i-a: fix the blue "USB 3.0" ports for OHCI/EHCI "USB 2.0" modeMike Banon
Set up the proper IRQ routing for OHCI/EHCI devices which appear if XHCI controller is disabled (CONFIG_HUDSON_XHCI_ENABLE is not set). Now both "USB 3.0" ports are working fine at OHCI/EHCI "USB 2.0" mode. They also work fine if XHCI controller is enabled. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I50a773eeab890627abc963e0a61f781d1cea3259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-01-10mb/lenovo/t431s/devicetree: Rebalance against t430s onePeter Lemenkov
Change-Id: Iec40dd20c87b97dbd81ba3c63486cb5e66d99dc6 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37600 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/t431s/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I247129317799d342b28f2c0ed68949ecbe7d9c75 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37301 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10src: Remove blank acpi_tables source filesKarthikeyan Ramasubramanian
Due to build rules, dummy acpi_tables source files were added in many mainboards. With commit 1e83e5c61a3aa98f58f7d8cbf8d1eb9532896cc3 ("src/arch/x86: Build mainboard acpi_tables source if present"), the build system will build mainboard acpi_tables only if present. Remove the dummy/empty/blank acpi_tables source files. BUG=None TEST=Build test with some google mainboards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0cef34368e2e5f5e3b946b22658ca10c7caad90a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-10util/inteltool: Add MCHBAR dumping support for Ice Lake U systemsJohanna Schander
According to intels datasheet Document Number: 341078-001 10th Generation Intel® Core™ Processor Families Volume 2 of 2 we can dump the ICL MCHBAR similiar as on 8th / 9th gen CPUs. The difference is that on ICL the MCHBAR address is definited by the bits 38:16 instead of 38:15 giving the constraint that it has to be 64kbit instead of 32kbit aligned. (Section 3.1.13) Change-Id: Ia597a4b3738c11cb48ce5808d8459b4a2a768077 Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-10configs: Build test flashconsolePatrick Rudolph
Change-Id: I70467862b238f8be62eafb5532ede9882dd2f41a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38174 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/hp/*/devicetree.cb: Inherit the subsystemidAngel Pons
Since all the `subsystemid` lines in these devicetrees use the same values, factor them out via inheritance. There are some exceptions though. There are some enabled devices which lack a `subsystemid` entry. Looks like HP uses the same subsystem ID on every device, so assume that these devices should also use that subsystem ID as well. While we are at it, tidy up all the now-empty device blocks. Change-Id: Iccd74fff9456e1204735a80ecc4f7685624cb78e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38081 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10vc/amd/agesa: Remove unused assignmentsJoe Moore
'Status' is assigned a value three times before it is checked. Remove the first two assignments. Change-Id: Id7136d62b4dbd6dce877983467960373b3a7ac22 Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-01-10mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to COM2Michał Żygowski
Enable COM2 port on SuperIO if UART index is 1. This change allows to use full RS232 COM1 port for different purposes when COM2 is selected as main port. TEST=flash coreboot with console on COM2 and observer output with UBS-TTL converter connected to COM2 header on PC Engines apu1 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1e72c5a43a302658f86dafd863e5a67580eae3e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/29791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-10nb/intel/sandybridge: Add a bunch of MCHBAR definesAngel Pons
While we are at it, also: - Rename related variables to match the register names. - Update some comments to better reflect what some registers are about. - Add various FIXME comments on registers that seem to be used wrongly. With BUILD_TIMELESS=1, this commit does not change the coreboot build of: - Asus P8H61-M PRO with native raminit. - Gigabyte GA-H61MA-D3V with native raminit. - Lenovo Thinkpad X230 with native raminit. - Lenovo Thinkpad X220 with MRC raminit. Change-Id: I5e5fe56eaa90842dbbdd1bfbbcb7709237b4c486 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-10mb/facebook/monolith: Remove SDIO controller from devicetreeWim Vervoorn
The SDIO device is disabled so remove it from the devicetree. BUG=N/A TEST=build Change-Id: I6497f6134d8fc001bf4cb7e348ae00077aa34814 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38129 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/facebook/monolith: Enable HDA for HDMI outputWim Vervoorn
The HDA controller was disabled because no codec exists on the board. However, this also disabled audio over HDMI. To correct this, enable Azalia and the HDA controller in the devicetree. BUG=N/A TEST=tested on facebook monolith Change-Id: I7be2c29151dc9d6c247c3332fb9adfb34449c703 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10fsp1_1: Drop unused weak functionNico Huber
All FSP 1.1 platforms override the weak soc_load_logo(). Change-Id: Ib2eae166e02771311c50ea7e4f294790dfa2b99e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38138 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10vc/amd/agesa/f16kb/Proc/GNB: Fix out-of-bounds readJoe Moore
Incorrect values read from a different memory region will cause incorrect computations. VceFlags array size should be 4 based on similar code in f15 branch, and because f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c only loads 4 values for VceFlags in DefaultPpF1ArrayKB. Leaving it at 5 results in an out-of-bounds read of PP_FUSE_ARRAY_V2_fld16 in line 901 of f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c when Index reaches 4. Change-Id: I0242c0634e66616018e6df04ac6f1505b82a630f Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241878 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38056 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/facebook/monolith: Add UNIFIED_MRC_CACHE region in fmd fileWim Vervoorn
The RW_MRC_CACHE was not included in a UNIFIED_MRC_CACHE region which is expected by some parts of the code. Add the UNIFIED_MRC_CACHE and include the RW_MRC_CACHE in this region. BUG=N/A TEST=tested on facebook monolith Change-Id: I1654ca210dc2a8e976d698fd8330641da23e8380 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/**/devicetree.cb: Remove untrue commentsAngel Pons
Even if they were corrected, they just rephrase the code. Change-Id: Iebc4e8c9eb0f44f84acf532ad12a5d064075a102 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10drivers/intel/fsp2_0/logo.c: Correct check for logo_sizeWim Vervoorn
The check to validate if the logo file was loaded correctly was incorrect. Now check the actual logo size. BUG=N/A TEST=build Change-Id: Ib3a808dd831986e8347512892ee88983d376d34c Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38124 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10drivers/intel/fsp1_1/logo.c: Correct check for logo_sizeWim Vervoorn
The check to validate if the logo file was loaded correctly was incorrect. Now check the actual logo size. BUG=N/A TEST=build Change-Id: I4df2076b2f0cc371848a912c622268dfec24e2ef Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10soc/mediatek/mt8183: Restore vcore after DRAM calibrationHuayang Duan
DRAM calibration sets vcore to different voltages at different frequencies. After DRAM calibration, vcore should be restored to the default voltage, which is 800mV for both eMCP and discrete DDR devices. BRANCH=kukui BUG=b:146618163 TEST=bootup pass Change-Id: Ia87b4ac78a32dbd4c4ab52e84d307cb46525afa1 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-01-10mb/lenovo/t530/devicetree: Use subsystemid inheritancePeter Lemenkov
Missing PCI IDs are checked against those collected at https://github.com/linuxhw/LsPCI/tree/master/Notebook/Lenovo/ThinkPad. Change-Id: I61457b7a791dc3341d582f67e651acc6230c525c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37399 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/x1/devicetree: Rebalance against x220 onePeter Lemenkov
Change-Id: Ib009c33d8393d4a76036941ac77965dc12e4ec3e Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37603 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/x1/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I0081b5f219447b110dddfa82cbae51d9ca282f5b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37384 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/x1_1st_gen/devicetree: Use subsystemid inheritancePeter Lemenkov
PCI ID was changed according to the reports from Linux Hardware Project: https://github.com/linuxhw/LsPCI/tree/master/Notebook/Lenovo/ThinkPad Change-Id: I67b81a4c9378c13d557e5d9c5d3797cebeeff5a1 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10timestamps: Fix syncing, logging and commentsKyösti Mälkki
For timestamps added before CBMEM coming online and call to timestamp_sync_cache_to_cbmem(), ts_table->base_time was subtracted twice. The second time though, the value of zero was subtracted. Make the stamps logged on the console relative to base_time too, such that cbmem -1 and cbmem -c outputs will match. Remove comments about postponing initialisation of timestamps to ramstage, that does not happen anymore. Change-Id: Ia786c12c68c8921c0d09bc58a29fefdc72bf0c6d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10timestamps: Fix TIMESTAMPS_ON_CONSOLE behaviourKyösti Mälkki
As logging is guarded by Kconfig, increase the level from BIOS_SPEW to BIOS_INFO. The original callsite inside timestamp_add_table_entry() was also called when syncing from timestamps from .bss to CBMEM. We should not reprint the values then. Change-Id: I72ca4b6a04d8734c141a04e651fc8c23932b1f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-10mb/google/fizz: Add Endeavour variantJeff Chase
Use the existing Karma variant as a base. BUG=b:144307303 TEST=build Change-Id: I09a10e99877d18361b31b36bed703b02508ccd05 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10src/device: Update pci_class to PCI-SIG SpecificationElyes HAOUAS
Update based on PCI-SIG's specification: "PCI code and ID assignment specification, Rev 1.11 (24 Jan 2019)" Change-Id: If51605719fd96e399aec2ae86caedda44f2648d4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/msi/ms7707/devicetree.cb: Align contentsAngel Pons
Change-Id: I2e8100d01d1feb29df83c400f712e58ae9a5e402 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/wtm2/devicetree.cb: Align commentsAngel Pons
Change-Id: I701aea4656e59a369c2e663438a4b2f9644f0ed6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/emeraldlake2/devicetree.cb: Align contentsAngel Pons
Change-Id: I4ad24a011bd0711dc9a1133dc6188a213cc3926b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/dg43gt: Make devicetree prettierAngel Pons
Use lowercase for hex constants and align comments and register values. Change-Id: Ib14906113e366a2a6f268fe8b8be32b1794fb344 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38077 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/intel/dcp847ske: Make devicetree prettierAngel Pons
Align contents and fix some redundant comments. Change-Id: I45fb02ac90fe3d280379b08c9931f1064c71633f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/foxconn/d41s/devicetree.cb: Indent with tabsAngel Pons
As on most other boards, use tabs to indent the devicetree. Change-Id: I1d2fd6e758a3b2dccb8fc43d425f4520fd2e544f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38075 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/compulab/intense_pc: Reformat devicetreeAngel Pons
Use subsystemid inheritance, which results in a much more compact devicetree. In addition, align and correct various comments. Change-Id: Iafce736691b62ae8f359c2d74f8bd3549493029a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/compulab/intense_pc: Drop zero valuesAngel Pons
They default to zero already. Change-Id: Iaa557b18c34584dccb5c889ab8bd2173ed4ea04b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/roda/rk886ex/devicetree.cb: Align commentsAngel Pons
Change-Id: I67e3149657c04f72aac0b20bc31af338129a13b2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5ql-em/devicetree.cb: Do minor fixesAngel Pons
Use lowercase for hex constants, remove registers that default to zero already and drop outdated comment about AHCI mode. Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8z77-m_pro: Make devicetree prettierAngel Pons
Align comments, and make PCIe port comments consistent. Change-Id: Id39337236deff7721183e749a6b63aadaa036b2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qc/devicetree.cb: Drop zero valuesAngel Pons
They default to zero already. Moreover, the comment about AHCI mode no longer applies, as it was made the default mode. Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qc/devicetree.cb: Do minor cosmetic fixesAngel Pons
Use lowercase for hex constants and align some comments. Change-Id: I418ed29dfbc90feb591a2b30e994d9b3e6176f86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qpl-am/devicetree.cb: Do minor cosmetic fixesAngel Pons
Use lowercase for hex constants, inline a lone `end` and align a comment. Change-Id: Ibf3882dd134d33611138c2a9f89a3b2b37c136b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8h61-m_pro: Make devicetree prettierAngel Pons
Replace a bunch of spaces with tabs, put host bridge and friends above southbridge, fix "TPM Module" (Trusted Platform Module Module) and add some empty lines to help the reader. Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8h61-m_pro/devicetree.cb: Drop zero fieldsAngel Pons
They default to zero already. Change-Id: I5c99043f16bc65de952afa0ce8d40bf947bfee15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/veyron/devicetree.cb: Drop illogical commentAngel Pons
This comment seems to have been copied off some QEMU board. As it would not apply to any veyron variant, drop it. Change-Id: I70a2923520f5c59ae31d149920cf4b096e5a11d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/nyan/devicetree.cb: Correct some commentsAngel Pons
Use a consistent spelling for SoC (System-on-a-Chip), and fix a few minor typos. Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource properSubrata Banik
This patch ensures coreboot is not publishing above 4GB mmio resource if soc common config "enable_above_4GB_mmio" not enable. Publishing unnecessary 4GB above MMIO resource with wrong base and size is causing problem while working with discrete GPU. Unable to boot with dGPU on IA platform with below error: [ 2.297425] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.302858] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.309427] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.316679] pcieport 0000:00:1c.0: bridge window [mem 0x840000000-0x8c01fffff 64bit pref] [ 2.325072] pcieport 0000:00:1c.0: PCI bridge to [bus 05] [ 2.330502] pcieport 0000:00:1c.0: bridge window [io 0x2000-0x2fff] [ 2.337062] pcieport 0000:00:1c.0: bridge window [mem 0xb2000000-0xb20fffff] [ 2.344317] pcieport 0000:00:1c.0: bridge window [mem 0xa0000000-0xb01fffff 64bit pref] [ 2.352541] [drm] Not enough PCI address space for a large BAR. Change-Id: I77b3a0e44582b047d7fbe679d3000d616f7e6111 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2020-01-10drivers/spi/spi_flash: explicitly handle STMicro deep power stateAaron Durbin
In order to provide more consistent probing in future refactorings, pull out the release from deep sleep path in STMicro's SPI flash probing function. Call that function explicitly when RDID doesn't return anything at all. The old STMicro parts, even if supporting RDID, won't decode that instruction while in a deep power down state. Instead of re-issuing RDID after the successful wake assume the id fixup is valid. Change-Id: I46c47abcfb1376c1c3ce772f6f232857b8c54202 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-09sb/intel/common: Add smbus_set_slave_addr()Kyösti Mälkki
Change-Id: I7dddb61fab00e0f4f67d4eebee0cfe8dcd99f4ab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38230 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 00:30:15 +0000