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2017-11-25util/intelmetool: Fix lint errors and warningsPatrick Rudolph
Clean the code to fix all errors and warnings. No functional change. Changes: * Fix lines over 80chars * Fix typos * Restructure code to reduce indent level * Move RCBA handling into own files * Introduce helper functions for RCBA access * Move GPL string into header * Fix whitespace in macros Change-Id: Ib8e3617ebb34c47959d6619dfbc7189045e6b8f7 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-11-25google/fizz: Remove tpm i2c configs from KconfigShelley Chen
We are disabling tpm over i2c, so the configs are not needed anymore. BUG=b:65056998 BRANCH=None TEST=emerge fizz and make sure can still boot up. Change-Id: Id88f32fa952801749544534442fc15d85fc1a892 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25google/fizz: Disable unused i2c linesShelley Chen
As cr50 has now switched to using SPI, no need to enable the i2c1 anymore. Additionally, disabled unused I2C devices -- I2C0, I2C2 and I2C3. BUG=b:69374421 BRANCH=None TEST=test on fizz celeron. Make sure /dev/tpm0 created on (many) reboots. cat /proc/interrupts. Make sure # interrupts for 16 after booting is reasonable (not > 10k) and idma64.0, i2c_designware.0 are not listed with that interrupt line anymore. Should look something like this: 16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-23soc/intel/cannonlake: Add PM methods to power gate SD card controllerVaibhav Shankar
When system enters S0ix, system fails to power gate SD card controller. This patch implements PM methods to put the SD card controller in D3 during S0ix entry. TEST=Suspend and resume using 'echo freeze > /sys/power/state'. The System should not be blocked by sd card controller. Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/22487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-23google mainboards: select SYSTEM_TYPE_LAPTOP where appropriateMatt DeVillier
Some Google boards are missing this selection, leading them to being incorrectly identified as type 'Desktop' in SMBIOS type 3 table. Correct this by adding 'select SYSTEM_TYPE_LAPTOP' to the boards' Kconfigs. TEST: boot Linux and check correct chassis type listed via dmidecode Change-Id: Ib1145e314812a3f300cfd1a435a687aa0862158a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23src/mainboard: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23soc/intel/cannonlake: Invoke pmc and hard reset only if CSE fails to resetJohn Zhao
If CSE fails to do a global reset with the calling sequence of heci reset/send/receive, then invoke pmc and hard reset. TEST= Force global reset from early or late romstage. The function send_heci_reset_message has the calling sequence of heci reset/send/receive. It is observed timed out error (associated with heci_receive) occurs only if global reset is forced during early romstage. If global reset is trigged at late stage (i.e, after fsp_memory_init), then no timed out error and CSE handles reset properly. Change-Id: I5bb12554e5745d7704a1b684a3a51034bb35f787 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22549 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
There is currently no case where a struct cpu_device_id instance needs to be modified. Thus, declare all instances as const. Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23sb/intel/i82801jx: Store initial timestamp in bootblockArthur Heymans
The function to fetch this timestamp is already present. Change-Id: I760aea8a867339764be9ca627b2ccdff4fd18e30 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23sb/intel/i82801ix: fetch initial timestamp in bootblockArthur Heymans
TESTED on Thinkpad x200 Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-23google/fizz: Define smbios_mainboard_sku to return OEM IDsShelley Chen
Currently, mosys just returns "fizz" as model/chassis values. Returning proper OEM IDs so that mosys can return the proper variant. BUG=b:67732053 BRANCH=None TEST=mosys platform model; mosys platform chassis; Make sure returns the right variant string and not fizz. Change-Id: I42e293e833b0f7c9870dc275561ad13256836e60 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-23soc/amd/common: Include appropriate headers in dimm_spd.hMarc Jones
Change-Id: I69e8eaffefbda4fdfb89264a55762558950aa5e2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23soc/amd/stoneyridge: Get entire DDR4 SPDMarc Jones
Set the SPD size to 512 to get the entire DDR4 SPD. Change-Id: I0bdf8101de22533b2f4337d3c9e4423d62e6c66d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22chromeec: Change the API for hostevent/wake masks to handle 64-bitFurquan Shaikh
ChromeEC is getting ready to bump up the hostevents and wake masks to 64-bits. The current commands to program hostevents/wake masks will still operate on 32-bits only. A new EC host command will be added to handle 64-bit hostevents/wake masks. In order to prevent individual callers in coreboot from worrying about 32-bit/64-bit, the same API provided by google/chromeec will be updated to accept 64-bit parameters and return 64-bit values. Internally, host command handlers will take care of masking these parameters/return values to appropriate 32-bit/64-bit values. BUG=b:69329196 Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22google/gru: Add support for rainierEge Mihmanli
Rainier is a scarlet-derived board but uses eDP as opposed to MIPI. Using GRU_BASEBOARD_SCARLET is enough, except for display related logic. In those cases, use board specific logic instead of baseboard. Change-Id: I596f7ca6bc26312ecaeb261c96cebd46974c2cdf Signed-off-by: Ege Mihmanli <egemih@google.com> Reviewed-on: https://review.coreboot.org/22542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-22vendorcode/amd/pi/00670F00: Halt build if headers aren't wrappedMartin Roth
Make sure that AGESA headers don't get pulled directly into coreboot files again. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee; Include AGESA.h into files verify that the build fails. Change-Id: I8d6d94872ebf76a9df2850ed0452cf6b1a446ffd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22vendorcode/amd/pi/00670F00: Remove direct AGESA header includesMartin Roth
Update amdlib to pull in the AGESA headers through agesa_headers.h BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: I3a2a2fde9738a9fe7a0b55cb91c29416cdc227a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22Create SOC description file soc.aslRichard Spiegel
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge several includes into a single file in soc directory. Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl. Then copy the required section from dsdt.asl into a new soc.asl. Affected boards: amd/gardenia and google/kahlee. BUG=b:69368752 Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22541 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-22build system: drop duplicate rule for $(objutil)/blobtool/blobtoolPatrick Georgi
There's already one in util/blobtool/Makefile.inc BUG=chromium:787042 TEST=no more warning about duplicate rules Change-Id: I8bc17d3b182369cf5b67bdcf392db7932e5389bf Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22555 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-22drivers/i2c/tpm/cr50: Simplify and increase init delay to 30 secondsDuncan Laurie
The Cr50 i2c driver provides separate entry points for probing and initialization, but probing function does not really do much. It also claims and releases locality on every coreboot stage, but there is no need for this - locality should be definitely claimed after reset and then it could be retained through the boot process. On top of that the driver does not properly account for long time it could take the Cr50 chip to come around to reset processing if TPM reset request was posted during a lengthy TPM operation. This patch addresses the issues as follows: - tpm_vendor_probe() and tpm_vendor_cleanup() become noops, kept around to conform to the expected driver API. - tpm_vendor_init() invokes a function to process TPM reset only in the first stage using TPM (typically verstage), the function checks if locality is claimed and if so - waits for it to be released, which indicates that TPM reset processing is over. - before claiming locality check if it is already taken, and if so - just proceed. BRANCH=none BUG=b:65867313, b:68729265 TEST=Verified that reef no longer hangs during EC reboot and firmware_Cr50ClearTPMOwner (not yet merged) tests. Change-Id: Iba8445caf1342e3a5fefcb2664b0759a1a8e84e3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-21spi/tpm: claim locality just once during bootVadim Bendebury
All coreboot stages using TPM start with the same sequence: check if locality is claimed, if so, release it by writing 'active locality' bit, then try claiming it. This is actually not a proper procedure: section "5.5.2.3.1 Command Aborts" of "TCG PC Client Platform TPM Profile (PTP) Specification Level 00 Revision 00.430 Family 2" lists overwriting active locality status bit as a means of triggering TPM command abort. On top of that, none of the coreboot stages releases locality, it is enough to claim it once when device starts booting. In fact, locality being active when the device is in verstage is most likely due to delayed TPM reset processing by the Cr50 TPM: reset is an asynchronous event, and is processed once current command processing completes. The proper procedure is to wait if locality is active until it is released (which will happen when Cr50 processes reset) and then proceed to claim it. This needs to happen only during verstage, other stages using TPM are guaranteed has been claimed earlier. BRANCH=gru BUG=b:65867313 TEST=the new autotest triggering EC reset during key generation process does not cause boot failures on Fizz device any more. Below are times verstage had to wait: TPM ready after 3132 ms TPM ready after 22120 ms TPM ready after 4936 ms TPM ready after 6445 ms TPM ready after 11798 ms TPM ready after 27421 ms TPM ready after 4582 ms TPM ready after 7532 ms TPM ready after 27920 ms TPM ready after 3539 ms TPM ready after 12557 ms TPM ready after 6773 ms TPM ready after 1631 ms TPM ready after 197 ms TPM ready after 24330 ms TPM ready after 3241 ms Change-Id: Iaee04f009bcde03712483e5e03de4a3441ea32b1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-21src/soc/intel/apollolake: move TCO1 disable into bootblockVadim Bendebury
Cr50 reset processing could take long time, up to 30 s in the worst case. The TCO watchdog needs to be disabled before Cr50 driver starts, let's disable it in bootblock. BRANCH=none BUG=b:65867313, b:68729265 TEST=verified that resetting the device while keys are being generated by the TPM does not cause falling into recovery. Change-Id: Iaf1f97924590163e45bcac667b6c607503cc8b87 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/22553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21arch/x86: Write ACPI DBG2 table only if the device has been enabledMario Scheithauer
The commit 93bbd41e (soc/intel: Enable ACPI DBG2 table generation) causes a crash on the mainboard mc_apl1. On this mainboard all internal SOC UARTs in the devicetree are switched off. As a result, no resources are allocated to the UARTs. The function find_resource() expects an existing resource. Otherwise, the CPU will stop. It should therefore not only be queried whether a device is present, but also whether it is enabled. Change-Id: I56ce44ae0cf77916fcb640f79fb8944fe33177cd Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-21vendorcode/amd/pi/00670F00: Clean up makefileMartin Roth
- Remove unnecessary cflags, exports, and variables - Don't include AGESA cflags in the entire build - Reformat build target BUG=b:69220826 TEST=Build Change-Id: I60cb20a3849439cb808f5d3919588853e9c8c734 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21soc/amd/stoneyridge: Add ELOG to SMMJohn E. Kabat Jr
1. Add ELOG entries to smihandler.c 2. Add save_state utilities that are needed by southbridge_smi_gsmi BUG=b:65485690 Change-Id: I458babe1694f042215dd0e1c3277856e340de86f Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com> Reviewed-on: https://review.coreboot.org/21728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21amd/stoneyridge/spi: Fix reads greater than 5 bytesMarshall Dawson
This corrects a bug in 918c8717 "amd/stoneyridge: Add SPI controller driver". Pass a pointer to din to the do_command() function so the caller's copy is correctly updated. The bug allowed reads <= 5 bytes to work correctly (3 bytes consumed in the FIFO by the address) but overwrote data in the din buffer on larger transfers. Change-Id: I32b7752f047112849871cafc9ae33c5ea1466ee1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21soc/amd/common: Remove duplicated #include amd_pci_int_defs.hRichard Spiegel
Remove <#include amd_pci_int_defs.h> from amd_pci_util.h, as the user of the functions declared in amd_pci_util.h don't need the contents of amd_pci_int_defs.h. BUG=b:62200907 Change-Id: I258d549d3eea3fb8919c0cddbb41dc2bc4738c4e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21mb/google: Update/add ChromeOS device marketing namesMatt DeVillier
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added marketing names for many ChromeOS devices; add some that were left out, correct some errors, and try to format model names/numbers consistently (or as consistently as the manufacturers allow). Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20mainboard/google/fizz: Enable separate MRC cache for recovery modeShelley Chen
Enable separate MRC cache for recovery mode. This requires change in flash layout to accomodate another region for RECOVERY_MRC_CACHE. BUG=b:69473883 TEST=Verified following scenarios: 1. Boot into recovery does not destroy normal mode MRC cache. 2. Once recovery MRC cache is populated, all future boots in recovery mode re-use data from the cache. 3. Forcing recovery mode to retrain memory causes normal mode to retrain memory as well. Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/22518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-20google/gru: Add config for scarlet-derived boardsEge Mihmanli
There is merit in having new boards use the pinouts and controls in scarlet. This adds a config so new scarlet-derived boards can easily use scarlet structure without going through every file and adding new logic. TEST=Run "emerge-scarlet coreboot" Signed-off-by: egemih@chromium.org Change-Id: I5808f93f4563033ce93050e1eedb6eac2b52c3b3 Reviewed-on: https://review.coreboot.org/22517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-20soc/intel/cannonlake: Add ACPI workaround for EMMCLijian Zhao
Two W/A had been added here for EMMC to make it working properly. 1. Enable power gating after D3 entry, disable power gating before D0 entry. 2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of D3. BUG=b:69323943 TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform. Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20amd/stoneyridge: Fix SPD files and functions camel caseMarc Jones
Remove ugly camel case in the soc/amd/common and Stoney Ridge SPD files and functions. Update the related mainboards. Also, remove a unreferenced function prototype, smbus_readSpd(). Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19include/timer.h: add NSECS_PER_SEC macroLin Huang
Change-Id: I4367f84be5a4bd635b422b6e7cbdc9aa3ccfbf5c Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/22466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-19vendorcode/amd/pi/00670F00: Remove dependency on amd/include dirMartin Roth
Copy the two headers used by the Stoney BinaryPI implementation into the 00670F00 directory so that any changes that are made to them don't affect other platforms. BUG=b:67299330 TEST=Build Change-Id: I5d37fac72871f2617c4be45c151741436cbfce96 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mb/google/kahlee: Move ec.h into variant include directoriesMartin Roth
The mainboard directory is included through the PI makefile - most mainboard directories aren't in the include path at all. Move the ec.h file into the baseboard/variant directory that is already in the include path. BUG=b:69220826 TEST=Build Change-Id: I89d361b700c66ba576de724927574fdab9461fc6 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19vendorcode/amd/pi/00670F00: Remove cpuFamilyTranslation.cMartin Roth
The file Proc/CPU/cpuFamilyTranslation.c isn't being included into the build, so it's obviously not needed. BUG=b:69220826 TEST=Build Change-Id: Id244d110b4f15e1d6af6c701f62e2f05d7eb289a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h I missed this file in the Kahlee cleanup. BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19mainboard/google/kahlee: Update memory.cMartin Roth
This fixes some issues with the initial implementation that was copied from reef. - The board ID value shouldn't be size_t - it's not a size. - Kahlee doesn't even need the memory.c file - it uses an SoDIMM. BUG=b:68293392 TEST=build stoney platforms, boot kahleebo Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22515 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17mb/google: Add Chromebook marketing namesJonathan Neuschäfer
It's sometimes hard to find the code name of a Chromebook. Add the marketing names to Kconfig, since they are easily available. Information (mostly) taken from: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices Unknown boards (unreleased, etc.): * Fizz * Foster * Nasher, Coral * Purin * Rotor * Rowan * Scarlet, Nefario * Soraka * Urara * Veyron_Rialto Baseboards: * Glados * Gru * Jecht * Kahlee * Nyan * Oak * Poppy * Rambi * Zoombini White label boards: * Enguarde * Heli * Relm, Wizpig TODO: How does this interact with the board_status code? Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-17Move amd/stoneyridge/include/amd_pci_int_defs.h to include/soc/Richard Spiegel
Move src/soc/amd/stoneyridge/include/amd_pci_int_defs.h to src/soc/amd/stoneyridge/include/soc/. After much discussion, src/soc/amd/stoneyridge/include/soc is probably the best location. It was found that there are other common code that include headers from this folder. BUG=b:62200907 Change-Id: I69e0a54e5d64ae28919871c687a0177786b789c8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-17amd/gardenia: Add defines in OemCustomize.cMarshall Dawson
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I81aa0165660e7627f1d977ac40479700cff8b80b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21854 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17soc/intel/cannonlake: fix gpio pin numbersBora Guvendik
Update pin numbers to match kernel cannonlake pinctrl driver. TEST=boot to OS Change-Id: Id65736db03200fd434dd9292ce081727abd6832b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22477 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17soc/intel/cannonlake: Add cpu.asl fileShaunak Saha
This patch adds the cpu.asl file in cnl. We are only defining the PNOT method here in this patch as this is needed by the ec/google/chromeec/acpi/ec.asl file for the AC methods. TEST= code compiles and boots when we include the ec.asl file. Change-Id: Id93012833fac116d4d7514aa2d0b8493d2f666a9 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/22365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-17amd/stoneyridge: Enable SMI trap on SlpTypMarshall Dawson
Program PMx08 to support SMIs when software writes the SlpTyp bit in the Pm1Control register. The southbridge needs to send the SMI message prior to the completion response of the I/O cycle. Also, disable sending the STPCLK message before the completion response. Disable the SlpTyp functionality, then enable the SMI source. BUG=b:65595850 Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17amd/stoneyridge: Add SlpTyp SMI handlerMarshall Dawson
When an SMI occurs due to SlpType, interpret the type of request being made. If it's S3 or higher, flush the cache and disable further SMIs. Reenable SlpTyp functionality in the ACPI logic and reissue the cycle. BUG=b:65595850 Change-Id: I88d413cdbfc2daf44e8d1142c6532f7034795ead Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17amd/stoneyridge: Add SPI controller driverMarshall Dawson
Add more definitions for the controller registers and fields. Add source that is adapted from hudson and updated for Stoney Ridge. This was tested with follow-on patches that write S3 data to flash. BUG=b:68992021 Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-17mb/lenovo/t400/blc.c: Add LTN154P2-L05 to whitelistKevin Keijzer
TESTED on Lenovo T500 Change-Id: I5546641cb34264e29ccb3398dd68f6144dafe524 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/22367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-17mb/lenovo/t400: Add LTN154X3-L02 to list of known displaysKevin Keijzer
TESTED on Lenovo T500 Change-Id: I9c9fef82ca4af99c7d4813e0ab0e315fde93b972 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/22475 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-11-16vendorcode/amd/pi/00670F00: Get rid of filecodes, replace filecode.hMartin Roth
coreboot doesn't need AGESA's version of Filecode.h. Some of the files that have been copied from AGESA include the header, so we can't get rid of it completely yet. - Remove includes from files that weren't copied from the AGESA source. - Remove FILECODE definitions from coreboot source. BUG=B:69220826 TEST=Build Gardenia; Build & boot Kahlee. Change-Id: If16feafc12dedeb90363826b62ea7513e54277f4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-16vendorcode/amd/pi: Create stoney version of amdlibMartin Roth
Copy the vendorcode/amd/pi/Lib directory into 00670F00 directory and update the 00670F00 Makefile to use it instead of using the common version. This allows changes to stoney without affecting the rest of the AMD binary PI platforms. BUG=b:67299330 TEST=Build Gardenia; Build & boot kahlee Change-Id: I2fe4303f882938e9d917a3001476213f49426455 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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