summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/{cnl,icl,skl}: Convert 'platform.asl' to ASL 2.0 syntaxSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I3fcd971402e540d91a7392ca58175eb3ecc24cec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45981 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/skylake: Align platform.asl with CNLSubrata Banik
Refer _WAK and _PTS ASL functions from common platform.asl TEST=Dump and disassemble DSDT, verify all methods present inside common platform.asl like _WAK, _PTS etc. are still there. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I625e42b3c49abbb3595a4307da5fc24850a98fbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/45980 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/common/block/acpi: Factor out common smbus.aslSubrata Banik
This patch moves smbus.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify SBUS device present inside common smbus.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05mb/{google,intel}/{volteer,tglrvp}: Refer to common IPU ASLSubrata Banik
Delete SoC local copy of ipu.asl and refer from common block ipu.asl TEST=Dump and disassemble DSDT on tglrvp, verify IPU0 device present there. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I6a0f8a919092f7bbcd64d4791746d30fdee33894 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/jasperlake: Delete unused ipu.aslSubrata Banik
Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I8c7363d442ed40c36fc01dc3608bab864865f29d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45977 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/common/block: Rename IPU ACPI deviceSubrata Banik
IMGU->IPU0 to align with other SoC IPU entires. TEST=Dump and disassemble DSDT on poppy, verify IPU0 device present there. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I803c01f9156a56dbd903b6ba7897cc0f96b0a26a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05soc/intel/common/block/acpi: Factor out common pch_glan.aslSubrata Banik
This patch moves pch_glan.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify GLAN device present inside common pch_glan.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03Revert "util/spd_tools: output binaries instead of hexdumps"Rob Barnes
This reverts commit f23794cf04030bb8d1d7ebe0a3634dffd092e2f7. Reason for revert: This change breaks compatibility if the changes in CB:44775 are not also included. CB:44775 is still under discussion, so revert this change to make spd_tools usable again. Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I5840a1b895dcbc8b91c76d8b60df2f95b93a4370 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44999 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/alderlake/ramstage: Do initial SoC commit till ramstageSubrata Banik
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel/xeon_sp/acpi: Rename pci_irq.aslMarc Jones
Rename pci_irq.asl to pci_irqs.asl to match other intel soc file names. This makes comparing differences much easier. Change-Id: I622dfef675c3df2dff7a3024ccbe14c356a5cd86 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45834 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp: Clean up pci_devs.hMarc Jones
Prepare for merging cpx and skx pci_devs.h. Remove duplicate defines. Move defines so they match each other. Checked TiogaPass and DeltaLake BUILD_TIMELESS. Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45833 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Make use of PMC low power program from common blockSubrata Banik
List of changes: 1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory 2. Remove redundant PMC programming from SoC and refer to common code block 3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC function. Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/common/block/pmc: Add PMC API for low power programmingSubrata Banik
List of changes: 1. Create Kconfig to select pmc low power program by SoC 2. Add API to make ACPI timer disable 3. Add API to ignore XTAL shutdown for SLP_S0# assertion Change-Id: I017ddc772f02ccba889d316319ab3d5626b80ba5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Move pch_misc_init() to common codeSubrata Banik
List of changes: 1. Move pch_misc_init() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. 3. Create macros for IO port 0x61 and 0x70 as applicable. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: Ie36ee63869c076d251ccfa5409001d18f22600d7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Move soc_pch_pirq_init() to common codeSubrata Banik
List of changes: 1. Rename soc_pch_pirq_init() as pch_pirq_init() and move into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I856b5ca024e58fd14b4d1721f23d9516a283ebf8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel: Move pch_enable_ioapic() to common codeSubrata Banik
List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel/xeon_sp/include: De-duplicate .h filesMarc Jones
Move duplicate .h files to top level xeon_sp/include/soc from silicon specific cpx/include/soc and skx/include/soc. Change-Id: I11d8a95a4b2f9451615b236798b3bd030c724858 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45221 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Prepare acpi.* for mergingMarc Jones
Clean up acpi.h in preparation for merging with cpx/ acpi.* files Change-Id: I2a0dc964eeb7f8da53676eb94c4385ff8668f6af Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45218 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp: Use common ASL code for xeon_spMarc Jones
Move and use the common xeon_sp/cpx/acpi asl for skx/. There were only minor whitespace differences between the directories. Update the mainboards to build the moved files. TiogaPass coreboot.rom checked with BUILD_TIMELESS. Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Fix uncore.asl \_SB namespace issueMarc Jones
The skx uncore ACPI scope was missing the \ on \_SB causing the uncore IRQs to not be in the namespace. This addresses ACPI uncore IRQ routing issues. This was found preparing skx acpi to match cpx acpi for merging in the future. Check scope in dsdt.asl in tiogapass build. Change-Id: I799042babbe60287e5e4ec60b21c08d57ccda04b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45269 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Update ITSS OperationRegion to ACPI2.0 notationMarc Jones
Prepare for merge with cpx. Use the C style operators instead of the ACPI1.x polish notation. This is much easier to read and matches the cpx code. This generates the same ASL code. Checked with BUILD_TIMELESS on TiogaPass. Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45270 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Update uncore IRQ routing ACPI tablesMarc Jones
Update the skx uncore ACPI routing tables to match cpx. This adds the IRQ routing for B-D for legacy and IOAPIC modes. Change-Id: Iac0ffdb467a78b9befe7402c074835ea602d43c8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-02mrc_cache: Update mrc_cache data in romstageShelley Chen
Previously, we were writing to cbmem after memory training and then writing the training data from cbmem to mrc_cache in ramstage. We were doing this because we were unable to read/write to SPI simultaneously on older x86 chips. Now that newer chips allow for simultaneously reads and writes, we can move the mrc_cache update into romstage. This is beneficial if there is a reboot for some reason after memory training but before the previous mrc_cache_stash_data call originally in ramstage. If this happens, we would lose all the mrc_cache training data in the next boot even though we've already performed the memory training. Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't do mmapping but still want to use the cbmem to store the mrc_cache data in order to write the mrc_cache data back at a later time. We are maintaining the use of cbmem for these older platforms because we have no way of validating the earlier write back to mrc_cache at this time. BUG=b:150502246 BRANCH=None TEST=reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44196 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02soc/intel/braswell: Increase dcache sizeShelley Chen
Increase the DRAM cache size for Braswell to address the compilation error Cache as RAM area too full when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage. BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45827 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-02mb/clevo/l140cu: Add variant specific romstage.c to buildFelix Singer
While restructuring the mainboard directory, it was forgotten to add the variant specific romstage.c to the build. Therefore, add romstage.c to the Makefile fixing the raminit. Change-Id: I7afbf1574803128f7d62592eed2398c945334757 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45928 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-02amdfwtool: Fix the gcc warning about sign comparisonZheng Bao
New (maybe) compile tool complains the warning below. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Fix all of them. Change-Id: I59624326233284e6c3595df49625563254949c45 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-02drivers/intel/fsp2_0: use FSP to allocate APEI BERT memory regionJonathan Zhang
APEI (ACPI Platform Error Interface) defines BERT (Boot Error Record Table) memory region: * Bootloader (firmware) generates UEFI CPER (Common Platform Error Record) records, and populates BERT region. * OS parses ACPI BERT table, finds the BERT region address, inteprets the data and processes it accordingly. When CONFIG_ACPI_BERT is defined, update FSP UPD BootLoaderTolumSize, so FSP allocates memory region for it. The APEI BERT region is placed on top of CBMEM, for the size of CONFIG_ACPI_BERT_SIZE. Apart from APEI BERT region, we also have plan to add APEI HEST region which holds OS runtime hardware error record, based on firmware first hardware error handling model. HEST region will be reserved same way as BERT region. Note that CBMEM region can not be used for such purpose, the OS (bert/hest) drivers are not able to access data held in CBMEM region, as CBMEM is set as type 16 (configuration table). An option considered was to reserve the BERT region under CBMEM. However, we do not know the size of CBMEM till acpi tables are set up. On the other hand, BERT region needs to be filled up before ACPI BERT table is finalized. Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-02util/ifdtool: Include ADL dynamic check as per Gen12 SPI flash guideSubrata Banik
BUG=b:153888802 TEST=Able to list correct PCH revision, SPI/eSPI frequency as per ADL SPI flash guide. Without this CL : PCH Revision: 500 series Tiger Point With this CL : PCH Revision: 500 series Tiger Point/ 600 series Alder Point Change-Id: I0faf0f0fdb625ff82eb0033b5b77e6470971bc23 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-01mb/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C ↵Jason Le
displays for TGL-Y RVP - Enable DDC pins for DDI-B - Enable HPD pins for DDI-1/DDI-2 - Update MPHY/USB2 Mapping to match with the TGL-Y RVP schematic BUG: System not able to detect displays attached to onboard micro-HDMI or Type-C connectors TEST: hot-plug/unplug HDMI displays with onboard micro-HDMI connector and USB Type-C connectors to make sure the displays get detected and enabled Change-Id: I08a1b16a8fa45cf0f366661395b9f2aa25c44935 Signed-off-by: Jason Le <jason.v.le@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-01drivers: sn65dsi86: Retry link training up to 10 timesJulius Werner
The kernel guys have found that automatic link training from this bridge can occasionally fail and needs to be retried. They have added up to 10 retries just to be sure, so let's do the same in coreboot. BUG=b:169535092 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I713b6851bd51d3527ed4c6e6407dee6b42d09955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45882 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01mb/google/zork: Configure EMMC_RESET_L to drive highKevin Chiu
Configure EMMC_RESET_L (GPIO68) to drive high by default. As per JEDEC specification for eMMC, RST_n_FUNCTION defaults to temporarily disable reset using RST_n signal (which is connected to EMMC_RESET_L on zork). Chrome OS platforms do not configure RST_n_FUNCTION thus making the reset signal unused. The spec also says that there are no internal pulls on the card and hence the RST_n signal should be driven appropriately to prevent the input circuits from flowing unnecessary leakage current. Thus, even though the line remains unused, since it is connected in hardware, this change drives EMMC_RESET_L to high. BUG=b:169222156 BRANCH=zork TEST=emerge-zork coreboot eMMC DUT reboot/suspend x100 iterations pass Change-Id: I9feb826eec8a8cdad5e2bd7efcbb1dcf96185dfd Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-10-01security/intel/stm: Fix size_t printf format errorFelix Held
This sort-of reverts commit 075df92298fe3bb0ef04233395effe668c4a5550 and fixes the underlying issue. The printf format string type/length specifier for a size_t type is z. Change-Id: I897380060f7ea09700f77beb81d52c18a45326ad Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eugene Myers <cedarhouse1@comcast.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-10-01mb/clevo/l140cu: Align comment with rest of the devicetreeFelix Singer
Change-Id: Idcaedd3d5b7e465644f79e5a882e42eff040fdbd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-01vc/amd/fsp/picasso: Add bit definitions for PSP info in transfer blockMartin Roth
BUG=b:168895748 TEST=None BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I299fdd0f007f7e4a8f597931a52f68dc98acc9ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/45804 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01mb/google/zork: Initialize the backlight in the OSMartin Roth
This fix needs to go into ACPI in the long-term, but this should suffice in the short-term. BUG=b:158087989 TEST=Boot berknip, verify backlight is enabled. Test suspend & resume sequence, backlight is still enabled. BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6ecc3c9e397c9756a78e480d3f639c507879a0ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/45854 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-01mb/google/zork: Remove code that reconfigured the backlight GPIOMartin Roth
The SMU code was assuming that GPIO 85 was used for a fan, which caused interesting backlight flickering. That has now been fixed, so remove the code that reconfigured it to a GPIO on resume. BUG=b:155667589 TEST=Verify the screen does not flicker on resume from S3 BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6d4f9d98e9df52fefab9b20d0ab0f0b67512d356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-30mb/amd: Add Pollock CRB Cereme as Mandolin variantFelix Held
Even though the devicetrees of Mandolin and Cereme are relatively similar, they are kept as separate files instead of using devicetree overrides to facilitate creating mainboard ports based on those CRBs. The two boards are reference boards for different zen/zen+ APU platforms that share the silicon, but use different packages. This is also consistent with the google/zork boards that have two different full base devicetrees for the two different platforms and then use devicetree overrides for the different variants of the two reference designs. BUG=b:159617786,b:169644059 BRANCH=zork Change-Id: Ief8a05b0a360563d26a81941720b78014feb0d25 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42786 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-303rdparty/blobs: advance submodule pointerFelix Held
This pulls in the following changes: * soc/intel/baytrail/microcode.bin: Remove outdated microcode * mainboard/amd/mandolin: add Cereme APCB Change-Id: If6dd7881b346782635dec07710fe5c4449254e3c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45851 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30mb/amd/mandolin: change EFS SPI mode from 1-4-4 to 1-1-4Felix Held
With this change the flash addresses will only get transferred over one data pin like in the non-quad SPI mode and only the data will get sent over all four data pins. Since this gives the flash chip a bit more time to fetch the data the host requested, this allows higher SPI frequencies resulting in a higher throughput when bigger chunks of memory get read. BRANCH=zork Change-Id: Iad4c922ffcdba4b17e6e81244ff37302eb171d97 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45831 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30mb/amd/mandolin: add missing SPI configuration to devicetreeFelix Held
This fixes the board not booting reliably when running from flash without the EM100 option selected during build time. Selecting EM100 mode overrides the settings, so when testing with an EM100 I didn't run into this issue. BUG=b:169644059 BRANCH=zork Change-Id: I2c7043c174dcf4501776a03b7689d8a20c214afb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45830 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30soc/amd/picasso: Add fields for the PSP to the transfer structMartin Roth
The PSP will be adding information into these fields after verstage runs. This allows data to be passed directly to coreboot very early in the boot process. BUG=b:168895748 TEST=None Branch=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Idbd1dfece59e99f6f15dfd8d002529ea6417cdbe Reviewed-on: https://review.coreboot.org/c/coreboot/+/45803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-30mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDurJamie Ryu
This patch updates the SLP_Sx assertion widths and power cycle duration for volteer. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159108661 TEST=Verified that the power cycle duration is 1~2s with a global reset on volteer. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-09-30security/intel/stm: Fix size_t printf format errorEugene D Myers
Size_t seems to have a compiler dependency. When building on the Purism librem 15v4, size_t is 'unsigned long'. In this instance, the compiler is the coreboot configured cross-compiler. In another instance, size_t is defined as 'unsigned short'. To get around the formatting conflict caused by this, The variable of type size_t was cast as 'unsigned int' in the format. Change-Id: Id51730c883d8fb9e87183121deb49f5fdda0114e Signed-off-by: Eugene D Myers <cedarhouse@comcast.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-09-303rdparty: Add STM as a submoduleEugene D Myers
The patch incorporates the STM build as a part of the coreboot build. A separate patch lists and documents the options that the developer can use. In most cases the default options will suffice. Change-Id: I8c6e0c85edd4e2b0658791553bd9947656e8c796 Signed-off-by: Eugene D Myers <cedarhouse@comcast.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-09-30libpayload: use PRIu64 type to print u64Jeremy Compostella
The appropriate way to print a u64 variable regardless of the current architecture is to use the PRI*64 macros. libpayload is mostly used in 32 bits but when ported to other projects and compiled in 64 bits it breaks the compilation. Change-Id: I479fd701f992701584d77d43c5cd5910f5ab7633 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-09-30soc/intel/tigerlake: Set TME upd param based on configPratik Prajapati
Set TmeEnable FSP-M upd based on config. TEST: TME ENABLE and LOCK bits get set when Tme is enabled. Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ia804c88057e17844f055fd852fc0b36cfe316432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-30mb/51nb/x210/gpio: Remove comments that contain pad functionsMaxim Polyakov
Remove these comments, because they do not contain useful information that helps to understand the circuit, which we do not have. Change-Id: I8a994a6f27d830bd05819043336d12c2ecef2f48 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45371 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-30mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFGMaxim Polyakov
Converts bit fields macros to target PAD_CFG_*() macros. To do this, the following command was used: ./intelp2m -n -t 1 -file ../../src/mainboard/51nb/x210/gpio.h This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m": CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical. Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 15:29:41 +0000