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AgeCommit message (Expand)Author
2018-11-12mb/google/octopus/var/bobba: Configure EC_SYNC IRQ as level-triggeredFurquan Shaikh
2018-11-12util/intelvbttool: Cleanup and fixesPatrick Rudolph
2018-11-12mb/emulation/qemu-i440fx|q35: Switch to C_ENVIRONMENT_BOOTBLOCKPatrick Rudolph
2018-11-12mb/emulation/qemu-i440fx|q35: Get rid of unused headersPatrick Rudolph
2018-11-12mb/*/*: Harmonise FD and devicetree on boards featuring ICH7Arthur Heymans
2018-11-12intel/i945: Factor out ram init time stampsPaul Menzel
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-11-12mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file"Elyes HAOUAS
2018-11-12siemens/mc_apl4: Enable SDCARDMario Scheithauer
2018-11-12siemens/mc_apl4: Remove external RTC from I2C0Mario Scheithauer
2018-11-12siemens/mc_apl4: Enable all PCIe root portsMario Scheithauer
2018-11-12siemens/mc_apl4: Remove reduced clock rate for I2C0Mario Scheithauer
2018-11-12siemens/mc_apl4: Disable CLKREQ of PCIe root portsMario Scheithauer
2018-11-12siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer
2018-11-12siemens/mc_apl3: Set Full Reset Bit into Reset Control RegisterMario Scheithauer
2018-11-12siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer
2018-11-12siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer
2018-11-12siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer
2018-11-12mb/google/octopus/variants/fleex: Set up tcc offset for fleexJohn Su
2018-11-12ec/google/chromeec: Configure EC_SYNC_IRQ as level triggeredFurquan Shaikh
2018-11-11mb/emulation/qemu-i440fx|q35: Link memory.cPatrick Rudolph
2018-11-10mb/lenovo/t400: Improve docking codePatrick Rudolph
2018-11-09soc/intel/apollolake: Disable HECI1 before jumping to OSFurquan Shaikh
2018-11-09arch/x86: Fix car_active for CONFIG_NO_CAR_GLOBAL_MIGRATIONFurquan Shaikh
2018-11-09drivers/*/tpm: Add postcar targetPhilipp Deppenwiese
2018-11-09include/program_loading: Add POSTCAR prog typePhilipp Deppenwiese
2018-11-09intel/i945: add timestamps in romstagePatrick Georgi
2018-11-09mb/google/kahlee/variants/liara: Decrease eDP adjust time to 20 msChris Wang
2018-11-09mb/google/kahlee: Tune eDP panel initialization timeChris Wang
2018-11-09mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT ge...Subrata Banik
2018-11-08mb/google/sarien: Set runtime IRQs to reset on PLTRSTDuncan Laurie
2018-11-08mb/google/sarien: Disable eSPI when ACPI is enabledDuncan Laurie
2018-11-08soc/intel/common: Add option to disable eSPI SMI at runtimeDuncan Laurie
2018-11-08mediatek/mt8183: Add DDR driver of write leveling partHuayang Duan
2018-11-08mediatek/mt8183: Add DDR driver of cmd bus training partHuayang Duan
2018-11-08mediatek/mt8183: Add DDR driver of pre-calibration partHuayang Duan
2018-11-08security/vboot: Add selection for firmware slots used by VBOOTPhilipp Deppenwiese
2018-11-08nb/amd/amdmct/mct_ddr3: Replace MTRR addresses with macrosElyes HAOUAS
2018-11-08src: Replace common MSR addresses with macrosElyes HAOUAS
2018-11-08nb/intel/gm45: Use macro instead of magic numberElyes HAOUAS
2018-11-08soc/intel/skylake: Add PCH sku id's supported for KBLPraveen hodagatta pranesh
2018-11-08mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRSTNick Vaccaro
2018-11-08mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11Nick Vaccaro
2018-11-08mb/google/octopus/variants/baseboard: Improve cold boot and S3 resumeJohn Zhao
2018-11-08soc/intel/apollolake: Improve cold boot and S3 resumeJohn Zhao
2018-11-08mb/google/poppy/variants/nami: add the hynix memory partsRen Kuo
2018-11-08src/mb/pcengines/apu2/romstage.c: Allow coreboot console output on COM2Michał Żygowski
2018-11-08drivers/spi: Return error in failure casePatrick Rudolph
2018-11-08security/vboot: Add VB2_LIB to postcar stage if availableWerner Zeh
2018-11-08toolchain: Add POSTCAR as a stage we have a toolchain forPatrick Georgi
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