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2008-05-14Check the JEDEC vendor ID for correct parity. Flash chips which can beCarl-Daniel Hailfinger
detected by JEDEC probe routines all have vendor IDs with correct parity. Use a parity check as additional hint whether a vendor ID makes sense. Note: Device IDs have no parity requirements whatsoever. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Example on how to add other chipsets to inteltool. ICH/ICH0, ICH4(-M) and ICH7Stefan Reinauer
have different register meanings, so they get their own lookup tables. This is a trivial patch. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-14Add lots of ATMEL SPI flash chips to flash.h.Carl-Daniel Hailfinger
Add a few flashchips already mentioned in flash.h to flashchips.c Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13flashrom: Move all IT87xx specific SPI routines from spi.c to a separateCarl-Daniel Hailfinger
file it87spi.c. No behavioural changes, but greatly improved SPI abstraction. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13Add new revised inteltool that dumps all kinds of chipset information and ↵Stefan Reinauer
drop old gpio_dump utility. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13This is a trivial patch which fixes the tint build by removing the extraMyles Watson
typedef for time_t. The other half bumps the tint patch revision in buildrom to take advantage of it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13flashrom: Move the SPI #defines from spi.c to spi.hCarl-Daniel Hailfinger
This patch has no code changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-13Change the SPI parts of flashrom to prepare for a merge ofCarl-Daniel Hailfinger
ICH9 SPI support. In theory, this patch has no behaviour changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12MX25L3205 and W25x40 have been confirmed to probe/read/erase/write OKCarl-Daniel Hailfinger
by Harald Gutmann. SST39VF040 has been confirmed to probe OK by misi e. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-12Add SST39VF512, SST39VF010, SST39VF040 support to flashrom. The SST39LFCarl-Daniel Hailfinger
series has the same IDs. Add short AMIC vendor ID to flashrom. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-11Fix the build when serial console support is disabled (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3298 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-11Quickfix to repair 'make clean; make menuconfig' (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3297 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10Improve flashrom SPI abstraction, second step.Carl-Daniel Hailfinger
This paves the way to have a fully generic generic_spi_command without knowledge about any SPI controller. The third step would be calling SPI controller functions via a function pointer. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-10flashrom: Rename generic_spi_*() functions to spi_*()Peter Stuge
This is a very early step toward cleaning up SPI code in flashrom. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-09coreboot-v2: Disable second serial port on NorwichJordan Crouse
There isn't really any good reason to have the second serial port enabled on Norwich, and this makes the X DDC code stop working. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08Add support for dumping ITE IT8718F EC registers (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08Don't split up register list in two blocks, otherwise "Register dump:"Uwe Hermann
will be printed twice in the output (trivial). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-08flashrom: Probe for up to 3 flash chips.Claus Gindhart
Currently there is an ongoing technology migration from LPC/FWH to SPI chips. For this reason some boards have multiple chips of different technologies onboard. This patch makes flashrom probe for up to 3 chips and if more than one chip is found flashrom exits, asking the user to specify -c. [root@localhost src]# ./flashrom ... Multiple flash chips were detected: SST49LF008A M25P16@ICH9 Please specify which chip to use with the -c <chipname> option. [root@localhost src]# Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Claus Gindhart <claus.gindhart@kontron.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07Implement GPIO configuration routines for the Intel 3100 southbridge,Ed Swierk
allowing you to specify per-mainboard GPIO settings. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3290 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07coreinfo: Add a module for browsing the boot LARJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07libpayload: Add LAR walking supportJordan Crouse
Add suport for walking LARs. These try to emulate the f* functions from POSIX, though they are obviously different in their behavior. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-07Fix a typo in lbtdump output (trivial).Ed Swierk
Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ed Swierk <eswierk@arastra.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06coreinfo: Show the current time and date in the menuJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06We were in the risk of running out of space in the option menu atJordan Crouse
the bottom of the screen - this turns the function keys into categories and then list specific items as part of the category. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3285 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06The previous commit had more in it then I wanted - so I am revertingJordan Crouse
this and re-commiting so that the history and comments are correct. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3284 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06coreinfo: Move the rdtsc.h include into the #ifdef CONFIG_MODULE_CPUINFOJordan Crouse
rdtsc.h shouldn't be included unless we really need it (and use it). Trivial. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3283 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06cs5536 IDE PWB flag was not getting set since it is 1<<14 and it was only ↵Marc Jones
doing a pci_write_config8. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06This patch changes Config-lab.lb for qemu to use lzma like the other targets.Myles Watson
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06This patch adds pc keyboard init function call for qemu in v2 since some ↵Aaron Lwe
payloads assume Coreboot initializes it. Coreboot v3 already does it. Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3280 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-06Fix various issues on MSI MS-7135 board.Jonathan A. Kollasch
- W83627THF is strapped to 0x4e, not 0x2e - there's no device 9 on PCI-E x1 bus, it should be device 0 - add mptable entries for AGR slot, based on info in user manual - enable floppy drive controller so that some legacy VGA ROMs will work Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-05This patch changes the payload path for Config.lb; this board is supported byWard Vandewege
buildrom and this bit was forgotten during r3092. This is a trivial patch. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-03flashrom: Add a tested bitmap field to the flash chip table.Peter Stuge
Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE. 8 bits out of 32 are in use now. No bits set means nothing has been tested. For chips with at least one operation that is not tested or not working, the user is asked to email a report to a special email adress so that the table can be updated. All chips are TEST_UNTESTED for now. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-30By default, the Intel 3100 LPC interface enables only I/O range 0x3f8Ed Swierk
for both serial ports, making it challenging to use COM2 for the early console. Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-29flashrom: Enable ROM decode range to 1MB for vt8237rBari Ari
Signed-off-by: Bari Ari <bari@onelabs.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28The generic jedec.c does not work for the ST M50FLW flashClaus Gindhart
devices, because they need an unlock command first. For this reason, ST M50FLW support is moved to a new HW support module, because any change in jedec.c would bear the risk to cause problems with the already supported devices. It's already tested with ST M50FLW080A; the other chips of this family i dont have available, so i couldnt test it. Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-28flashrom: Handle NULL probe, erase and write function pointers in thePeter Stuge
flashchips table. The read pointer was already checked properly. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25libpayload: Add gettimeofday() and friendsJordan Crouse
Add a gettimeofday() implementation - it works pretty well, but it drifts a little bit so its not very suitable for keeping time. It works best to track changes in time over small periods of time. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3272 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25libpayload: Fix a small but aggressive bug in printf()Jordan Crouse
This was causing the returned counter value to be one more then it should be when printing a single character. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25libpayload: Enable keyboard translation so that we can use scancode set 1Jordan Crouse
The qemu keyboard controller defaults to using scancode set 2, we use set 1. Turn on the translate mode in the keyboard controller to force the issue. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3270 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25libpayload: Fix malloc allocationJordan Crouse
Apparently the previous version worked on luck. Fix the allocation and add parens to better guide the compiler. Also, halt() if the heap is poisoned (like by an overrun). Finally, fix calloc() so that it actually works. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25libpayload: Add the null terminator to the end of the duplicated stringJordan Crouse
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25Change abuild ROM_IMAGE_SIZE to match the standard s_c_fam10 Config.lb.Marc Jones
The FAM10 code takes up more space in the uncompressed "ROMCC" portion of coreboot. Also, It is still growing as features are added. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25Remove inline from FAM10 CPU initialization functions.Marc Jones
This doesn't save any space for me but it is the right thing to allow GCC to optimize. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25Fix so pci device memory allocation does not use memory base address at ↵Aaron Lwe
0xfec00000, this is reserved for APIC. Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-25Payload location fix for buildrom (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24Add CPUID processor name string support for Fam10 CPUs.Marc Jones
Peter did a nice job cleaning up my initial patch. Thanks! Signed-off-by: Marc Jones <marc.jones@amd.com> Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24On APs the ClLinesToNbDis was being left enabled from CAR setup.Marc Jones
Disabling it should help performance. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24This board (http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX)Nikolay Petukhov
is based on amd-lx800/cs5536. Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-24Flash pages, which where excluded from updating using the exclude or theClaus Gindhart
layout option, as well as areas, whose flash contents already contain the desired data, will be skipped. These ensures absolute data security of critical areas (BIOS boot block), e.g. against a sudden power off or a CPU hangup during flashing. As a nice side effect, it speeds up the flash process, if the BIOS to be flashed is very similar to the version in flash. Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-04-23Same old story: Fam10 needs more space again. My calculations say itCarl-Daniel Hailfinger
needs 172 more bytes, give it 512 and hope that's enough for a while. Trivial. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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