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2021-04-26soc/intel/elkhartlake: Update GPIO communitiesTan, Lean Sheng
GPIOs are divided into different communities. Each community consists of one or more GPIO groups. We need to configure the groups in coreboot so that they are mapped properly. GPIO communities should be properly configured in GPIO_CFG and MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured in GPIO_CFG register while the PMC_GPP_* in pmc.h. GPIO communities in coreboot should match with the kernel gpio communities also. Kernel reads the ASL file from coreboot. This patch adds the proper community mapping in ASL code to match with kernel code. In gpio_soc_defs.c file we are indexing the groups correctly. In gpio.h file we define all the gpio devices as kernel populates sysfs with separate gpio device for each community. This patch is created based on Intel EHL PCH Datasheet with Document number 614109 and Chapter 21. Also update GPIO COM3 Port ID and 2 GPIO register values (HOSTSW_OWN_REG_0 & PAD_CFG_BASE) respectively. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ifc609b3d6ab9ea2b807dc0f178ec99f95d2db4cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/48555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-04-26mb/google/mancomb: Add mancomb APCBs into buildIvy Jian
This adds the Mancomb APCBs into the AMD firmware binary. BUG=b:182211161 TEST=Build and check log showing APCB sources present. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ifdf1e813fce6f93378c2495cf76bdace81d87c16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52600 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26src/soc/amd/picasso: Add HDMI 2.0 disable settingPatrick Huang
hdmi2_disable bit0~3 is used to disable HDMI 2.0 function in DDI0~3 BUG=b:179170193 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: I383bfd04e01f5202db093105662344869e475746 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-04-26src/vendorcode/amd/fsp/picasso: Add HDMI 2.0 Disable setting section of ↵Patrick Huang
FspmUpd.h This change adds HDMI 2.0 Disable setting BUG=b:179170193 BRANCH=none TEST=Build; Verify the UPD was passed to system integrated table Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Change-Id: Ie00389074f3718a23440c41ae0b116455aa8b603 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2021-04-26mb/google/mancomb: PCIe GPIOs - enable enables, disable resetsIvy Jian
To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I5e3e9fe21f44b832e26b0942759ae2ec96ec6c82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-26mb/google/volteer/variant/lindar: Create dynamic fan table mechanismKevin Chang
Add dynamic fan table mechanism for Lindar and Lillipup. Create different fan tables that provided from thermal team. BUG=b:185308432 TEST=Build FW and boot to OS modify CBI test with DPTF tool. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I1b79dbe1ae6ee7aa41cef832b4ee305cc8f4b753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-26mb/google/guybrush: Enable S0i3Karthikeyan Ramasubramanian
BUG=b:185939089 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-26soc/amd/cezanne/fsp_m_params: Configure the s0i3_enable UPDKarthikeyan Ramasubramanian
Configure the S0i3 enable UPD based on the mainboard configuration. BUG=b:178728116 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I18f43e964d1c70317155394257a5e2c1900816bb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-26vc/amd/fsp/cezanne:Add s0i_enable upd controlJason Glenesk
Add upd to enable S0i3 in fsp. BUG=b:178728116 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Cq-Depend: chrome-internal:3777391 Change-Id: I01759caa4d72e284b2b960634f89c6a2ab1dad57 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26mb/google/brya: Enable GL9755 SD card readerEric Lai
Enable GL9755 SD card reader. BUG=b:185397257 TEST=SD card is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-26soc/intel/alderlake: Use device ID from pci_devs header fileJohn Zhao
This change applies device ID from the SoC pci_devs.h directly. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ic5d2910ca53c02527aef0ad33ed52a35f2bdf7af Reviewed-on: https://review.coreboot.org/c/coreboot/+/52640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26soc/intel/alderlake: Fix devices list in the DMAR DRHD structureJohn Zhao
The VT-d specification states that device scope for remapping hardware unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list of hardware unit definition structure. This change fixes the devices list in the DMAR DRHD structure. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I14c34ad66a5ee8c30acabd8fe5a05c22087f9120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/intel/tigerlake: Use device ID from pci_devs header fileJohn Zhao
This change applies device ID from the SoC pci_devs.h directly. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0c3bd60c62664337429e6817d2cf54cf2e8d500b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26soc/amd/cezanne,picasso/Kconfig: add help text for MAX_CPUSFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: I76270b43b3202bda71ff3f6b97d5ffa2234511b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52646 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26sb/intel/lynxpoint: Add and use power state bit macrosAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf remains identical. Change-Id: Id85b76c0aaf481f99f55a9ce6d813ff32753e588 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-26soc/mediatek/mt8195: Add GPIO driverPo Xu
Signed-off-by: Po Xu <jg_poxu@mediatek.corp-partner.google.com> Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/mediatek/mt8195: Add timer supportYidi Lin
TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/mediatek/mt8192: Remove redundant SPM register definitionYidi Lin
A complete SPM register definition is defined in include/soc/spm.h. Remove the redundant definition from include/soc/pmif_spmi.h. TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: If55e7adabdf32bb4312b910dce9a55621a8da380 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26soc/mediatek/mt8195: add register definitionsYidi Lin
Add register definitions for infracfg_ao, topckgen, apmixed and SPM. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie740f22aa12f40950a27a3e0142e2d50a506b251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/mediatek/mt8195: Initialize watchdogYidi Lin
MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-04-26soc/amd/cezanne & picasso: Add Kconfig for hardcoded Soft Fuse bitsMartin Roth
Currently, some of the PSP Soft Fuse bits are hardcoded in the Cezanne and Picasso makefiles. This makes it impossible for platforms to change them. This change puts the hardcoded bits in Kconfig, allowing them to be modified by the platform. BUG=b:185514903 TEST=Verify that the correct Soft Fuse bits are set. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I190ebf47cb7ae46983733dc6541776bf19a2382f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52422 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-25Revert "nb/intel/ironlake: Handle broken ME firmware"Nico Huber
This reverts commit 4447996cc582d2c8745802b84b1f5a635e33a22a. It looks like the patch repurposed the `memory_reserved_for_heci_mb` variable as an indicator if the ME firmware is fine. The change to setup_heci_uma() made it bail out early, even though the implementation is obviously prepared to set things up even if the requested UMA size is 0. This also leaves the code in an inconsistent state: The second if's condition is always true. Resolves: https://ticket.coreboot.org/issues/305 Change-Id: Ie5a98be3f660078a85a79b5551e86f90f148974f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52426 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Stefan Ott <coreboot@desire.ch> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-25drivers/pc80/rtc: Factor out CMOS entry lookupAngel Pons
The procedure is identical for reads and writes. Factor it out. Change-Id: I22b1d334270881734b34312f1fee01aa110a6db4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52636 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-24mb/kontron/mal10/cmos.layout: Drop unused optionsAngel Pons
The `ethernet1` and `ethernet2` options are not used in this board. Change-Id: I24c8f662d094fb77ed1425ec13486ffa9c3dff07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52631 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-24mb/kontron/mal10/cmos.layout: Align contents with tabsAngel Pons
Replace spaces with tabs for consistency with other mainboards. Change-Id: I47440eeecf5f2cb2dbdd45b63fe753ffc7d27bd2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2021-04-24mb/clevo/cml-u/cmos.layout: Align contents with tabsAngel Pons
Replace spaces with tabs for consistency with other mainboards. Change-Id: Ia4042ecf7c62490b0a50bc42d5ddddd5872bf036 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52633 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-24mb/asus/p2b/cmos.layout: Align contents with tabsAngel Pons
Replace spaces with tabs for consistency with other mainboards. Change-Id: Ib0d5bf566148cc4890d5ba010314d11b7a4f8c2b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52634 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-24Coachz: Observe SPI_CLK voltage level is only 1.4V, need to adjustyolkshih
the signal integrity strength to correct voltage level 1.8V BUG=b:184714790 BRANCH=trogdor TEST=HW test Change-Id: Iee7b458b6aa7d701724da87ecdf0f993d0565c0c Signed-off-by: yolkshih <yolkshih@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wenchao Han <hanwenchao@huaqin.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-04-23soc/amd/picasso/mca: fix CTL_MASK MSR accessFelix Held
MC0_CTL_MASK is no longer available in fam 17h and newer and will result in a general protection fault when accessed. This register was moved, so use the one that is correct for this CPU generation. BUG=b:186038401 TEST=Mandolin no longer crashes in the machine check error handling path with a general protection fault. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibb042635d917dfcb2121849e2913aa62eca09dd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23soc/amd/common/block/include/amdblocks: add msr_zen.hFelix Held
Add defines for the Machine Check Architecture Extensions (MCAX) MSRs and the new MCA_CTL_MASK MSRs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id78483e7df00c3e99c698c0344f38be68d1dfb72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23amd/common/blocks: Print eSPI peripheral channelRaul E Rangel
BUG=none TEST=Boot guybrush with ESPI_DEBUG Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4312aaedcfed1535ef00a4686f218d30e351b33f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52226 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23lib/espi_debug: Add espi_show_slave_peripheral_channel_configurationRaul E Rangel
Prints out the following: eSPI Slave Peripheral configuration: Peripheral Channel Maximum Read Request Size: 64 bytes Peripheral Channel Maximum Payload Size Selected: 64 bytes Peripheral Channel Maximum Payload Size Supported: 64 bytes Bus master: disabled Peripheral Channel: ready Peripheral Channel: enabled BUG=none TEST=boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7d598ee4f0f9d8ec0b37767e6a5a70288be2cb86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-23mb/google/dedede/var/storo: Modify eeprom setting for MIPI cameraTao Xia
Currently, it fails to dump the nvme data by test command. It reports the following error: cat: '/sys/bus/i2c/devices/i2c-PRP0001:01/eeprom': Connection timed out So increase the value from 0x0400 to 0x2000 and double the address width from 0x08 to 0x10 to solve this problem. BUG=b:177393430 TEST=1. cat /sys/bus/i2c/devices/i2c-PRP0001:01/eeprom > /tmp/ov8856_eeprom.bin 2. hexdump -C /tmp/ov8856_eeprom.bin > ov8856_eeprom_dump.log 3. cat ov8856_eeprom_dump.log Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ia933927981f07e0f7954a4bc6d82f0bdd70181f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52048 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: ShawnX Tu <shawnx.tu@intel.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/picasso/cpu: make one line comment use only one lineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I264e44132a6a9df6f548c9856c2256d1b92916c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52612 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/picasso/cpu: make sure that MAX_CPUS isn't overriddenFelix Held
Trying to limit the number of available cores by setting the MAX_CPUS Kconfig option to a lower value than the SoC's default might result in cores being enabled in the FSP-S, but not fully initialized in coreboot which will cause some malfunction. Add a static assert to make sure that this option isn't changed from the default. To limit the maximum number of cores, use the downcore_mode and disable_smt devicetree settings instead. TEST=Build fails if MAX_CPUS isn't the expected default. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3cfe09f8bb89a2154d37a37398df982828c824f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52611 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/cezanne/cpu: make sure that MAX_CPUS isn't overriddenFelix Held
Trying to limit the number of available cores by setting the MAX_CPUS Kconfig option to a lower value than the SoC's default might result in cores being enabled in the FSP-S, but not fully initialized in coreboot which will cause some malfunction. Add a static assert to make sure that this option isn't changed from the default. To limit the maximum number of cores, use the downcore_mode and disable_smt devicetree settings instead. BUG=b:184162768 TEST=Build fails if MAX_CPUS isn't the expected default. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idd6aa1d99128b17218a8e910c33415218a58578f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52606 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/picasso: clean up Kconfig and headerKangheui Won
Clean up Kconfig and psp_trasfer.h files before copying over to cezanne. TEST=build, flash and boot on jelboz360 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ib370d93e23c15a2fe4c46051ed3647d2d067bb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52563 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/amd/cezanne: fix i2c compiler errors on non-x86Kangheui Won
if ENV_X86 is not true we had several compile errors in i2c code. Fix them before we add code for psp_verstage which is non-x86. BUG=b:182477057 BRANCH=none TEST=build Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I0796671dd34ab2d0f123c904a88c57cdad116a57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-23amd/vboot: remove bl_syscall_public.h from includeKangheui Won
bl_syscall_public.h is a header file for PSP app, but was used for x86 code to get the definition of PSP_INFO. Move the definition into psp_transfer.h and do not include bl_syscall_public.h from x86 code. BUG=none TEST=build psp_verstage on zork BRANCH=none Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I0fe011652a47d0ba2939dc31ee3b83f0718a61dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/52537 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23payloads/depthcharge: Use static_fw_config.h file for depthcharge buildBora Guvendik
Use static_fw_config.h during depthcharge build to be in line with latest depthcharge changes on the main branch. https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/2523517 BUG=none TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I72a681d9321750c392000e11a21d81020dde3fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
2021-04-23mb/google/guybrush: Update memory configurationMartin Roth
The next guybrush build uses 2 new LPDDR4X memory chips: - Micro MT53E1G32D2NP-046 WT:B - Hynix H9HCNNNBKMMLXR-NEE The MT53E2G32D4NQ-046 WT:A chip has been added to the global LPDDR4X list since the last time guybrush was updated, so that's brought into the guybrush SPD directory as lp4x-spd-10.hex, but it's not used. BUG=b:186027256 TEST=Build only Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia5efd548f8b9442fb3703518387175aba8933a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-23util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 configMartin Roth
The revision B version of the MT53E1G32D2NP-046 memory chip will be used in the next guybrush build. It has a different internal layout than the Revision A part, with 2 ZQ lines per module instead of 1. BUG=b:186027256 TEST=Build only Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I066f40eb890648a9be17cfe0cee20d299000c11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-23mb/google/octopus/var/fleex: Add ssfc codec cs42l42 supportEric Lai
Add cs42l42 codec support in fleex. BUG=b:184103445 TEST=boot to check cs42l42 is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-23drivers/i2c/cs42l42: Add driver for generating device in SSDTVitaly Rodionov
This driver uses the ACPI Device Property interface to generate the required parameters into the _DSD table format expected by the kernel This was tested on the octopus/variants/fleex ainboard to ensure that the SSDT contained the equivalent parameters that are provided by the current DSDT object Signed-off-by: Vitaly Rodionov <vitaly.rodionov@cirrus.corp-partner.google.com> Change-Id: I7c3145b20a1ba743d91eb64b93cb001db3854c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-23soc/intel/xeon_sp/cpx: Add UPI locksMarc Jones
Add UPI locks as indicated by the Intel docs. Change-Id: I9d1336e57f1776f3024883d6edcf0a855b1382c6 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23soc/intel/xeon_sp/cpx: Add IMC locksMarc Jones
Add IMC locks as indicated by the Intel docs. Change-Id: Id5c43711e80f4e2112c305a9b48d0a4c8509e89b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23mb/system76/oryp5: Leave NC GPIOs unterminatedTim Crawford
Remove the unneeded pull up, as leaving them unterminated disconnects them from internal logic. Also replace use of PAD_CFG_TERM_GPO with PAD_CFG_GPO where no termination is used. Change-Id: Ia85ea39d46d7d9584b94726a7d601ca06826b1d1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23mb/intel/shadowmountain: Enable HECI1 interfaceSridhar Siricilla
The patch enables HECI1 interface Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia2638559bcaac78d024e35abd09534b61eacb843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-04-23mb/intel/shadowmountain: Enable RTD3 for SD cardRizwan Qureshi
Enable the PCIe RTD3 driver for the PCIe attached SD card interface and specify the srcclk pin and reset GPIO. TEST=Tested on shadowmountain platform to ensure the system can enter the S0ix state and suspend/resume is stable Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52134 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23soc/intel/jasperlake: Remove TCSS setting from the DMAR tableJohn Zhao
The Jasperlake does not support TCSS. This change removes the TCSS setting from the DMAR table. BUG=None TEST=Built image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I573e2038fd76ac66af88125117774b40cc80c704 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52575 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-08 21:28:50 +0000