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2021-05-08trogdor: Add backlight support for sn65dsi86bridge for HomestarVinod Polimera
Add backlight support in sn65dsi86bridge through the AUX channel using eDP DPCD registers, which is needed on the GOOGLE_HOMESTAR board. Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52663 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08drivers/sn65dsi86: Switch EDID reading to use "indirect mode"Julius Werner
The SN65DSI86 eDP bridge supports two ways to read the EDID: for now we've been using "direct mode", which works by basically making the bridge I2C device listen to another chip address besides its own and proxy all requests received there directly to the eDP AUX channel. The great part about that mode is that it is super easy and hassle-free to use. The not so great part about it is that it doesn't work: for EDID extensions, the last byte (which happens to contain the checksum) is somehow always read as zero. We presume this is a hardware bug in the bridge part. The other, much more annoying way is "indirect mode", where each byte transmitted over the AUX channel has to be manually set up in the I2C registers of the bridge, just like we're already doing with DPCD transactions. Thankfully, we can reuse most of the DPCD code for this so it's not a lot of extra code. It's a bit slower but not as much as you'd expect (26ms instead of 18ms on my board), and the difference is not very relevant compared to common total times for display init. Also, some of the (previously unused) enum definitions for the AUX_CMD mode field of the bridge had just been plain wrong for some reason, and needed to be fixed to make this work. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I65f80193380d3c3841f9f5c26897ed672f45e15a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52959 Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07soc/amd/common/acpi/pci_int.asl: Allow IRQ sharingRaul E Rangel
PCI interrupts are level active low, so they can be shared. BUG=b:184766519 TEST=Boot guybrush to OS with `pci=nomsi amd_iommu=off noapic` Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I439337dd66fe56790406c6d603e73512c806a19d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52957 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07skylake mainboards: Use enum values for SaGvAngel Pons
Replace `3` with `SaGv_Enabled`, which has the same value. Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-07skylake DT/HALO mainboards: Drop `SaGv` settingAngel Pons
SaGv is only supported on ULT/ULX hardware. Change-Id: I25001e97cce3193629e7fa7573bf9b352362d59b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-07aopen/dxplplusu: Fix IOAPIC in ASLKyösti Mälkki
Change-Id: I8a2abe2cf20952491d181766a3ca492de355fc88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-07nb/intel/e7505: Fix for RESOURCE_ALLOCATOR_V4Kyösti Mälkki
Memory region 0xa0000 to 0xc0000 was not reserved, the first PCI memory resources might get assigned in this space. FIXES: aopen/dxplplusu PCI EHCI 0:1d.7 memory resource. Change-Id: Ia17025bde83b91d71ad719de6348197cf92e267e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-07soc/amd/common: Add Kconfig/Makefile support for common/fsp/*Raul E Rangel
This will allow us to have subdirectories in common/fsp. BUG=b:184766519 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib3497791e1963867c8fe06a42c111e5d0503ade1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-07mb/google/volteer: Create volet variantSheng-Liang Pan
Create the volet variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:186334008 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOLET Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-07mb/pcengines/apu1: Disable memory bank interleavingMichał Żygowski
Bank interleaving does not work on this platform, disable it. AmdInitPost returns success thanks to this setting. TEST=boot apu1 and see AGESA_SUCCESS after AmdInitPost Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/52779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-07mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happyMichał Żygowski
Bank interleaving does not work on this platform, disable it. Additionally enable ECC feature on SKUs supporting it. AmdIntPost returns success thanks to these settings. TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after AmdInitPost Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I010645f53b404341895d0545855905e81c89165e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-07soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cacheYidi Lin
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52925 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07mb/google/cherry: configure GPIOsYu-Ping Wu
Configure Chromebook specific GPIOs, including EC_AP_INT, SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK. Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52924 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIOMaulik V Vaghela
We need to configure CPU PCIE root port related gpios in early boot block stage for CPU root ports to work. Since we're removing this programming from FSP, coreboot needs to take care of programming this GPIOs. Also we need to enable virtual wire messaging for native gpios for CPU PCIE root ports. Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270 Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-07mb/google/volteer/var/elemi: Add spd for K4AAG165WB-BCWEWisley Chen
Add SPD support to elemi for K4AAG165WB-BCWE BUG=b:187379245 TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-wqbootimage Change-Id: I839447a9e7c7b6558b2d0877c67dc9cf89ee792a Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-05-07sb/intel/common/pmclib: Use pmbase functionsArthur Heymans
Change-Id: Ic0be2c1ffaadcc6212c548332d60d40b405abbda Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-07sb/intel/common: Fix platform_is_resuming()Arthur Heymans
platform_is_resuming() was using the wrong register (PM1_STS) to figure out if the platform was resuming (PM1_CNT). Change-Id: I1f69dca1da158aae15c6da6d4c898c71d9cdb51f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-07sb/intel/common: Implement acpi_is_wakeup_s3()Arthur Heymans
acpi_is_wakeup_s3() requires acpi_get_sleep_type(). Change-Id: Ibe01863e685bcbc9652a72be0632cfbd83e18380 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-07soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen
On tgl, we noticed system hang if a shutdown is triggered before fsps. The dut is unable to shutdown properly due to tcss is stuck before tcss_init in fsps. This change enable power button smi on jsl, tgl, adl after fsps. it can also prevent a shutdown failure due to lack of fsps init on certain ip. BUG=b:186194102, b:186815114 TEST=Power on the system and pressing power button repeatedly doesn't cause the system hang during shutdown. Change-Id: I70b871f2676a89bc782116e02beba5c20ec51eef Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-07soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmasterKane Chen
If a power button SMI is triggered between where it is currently enabled and before FSP-S exits, when the SMI handler disables bus mastering for all devices, it inadvertently also disables the PMC's I/O decoding, so the register write to actually go into S5 does not succeed, and the system hangs. This can be solved by skipping the PMC when disabling bus mastering in the SMI handler, for which a callback, smihandler_soc_disable_busmaster is provided. BUG=b:186194102, b:186815114 TEST=Power on the system and pressing power button repeatedly doesn't cause the system hang during shutdown. Change-Id: I1cf5cf91ebad4a49df6679e01fc88ff60c81526c Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-07mb/google/mancomb: Update AMDFW config fileMartin Roth
Mancomb uses DDR4 SODIMMs, but the default cezanne configuration is for the LPDDR4 version. This changes to use SODIMMS. Further changes may be needed for platform customization, so I put the config file in variants/baseboard instead of the root mancomb directory. BUG=b:187094481 TEST=Build only Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06mb/google/mancomb: Implement tis_plat_irq_statusMartin Roth
This patch was implemented on Guybrush at CB:52352 BUG=b:185397933 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I141a504a827f37724fab0aaed7498fd543e471d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06mb/google/mancomb: Update Kconfig with needed optionsMartin Roth
DISABLE_KEYBOARD_RESET_PIN - This pin goes to a test point and is not used for the reset. DRIVERS_UART_ACPI - Add the UART ACPI code FW_CONFIG - Mancomb uses the firmware config interface PSP_DISABLE_POSTCODES - The PSP is not yet initializing eSPI correctly to send post codes to the EC, so disable them for now. BUG=None Test=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I39efcc8d1e0fb1e7ac0b0541a49db0ac0ee56481 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-06mb/google/mancomb: Fix EC SCI configurationMartin Roth
This change fixes two problems: 1) We had the enum values for .direction and .level swapped. The naming is very confusing... 2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low event that is only cleared by reading the eSPI status register 0x9C. Cezanne has added a new event source that directly exposes the SCI bit. This is the correct event source to use for EC SCI. This same patch was added for Guybrush at CB:52673 BUG=b:186045622, b:181139095 TEST=Build Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iac86d2ef5bdd21fbb0a0d4e235efe4fe621023b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52948 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06mb/google/mancomb: Switch eSPI ALERT# to in-bandRaul E Rangel
This matches what we are doing on guybrush. BUG=b:187122344, b:186135022 TEST=build Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id61de28cd0ee762693b287b29bdd7605d4176929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52956 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06mb/google/guybrush: Switch eSPI ALERT# to in-bandRaul E Rangel
Using the push-pull alert was causing leakages when in S0i3. This is because the EC drives ALERT#, so when the AP enters S0i3, the extra current leaks into the SoC and ends up turning on the power regulators. By using in-band ALERT#, the EC no longer drives this pin high, thus fixing the leak. We could also have used an open drain alert, but the rise time is less than ideal. BUG=b:187122344, b:186135022 TEST=Measure S0i3 power on guybrush and validate it's no longer high. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-06soc/amd/common/espi,mb/: Allow configuring open drain ALERT#Raul E Rangel
Some designs might wish to use an open drain eSPI ALERT#. This change adds an enum that allows setting the eSPI alert mode. BUG=b:187122344, b:186135022 TEST=Boot guybrush using all 3 alert modes Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/amd/common/espi: Don't set alert pin in espi_set_initial_configRaul E Rangel
The eSPI spec says that the Alert Mode defaults to in-band on reset. This change ensures the controller is in sync with the eSPI peripheral. The configured alert mode is configured in espi_set_general_configuration. BUG=b:187122344, b:186135022 TEST=Boot guybrush and make sure we don't get any eSPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib43e190d08d77ecfcd22ead2bf42e5de2202b555 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52953 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/common/espi: Print set eSPI peripheral configRaul E Rangel
This will print the config we are setting on the eSPI peripheral. e.g., Setting general configuration: slave: 0x98a00000 controller: 0xe2000000 eSPI Slave configuration: CRC checking enabled Dedicated Alert# used to signal alert event eSPI quad IO mode selected Only eSPI single IO mode supported Alert# pin is open-drain eSPI 33MHz selected eSPI up to 20MHz supported Maximum Wait state: 0 BUG=b:187122344, b:186135022 TEST=Boot guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1a2382d8ab3d3f0d14a139c57470cb895112eca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52952 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/{common/picasso}: Move pci_int.aslRaul E Rangel
We can share this with cezanne. BUG=b:184766519 TEST=Build picasso Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If746d55345f6b7c828376b64adc5532d20413f68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52916 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/amd/{picasso/common}: Move populate_pirq_data prototype to commonRaul E Rangel
This method signature will also be used by cezanne, so move it to common. BUG=b:184766519 TEST=Build picasso Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I421bdad51776278f83148174e6f72bdc38249e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-06vc/amd/fsp/cezanne: Add AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUIDRaul E Rangel
This HOB describes the PCI routing table. It will be consumed by coreboot to generate the _PRT ACPI object. BUG=b:184766519, b:184766197 TEST=Build guybrush Cq-Depend: chrome-internal:3794981 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db Reviewed-on: https://review.coreboot.org/c/coreboot/+/52869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-06emulation/qemu-x86: Select BOOT_DEVICE_NOT_SPI_FLASHArthur Heymans
SPI flash is not emulated on these boards. Change-Id: If29a87441cb26e53c9814ed10ddcfe14752c3965 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52791 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06drivers/pc80/rtc/option.c: Constrain API to integer valuesAngel Pons
None of the options accessed within coreboot is a string, and there are no guarantees that the code works as intended with them. Given that the current option API only supports integers for now, do not try to access options whose type is 's' (string). Change-Id: Ib67b126d972c6d55b77ea5ecfb862b4e9c766fe5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-06include/console: Align ramstage Boot State Machine postcodesSubrata Banik
This patch ensures all boot state machine postcodes are in right order. Move POST_ENTRY_RAMSTAGE macro definition after POST_BS_PAYLOAD_BOOT. Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06nb/amd/{agesa,pi}: Avoid overflows during DRAM calculationMichał Żygowski
Do not use get_dram_base_mask to calculate system DRAM limits. Shift operation around values operating on base and mask were causing overflows and thus incorrect system DRAM limit. Another function returning base and limit in KiB has been developed to avoid data loss. Keep DRAM high base and limit in calculations only for Trinity where the physical CPU address bits is 48. Although it is almost impossible to have a non-zero value there, the platform would have to support nearly 256GB of RAM. TEST=boot PC Engines apu1 2GB, apu2 4GB and apu3 2GB and boot Debian with Linux 4.14 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I3b5c1df96c308ff50c8de104e213219a98f25e10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-06mb/google/octopus: add audio codec into SSFC support for BloogTony Huang
BUG=b:186380809 BRANCH=octopus TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check whether device tree is updated correspondingly by disabling unselected one. Change-Id: I0975a8b64452c3f636e6c5937c6918518ec5b4e9 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-05-06mb/intel/adlrvp_m: Disable Type-C xDCIBernardo Perez Priego
Disabling this pci 0d.1 device since it is not required. TEST= Boot to OS. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iccdf38111e3961ba887829abfa4146a9b37df9be Reviewed-on: https://review.coreboot.org/c/coreboot/+/52744 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06arch/x86/walkcbfs.S: Use FMAP instead of "cbfs master header"Arthur Heymans
Tested on qemu/i440fx on X86_64: - Page tables are found in cbfs (finding a file works) - returns 0 when a file is not found - works when there is no cbfs file at the start of the FMAP, e.g. with the cbfs master header removed. Change-Id: Ibab657cc40cd5c09c3a73c54950b98ac45a98dbf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52879 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06arch/x86: Always include walkcbfs.SArthur Heymans
Let the linker decide if this code is needed. Change-Id: I26fb19d461db39ce554af7b948f0d10a12920299 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-06mb/amd/majolica: Enable S0i3 by defaultJason Glenesk
Set s0ix_enable to true. BUG=b:178728116 TEST=Cold boot and perform a cycle of S0i3. Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-06Revert "soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure"Arthur Heymans
This reverts commit 8122b3f6123158024ed2844af17289a9abb98036. This broke DMAR. DRHD defines the scope of the device entries below. Change-Id: Iac4858f774fa3811da43f7697a9392daba4b4fba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-05-06security/tpm: Add option to init TPM in bootblockArthur Heymans
When using a hardware assisted root of trust measurement, like Intel TXT/CBnT, the TPM init needs to happen inside the bootblock to form a proper chain of trust. Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51923 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak
TGL boards using the Type-C subsystem for USB Type-C ports without a retimer attached may require a DC bias on the aux lines for certain modes to work. This patch adds native coreboot support for programming the IOM to handle this DC bias via a simple devicetree setting. Previously a UPD was required to tell the FSP which GPIOs were used for the pullup and pulldown biases, but the API for this UPD was effectively undocumented. BUG=b:174116646 TEST=Verified on volteer2 that a Type-C flash drive is enumerated succesfully on all ports. Verified all major power flows (boot, reboot, powerdown and S0ix/suspend) still work as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/intel/tigkerlake: Add IOM PCR PIDTim Wawrzynczak
Required for accessing IOM REGBAR space. Change-Id: Ic1c9beee69d184388f3e850744b3aeebe38eafbb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/intel/tigerlake: Add known CPU Port IDs for GPIO communitiesTim Wawrzynczak
Change-Id: I97c00e1985f319ff1db57314723d8405c2a6cbd2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/intel/common: Add CPU Port ID field to GPIO communitiesTim Wawrzynczak
The CPU can have its own Port IDs when addressing GPIO communities, which differ from the PCH PCR IDs. 1) Add a field to `struct pad_community` that can hold this value when known. 2) Add a function to return this value for a given GPIO pad. Change-Id: I007c01758ae3026fe4dfef07b6a3a269ee3f9e33 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-06soc/intel/tigerlake: Add known GPIO virtual wire informationTim Wawrzynczak
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at least some of their groups; add the known information into the community definitions. Change-Id: Icc4581e61ee904cbd998738962d360a58d24bc35 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52589 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-06soc/intel/common: Add virtual wire mapping entries to GPIO communitiesTim Wawrzynczak
Some SoCs may define virtual wire entries for certain GPIOs. This patch allows SoC code to provide the mappings from GPIO pads to virtual wire indexes and bits when they are provided. Also a function `gpio_get_vw_info` is added to return this information. Change-Id: I87adf0ca06cb5b7969bb2c258d6daebd44bb9748 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52588 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-14 15:11:18 +0000