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2020-10-13mb/intel/adlrvp/dsdt.asl: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I6f4d0bf9adc1cce4942a16675a072ffea00bd2e0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-10-13include/acpi/acpi.h: Introduce ACPI_DSDT_REV_2 macroElyes HAOUAS
This to replace DSDT revison number with macro so we can adapt all boards at once if needed. Change-Id: I9e92a5f408f69aa1a6801bc2cba8ddfe2180b040 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-13mb/{51nb/x210,razer/blade_stealth_kbl}/dsdt.asl: decrease DSDT revision from ↵Elyes HAOUAS
0x5 to 0x2 DSDT revision 2 is used for ACPI v2 and greater. Change-Id: Ia019358be6574db1b2b06a8a7d52ae996cf45571 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13mb/intel/latest mainboards: Get rid of power button device in corebootSubrata Banik
Refer to commit d7b88dc (mb/google/x86-boards: Get rid of power button device in coreboot) This change gets rid of the generic hardware power button from all intel mainboards and relies completely on the fixed hardware power button. Change-Id: I8f9d73048041d42d809750fdb52092f40ab8f11f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12soc/intel: Configure PAVP at compile-timeBenjamin Doron
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. Per the FSP default, this was always being enabled previously. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12util/superiotool: Add EC registers for IT8728FMatt DeVillier
Add support for dumping registers, default values for EC on ITE IT8128F. Taken from datasheet 'IT8728F V0.4.2' Test: 'superiotool -d -e' on board with IT8728F Super IO Change-Id: I7074b740565edf458d6894c066b61c083a657cb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12soc/intel/cannonlake: Align cosmetics with Ice LakeAngel Pons
By ironing out cosmetic differences between Cannon Lake and Ice Lake, comparing actual code differences using a diff tool becomes simpler. Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical. Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-12mb/clevo/l140cu: clean up memcfgMichael Niewöhner
The DQ and DQS byte maps do not apply to DDR4 configurations, thus simply drop them. Also drop ECT, as it's already initialized to zero and can't be used on DDR4 anyway. Further, trim down all the meaningless and/or wrong comments. Change-Id: I32f1b7bb46eaaf0f0ecad1df310f5de988f64c85 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46249 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/clevo/l140cu: drop disabled SPD indicesMichael Niewöhner
Drop the disabled SPD indices from memcfg, since they're already initialized to 0. Change-Id: I6d88bdac17222c2c5c35439517fe0bea46744b2b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-10-12mb/clevo/l140cu: drop USE_LEGACY_8254_TIMERMichael Niewöhner
Drop USE_LEGACY_8254_TIMER, since it's not required anymore for booting grub, despite the comment. The issue was resolved upstream five years ago: http://git.savannah.gnu.org/cgit/grub.git/commit/?id=d43a5ee65143f384357fbfdcace4258e3537c214 Test: - Boot EFI GRUB2 from TianoCore payload (Debian Live, Ubuntu installer) - Boot GRUB2 payload Change-Id: I5ce4f5168586bf305969b2e24b6ee895c8552749 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45960 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/clevo/l140cu: set PS/2 timeout for SeaBIOSMichael Niewöhner
The keyboard only works randomly, because SeaBIOS initializes PS/2 before the EC is ready. Set the PS/2 timeout for SeaBIOS to 500 ms, to wait for the EC before initializing the keyboard. Test: keyboard works fine. Change-Id: I2be75961035f04a7ffa6f7e1dbaabb1243b857f9 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45959 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/volteer/var/voxel: disable DdiPortHpdSheng-Liang Pan
GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd BUG=b:169690329 TEST=build and verify type-c(C0/C1) port functional normally Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46069 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/dedede: refactor DPTF section for simpler overridesSumeet R Pawnikar
Refactor DPTF section of code under the baseboard devicetree and overridetree. This makes override mechanism more simpler, because not all the DPTF fields need to be overridden. BUG=None BRANCH=None TEST=Built and tested on dedede system Change-Id: I8e7cfe60c010ed4c07f9089325b289519e861f84 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-12vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3373Srinidhi N Kaushik
Update FSP headers for Tiger Lake platform generated based on FSP version 3373. Previous version was 3333. Changes include below UPDs: ITbtPcieTunnelingForUsb4 SlowSlewRate FastPkgCRampDisable BUG=b:169759177 BRANCH=none TEST=build and boot delbin/tglrvp Cq-Depend:chrome-internal:3308203, chrome-internal:3308204 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2e28905f8f7241940ea92ac3e83b52ff7948953a Reviewed-on: https://review.coreboot.org/c/coreboot/+/45630 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Dossym Nurmukhanov <dossym@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12cpu/qemu-x86/cache_as_ram_bootblock: Fix wrong instructionPatrick Rudolph
The shld instruction does an arithmetic shift left on 64bit operants, but it's not the instruction we want, because what it actually does is shifting by cl, and storing the result in address 32. This wasn't noticed with QEMU as the DRAM is up and address 32 is valid. On real hardware when CAR is running this instruction causes a crash. Replace the instruction with the correct 64bit arithmetic left shift. Change-Id: Iedad9f4b693b1ea05898456eac2050a9389f6f19 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45820 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12nb/intel/i945/acpi: Convert i945.asl to ASL 2.0 syntaxElyes HAOUAS
It builds same binary for apple/macbook21 using BUILD_TIMELESS=1 Change-Id: I332afdcc4a1a7543571d8f9d121d8350347f7153 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45272 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12sb/intel/i82801gx/acpi: Convert *.asl to ASL 2.0 syntaxElyes HAOUAS
Also remove extra empty lines. It builds same binary for apple/macbook21 using BUILD_TIMELESS=1 Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45275 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/ibase/mb899/acpi: Convert platform.asl to ASL 2.0 syntaxElyes HAOUAS
It builds same binary for ibase/mb899 using BUILD_TIMELESS=1 Change-Id: I947c4228641abc38a5cd75e51fa2f096fda95d6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45280 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/intel/d945gclf/acpi: Convert platform.asl to ASL 2.0 syntaxElyes HAOUAS
It builds same binary for intel/d945gclf using BUILD_TIMELESS=1 Change-Id: Ic48008719a9cf6942ae8cdaebaab6ba43e665489 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45281 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/getac/p470/acpi: Convert 'gpe.asl' to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I9f5a89946888be3ed033c2ee079f171a23404e90 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-12mb/getac/p470/acpi/battery.asl: Remove unused remainderElyes HAOUAS
Change-Id: I6ddc3d0c50c5907e24644cea5979d064bea4acd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12superio/smsc/sch5147/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I509b76dbdbdee8a6287fc7d877c9f6e3c6a9068b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12superio/smsc/sio1007/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I9cca957104620e8fd4717d9bb77efa5a2c93b446 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12superio/ite/it8772f/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I9a4d7ddd39800f07300d3b22b02924b696917f28 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12superio/smsc/mec1308/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I7d15dbb90bbf910cdfd59d67fa4d9ca41420b8d9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12superio/fintek/f81803a/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ia7072112a1add1de9c3fb348bc70dbd404337819 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45989 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/intel: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated buils/dsdt.dsl for intel/kblrvp11 are same. Change-Id: I41195be171b48f41fe2955e4639d8b770853d483 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-10-12superio/winbond/*/acpi: Convert superio.asl to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I67e08a1099e41acb7031469069d9eddb274f7735 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45994 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/facebook: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I91f65fecdcdf41dc41f136e8d66bbf730343aef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46078 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/pcengines/apu2: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ie2b1b27c0715fc223e644c3df6c0e9cb876322c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-10-12mb/pcengines/apu1: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: I15b332033f3d492f9e01bb5f1eb25892dee418de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-10-12mb/google/asurada: Add USB supportCK Hu
Change-Id: I35dc4be65f0843c3c74695c443dd958676e6c12c Signed-off-by: CK Hu <ck.hu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-12soc/mediatek/mt8192: Refactor USB code among similar SoCsZhanyong Wang
Adjust ssusb register layout and offset accroding mt8192 Soc then refactor USB code which will be reused among similar SoCs Signed-off-by: Tianping Fang <tianping.fang@mediatek.com> Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com> Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-10-12soc/intel/jasperlake: Allow mainboard to override chip configurationKarthikeyan Ramasubramanian
Add a weak override function to allow mainboard to override chip configuration like GPIO PM. BUG=None TEST=Build and boot waddledee to OS. Ensure that the suspend/resume sequence works fine. Change-Id: I40fa655b0324dc444182b988f0089587e3877a47 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12security/intel/txt: Add and use DPR register layoutAngel Pons
This simplifies operations with this register's bitfields, and can also be used by TXT-enabled platforms on the register in PCI config space. Change-Id: I10a26bc8f4457158dd09e91d666fb29ad16a2087 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46050 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12security/intel/txt: Clean up includesAngel Pons
Sort them alphabetically, and use <types.h> everywhere. Drop unused <intelblocks/systemagent.h> header, too. Change-Id: Ib8f3339e5969cf8552984164fa7e08e070987a24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-10-12mb/google/dedede: Enable SaGv supportAamir Bohra
Allow MRC training in SaGv low, mid and high frequencies. TEST=Verify memory trains at low, mid and high SaGv point through FSP debug logs enabled. Change-Id: I0f60aad031ce9dfe23e54426753311c35db46c05 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45196 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12soc/intel/jasperlake: Correct SaGv mappingAamir Bohra
Jasper Lake support 3 Memory train frequencies low. mid and high. Update the SaGv configuration accordingly. Change-Id: I366de1ea7cf41c56b2954b8032c69bfba81058e2 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
2020-10-12security/intel/stm: Add options for STM buildEugene Myers
This patch adds options that support building the STM as a part of the coreboot build. The option defaults assume that these configuration options are set as follows: IED_REGION_SIZE = 0x400000 SMM_RESERVED_SIZE = 0x200000 SMM_TSEG_SIZE = 0x800000 Change-Id: I80ed7cbcb93468c5ff93d089d77742ce7b671a37 Signed-off-by: Eugene Myers <cedarhouse@comcast.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2020-10-12mb/google/volteer: Fix typo in baseboard power limits Sumeet R Pawnikar
Fix typo for power limit values under comment section in baseboard BUG=None BRANCH=None TEST=Build for volteer system Change-Id: I879b9587e863360bf4efda4099d96b42b904377e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-12soc/intel/common/block/smm: Fix compilation without intel uart codePatrick Rudolph
Allow to link the smihandler when not selecting SOC_INTEL_COMMON_BLOCK_UART. Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-10-12mb/ocp/deltalake: Select correct uart for consolePatrick Rudolph
Tested on OCP deltalake. The console now shows up on the serial. Change-Id: If4c412c1ca749f1feba47b2ce0beb52d0111be86 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-10-12soc/intel/common/block/i2c: Scan bridge devices behind I2C controllersKarthikeyan Ramasubramanian
Currently devices behind I2C controllers are scanned using scan_smbus. This is done under the assumption that there are no bridge devices behind I2C controllers. In order to support I2C multiplexers which act as bridge devices and have devices behind them, scan the I2C controllers using scan_static_bus. BUG=b:169444894 TEST=Build and boot waddledee to OS. Ensure that all the bridge devices behind I2C controller are scanned and enabled. Change-Id: I9d8159a507683d8c56dd5e59d20c30ed7e4b2cab Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-12mb/intel/tglrvp: Enable early EC syncAnil Kumar
- This change is required to execute EC sync in coreboot instead of depthcharge Bug=none Test=build and boot coreboot on TGLRVP Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I40ae104d4de93c12097e049253a33b23a46c6203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44689 Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/intel/tglrvp: Add support of TPM over SPIShaunak Saha
Bug=none Test=emerge build and boot on tglrvp and check that tpm is probed successfully from coreboot. Cq-Depend:chromium-review:1881839 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I4a3aec98f72524e8e2a1834878ef75b9f933ae3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2020-10-12util/intelp2m: Update output information format in the commentsMaxim Polyakov
Update the information format in the comments above the macros in the generated gpio.h file: PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART0_TXD */ -->(i) /* GPIO_39 - LPSS_UART0_TXD */ --> (ii) /* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) /* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii) /* _PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), */ --> (iiii) PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), Also, in the case of field macros: /* GPIO_39 - LPSS_UART0_TXD */ --> (ii) /* DW0: 0x44000400, DW1: 0x00003100 */ --> (ii) /* DW0 : PAD_TRIG(OFF) - IGNORED */ --> (iii) /* PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), */ --> (iiii) PAD_CFG_STRUCT(GPIO_39, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF), PAD_PULL(UP_20K) | PAD_IOSTERM(DISPUPD)), By default, if do not use the -i... option, then additional information in comments will not be generated. TEST: git clone https://github.com/maxpoliak/inteltool-examples.git test ./intelp2m -n -file test/inteltool-asrock-h110m-stx.log ./intelp2m -fld cb -file test/inteltool-asrock-h110m-stx.log ./intelp2m -fld fsp -file test/inteltool-asrock-h110m-stx.log ./intelp2m -fld raw -file test/inteltool-asrock-h110m-stx.log Before and after (now with -i key) the patch, gpio.h is no different. Change-Id: I760f4aadece786ea455fb7569f42e06fefce2b61 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45168 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12arch/x86/smbios: Update SMBIOS type 0 ec versionTim Chu
Update embedded controller firmware version for SMBIOS type 0. TEST=Execute "dmidecode -t 0" to check if the ec version is correct Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ibd5ee27a1b8fa4e5bc66e359d3b62e052e19e8a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12arch/x86/smbios: Update SMBIOS type 4 socket designationTim Chu
Add socket designation in type 4 smbios. TEST=Execute "dmidecode -t 4" to check if the socket designation is correct Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Icfdc201bd5b5921816bdce6c009a9db48c997e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-12mb/google/dedede: update devicetree for Botenalec.wang
Add trackpad, touchscreen, and usb port to devicetree BUG=b:160664447 BRANCH=NONE TEST=build bios and verify theirs function for boten Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com> Change-Id: I057f7d15d20d1a78acd733cc5463357e9c87afb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-12intelmetool: Add PCI ID for Cometlake-UMatt DeVillier
Tested on out-of-tree CML-U Purism board Change-Id: I0371e913a75e47b8e6f5a3e4da47b1e401a72b5d Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45929 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-11 21:58:59 +0000