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2011-06-28msrtool: added support for Intel CPUsAnton Kochkov
Change-Id: I05f54471665aa99335a88d097c6de20174f91dc6 Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-on: http://review.coreboot.org/50 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28SMM: add guard and include types.h in cpu/x86/smm.hSven Schnelle
Change-Id: I002845cf7a37cd6885456131826ae0ba681823ef Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/64 Tested-by: build bot (Jenkins)
2011-06-28X60: remove pci config register save/restoreSven Schnelle
SMM code already makes sure this register is saved and restored, so we don't have to do it. Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/65 Tested-by: build bot (Jenkins)
2011-06-23Add SMSC SCH3114 superio register descriptions to superiotool.Mark Norman
This has been tested on a Aaeon PFM-540I RevB PC104 SBC. Change-Id: Ie02875a1fa2d90d7cc843ce745f727312f7b7aec Signed-off-by: Mark Norman <mpnorman@gmail.com> Reviewed-on: http://review.coreboot.org/43 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-23T60: undock on external power lossSven Schnelle
If power is unplugged/lost, we should undock the docking station. The power loss can also be caused by the fact that the user removed the thinkpad from the docking station without pressing the Undock button/hotkey first. Without undocking it on this event, the thinkpad LPC switch will still connect the Docking connector, which causes crashes when docking it again. Change-Id: I9ed783e491827bde20264868eab2b3a79c232922 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/62 Tested-by: build bot (Jenkins)
2011-06-23T60: enable userspace EC eventsSven Schnelle
EC events 0x50-0x5f are never triggered by the EC. Instead they can be generated by writing the wanted events to register 0x2a. Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/61 Tested-by: build bot (Jenkins)
2011-06-23T60: add additional EC eventsSven Schnelle
We missed a few bits, i.e the battery and some hotkey events. Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/60 Tested-by: build bot (Jenkins)
2011-06-23Add ThinkPad modelsSven Schnelle
Change-Id: I4f1a5d99486929eb0be76a0ab3bf0158a23c7d36 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/59 Tested-by: build bot (Jenkins)
2011-06-23T60: add missing License HeaderSven Schnelle
Change-Id: I03636deac7b6d8e01654cf978b1aac79cba10641 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/58 Tested-by: build bot (Jenkins)
2011-06-22X60: add missing License HeaderSven Schnelle
Change-Id: I9d6e80a633990e86dd3adfa2a761d09f62978349 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/57 Tested-by: build bot (Jenkins)
2011-06-22H8: add missing License HeaderSven Schnelle
Change-Id: If472e1e8bb93d64cc52a9084ad33fb9abbf0fb33 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/56 Tested-by: build bot (Jenkins)
2011-06-22PMH7: add missing License HeaderSven Schnelle
Change-Id: I3468689408fce05142a0959d5d725bdbd03faea7 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/55 Tested-by: build bot (Jenkins)
2011-06-22Move SB800 clock init earlierScott Duplichan
Committing Scott's e350m1 changes (svn r6585): Move SB800 clock init earlier, Fixes problem where initial serial port output is garbled. Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/32 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Add the coreboot config to CBFSCristian Măgherușan-Stanciu
The CBFS will contain a new file, named 'config' of type 'raw' that is a stripped-down version of the .config file that was used to build the current coreboot image. For space savings, all the comments and empty lines were removed from the original config, except for one that lists the coreboot git revision that's built into the image. This is done in order to easily reproduce the work of someone else when only having their ROM image. In theory the reproduce could even be automated by a new dedicated make target. This should work even with abuild now. Change-Id: I784989aac0227d3679d30314b06dadaec402749e Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/46 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Move existing AMD Ffamily14 code to f14 folderefdesign98
This change moves the AMD Family14 cpu Agesa code to the vendorcode/amd/agesa/f14 folder to complete the transition to the family oriented folder structure. Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/52 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-21Add AMD SB900 CIMx codeefdesign98
This code is added to support the AMD SB900 southbridge. Change-Id: I7dc5e13a53ffd479dcea4e05e8c8631096e2ba91 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/41 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-21Add AMD Family 12 cpu Agesa codeefdesign98
This is the addition of the AMD Family 12 cpu code. Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c Signed-off-by: Frank Vibrans<frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/40 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20sb800: move spi prefetch and fast read mode to sb bootblock.Stefan Reinauer
So we don't waste time on the first cbfs scan. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> [adapt persimmon with the same change, and work around romcc bug in bootblock code: it doesn't like MEMACCESS[idx] |= value;] Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997 Reviewed-on: http://review.coreboot.org/9 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20Introduced support for 8MB and 16MB flash sizesCristian Măgherușan-Stanciu
Change-Id: I217ff84be3575ec09781710f19ad272c88227663 Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-on: http://review.coreboot.org/49 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-20ASRock E350M1: Enable USB3 supportMarshall Buschman
Requires Scott Duplichan's patch for NIC support. Enables required PCIe port for USB3 - does not interfere with normal operations on non-USB3 model. Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9 Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/45 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-19ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nicScott Duplichan
Scott Duplichan's patch from the mailing list: sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function once, after determining device 0x15 function enables. 1) Update the asrock e350m1 devicetree.cb to match the hardware. 2) Change the way the sb800 cimx wrapper code works. The original cimx code calls sb800 cimx function sbBeforePciInit() once. When ported to coreboot, the gpp component of this function was called once for each gpp port, as the gpp port's enable/disable state became known. A 05/15/2011 change makes the early gpp code run only once, triggered by processing the 4th gpp port. This method is not general enough because the 4th gpp port is not enabled on all boards. With the current change, the early gpp code runs when the first gpp port is processed. If any gpp ports are enabled, the first must be enabled. Tested with Win7 and linux on asrock e350m1. This change will also affect amd inagua, and has not been tested on that board. Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/44 Tested-by: build bot (Jenkins) Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-18SMM: flush caches after disabling cachingSven Schnelle
Fixes spurious SMI crashes i've seen, and ACPI/SMM interaction. For reference, the mail i've sent to ML with the bugreport: whenever i've docked/undocked the thinkpad from the docking station, i had to do that twice to get the action actually to happen. First i thought that would be some error in the ACPI code. Here's a short explanation how docking/undocking works: 1) ACPI EC Event 0x37 Handler is executed (EC sends event 0x37 on dock) 2) _Q37 does a Trap(SMI_DOCK_CONNECT). Trap is declared as follows: a) Store(Arg0, SMIF) // SMIF is in the GNVS Memory Range b) Store(0, 0x808) // Generates I/O Trap to SMM c) // SMM is executed d) Return (SMIF) // Return Result in SMIF I've verified that a) is really executed with ACPI debugging in the Linux Kernel. It writes the correct value to GNVS Memory. After that, i've logged the SMIF value in SMM, which contains some random (or former) value of SMIF. So i've added the GNVS area to /proc/mtrr which made things work. I've also tried a wbinvd() in SMM code, with the same result. After reading the src/cpu/x86/smm/smmhandler.S code, i've recognized that it starts with: movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx) movl %cr0, %eax andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */ orl $0x60000001, %eax /* CD, NW, PE = 1 */ movl %eax, %cr0 /* Enable protected mode */ data32 ljmp $0x08, $1f ...which disables caching in SMM code, but doesn't flush the cache. So the problem is: - the linux axpi write to the SMIF GNVS Area will be written to Cache, because GNVS is WB - the SMM code runs with cache disabled, and fetches SMIF directly from Memory, which is some other value Possible Solutions: - enable cache in SMM (yeah, cache poisoning...) - flush caches in SMM (really expensive) - mark GNVS as UC in Memory Map (will only work if OS really marks that Area as UC. Checked various vendor BIOSes, none of them are marking NVS as UC. So this seems rather uncommon.) - flush only the cache line which contains GNVS. Would fix this particular problem, but users/developers could see other Bugs like this. And not everyone likes to debug such problems. So i won't like this solution. Change-Id: Ie60bf91c5fd1491bc3452d5d9b7fc8eae39fd77a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/39 Tested-by: build bot (Jenkins)
2011-06-18T60: set dock LED's in mainboard.cSven Schnelle
The docking takes place in romstage to have early serial I/O for debugging. But to keep romstage small and prevent linking the EC code to romstage, set the status LED's in ramstage. Change-Id: I89fadbd61b6bfd9aff8c22370e51c84325f24751 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/42 Tested-by: build bot (Jenkins)
2011-06-16X60/T60: disable USB power during suspendSven Schnelle
Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/38 Tested-by: build bot (Jenkins)
2011-06-16Lenovo H8 EC: add usb_power_enable()Sven Schnelle
Can be used to disable/enable Power output on USB ports. Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/37 Tested-by: build bot (Jenkins)
2011-06-15SMM: don't overwrite SMM memory on resumeSven Schnelle
Overwriting the SMM Area on resume leaves us with all variables cleared out, i.e., the GNVS pointer is no longer available, which makes SMIF function calls impossible. Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/34 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15i945 GMA: restore tft brightness from cmosSven Schnelle
Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/24 Tested-by: build bot (Jenkins)
2011-06-15Remove old ACPI codeSven Schnelle
it isn't used anywhere, and could be fetched from git/svn history if needed. Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/35 Tested-by: build bot (Jenkins)
2011-06-15i82801gx: replace cafed00d/cafebabe by definesSven Schnelle
We're using '0xcafed00d' all over the code as magic for ACPI S3 resume. Let's add a define for that. Also replace 0xcafebabe by a define. Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/33 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-15Update README with newer version of the text from the web pageStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: I4f181979ca5e47b27731c681a320b34cbecc0027 Reviewed-on: http://review.coreboot.org/19 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com> Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-06-15X60: handle EC events in SMM if ACPI is disabledSven Schnelle
Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/27 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15X60: trigger save cmos on volume/brightness changeSven Schnelle
Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/25 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15CMOS: add set_option()Sven Schnelle
Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/23 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-13X60/T60: set CMOS defaultsSven Schnelle
Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/26 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-12ASRock/E350M1: Skip memory clear for boot time reductionMarshall Buschman
Applying Scott's patches to e350m1, svn r6600: Memory clear is not required for non-ECC boards. Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1 Signed-off-by: Scott Duplichan <scott@notabs.org> Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/20 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-12X60/T60: fix return value of mainboard_io_trap_handler()Sven Schnelle
The handler should return 1 if it handled the request. The current code returns 0, which causes 'Unknown function' logs. Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/29 Tested-by: build bot (Jenkins)
2011-06-12log ec data with DEBUG_SPEWSven Schnelle
Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/28 Tested-by: build bot (Jenkins)
2011-06-10Add ACPI automatic PIC/APIC interrupt routing logic for ck804Jonathan A. Kollasch
Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840 Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/13 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-09superiotool: Cosmetics and coding style fixes.Uwe Hermann
Change-Id: Iacda2a9e37635d5cffc5004caf588ef3e5e09b5e Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Reviewed-on: http://review.coreboot.org/18 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2011-06-09H8 EC: add volume CMOS settingSven Schnelle
Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/12 Tested-by: build bot (Jenkins)
2011-06-09util/crossgcc: Add build-without-gdb Makefile targetPeter Stuge
Change-Id: I5d02f1a23e54aa67be0cc01d921898c28c22f8e4 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/16 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
2011-06-09util/crossgcc: Add buildgcc -G and --skip-gdb optionsPeter Stuge
Change-Id: Ic31130774ad56abf0b5498b04b4890348352a621 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/15 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
2011-06-09Change make crossgcc to build without gdb by defaultPeter Stuge
Using gdb with coreboot is not (yet) very common, so at least for now it makes sense to not build gdb by default. A make crosstools target is also added, which runs the full build in util/crossgcc and thus generates a toolchain with both compiler and debugger. Change-Id: I939ebcd06ae9a1bc485fd18e70cac98112d3bbbf Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/17 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
2011-06-09Revert changes to set the sb800 to AHCI mode.Marc Jones
Seabios doesn't have this support included yet, which causes the generic Persimmon and other CIMx sb800 platforms to not boot. Change-Id: If07328b7c62d7fc314647adce8fab983ed327854 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: http://review.coreboot.org/14 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-09Add basic .gitignoreCristian Măgherușan-Stanciu
Ignore directories created by abuild, jenkins, payloads and crossgcc. Change-Id: I7d4145fc1e54a10ffdc4b884d8b8f0ae53e615c6 Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/10 Tested-by: build bot (Jenkins)
2011-06-07T60/PMH7: move 'touchpad' option to pmh7Sven Schnelle
This option is PMH7 specific, and should be moved there, so all Notebook utilizing a PMH7 have this option. For Thinkpads without Touchpad (like the X60), simply don't add 'touchpad' to cmos.layout. Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/6 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-07i82801gx: enable ACPI during S3 resumeSven Schnelle
disabling ACPI during S3 wakeup breaks ACPI wakeup, as the Host OS is assuming that ACPI is enabled. Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/7 Tested-by: build bot (Jenkins)
2011-06-07SMM: add defines for APM_CNT registerSven Schnelle
in the current code, the defines for the APM_CNT (0xb2) register are duplicated in almost every place where it is used. define those values in cpu/x86/smm.h, and only include this file. And while at it, fixup whitespace. Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484 Signed-off-by: Sven Schnelle <svens@stackframe.org> Reviewed-on: http://review.coreboot.org/4 Tested-by: build bot (Jenkins)
2011-06-07Add "gitconfig" make target to simplify gerrit configurationPatrick Georgi
"make gitconfig" installs the gerrit commit-msg hook and validates that user.name and user.email are configured. No data will be overwritten. Change-Id: I49ec98538574866e7ad6238ff3d02b9c1beef1bb Reviewed-on: http://review.coreboot.org/2 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
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