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2018-05-21sb/amd/sb600: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I587b32e33af72a37be8299b9db2ce26ba825a689 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-21sb/amd/rs690: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I818f808e1cd8b156158251724352f8be6041030c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-21google/kahlee: Reduce UMA memory to 32MBMarshall Dawson
Lower the amount of UMA memory to 32MB at AMD's request. TEST=none BUG=b:79906569 Change-Id: Ib1365dc38850b4b92c944ff95534573addbe4362 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26383 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21google/grunt: Reduce UMA memory to 32MBMarshall Dawson
Lower the amount of UMA memory to 32MB at AMD's request. TEST=boot Grunt, try S3 BUG=b:79906569 Change-Id: I5af038688b38b53c94b8265823eeee0f37980522 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-21mb/google/octopus: Add devicetree for BipJustin TerAvest
Bip should have different devicetree entries than Yorp; it doesn't have a DA7219 audio codec (instead it uses ALC5682). BRANCH=none BUG=b:79771967 TEST=boot, no longer see DA7219 ACPI in console. Change-Id: Ic63bbc51e122afc9fc2e8ec7fb024d18a3815b38 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/26342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-05-21cimx/sb800: Use PCI_DEVFN()Kyösti Mälkki
Change-Id: I2d01714e2a72810fe1b6567e7f1b2aab00ac5c80 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-21agesa/hudson pi/hudson: Use PCI_DEVICE_IDKyösti Mälkki
Change to 16bit read of the standard register. Change-Id: Id085935eb17838c07bd78716158e622f45f56906 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-21agesa/hudson pi/hudson: Skip device node searchKyösti Mälkki
The device node with requested path is already known. Change-Id: I2de6a2a6893b1a24085ebcafd5d7604214ed10ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-21sb/nvidia/ck804: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I59078ff96428d134f108ff2551556c8a7d2d3b37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-21sb/ricoh/rl5c476: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I04a1fc27f67555132667e42f14fd0263a18b56c6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-21nb/via/vx800: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ib432d3c3ce2788b0138a1b0e852385ab4f9b65ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-21nb/via/cn700: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ic58bb58b88ffc309472ee9ffc8a9c8619659811b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-21cbfs-compression-tool: Fix minor edge cases in algorithm type parsingJulius Werner
This patch adds two minor improvements to the way cbfs-compression-tool parses the compression algorithm type that is passed through the -t option of the 'compress' subcommand. These improvements are intended to prevent accidents and unexpected behavior when using the cbfs-compression-tool, in particular in automated contexts such as a Makefile rule. In the first part of this patch, a return statement is inserted after the 'if (algo->name == NULL)' check of the compress() function. This causes the function to exit immediately and subsequently abort the program when the algorithm type was not detected correctly. Previously, execution would continue with the 'algo' pointer pointing to the zeroed out stopper entry of the types_cbfs_compression[] array. The ultimate effect of this would be to pass 0 as 'algo->type' to the compression_function() function, which happens to be the same enumeration value as is used for CBFS_COMPRESS_NONE, leading to a valid compression function result that matches the behavior of no compression. Thus, if a script calling cbfs-compression-tool compress contained a typo in the -t parameter, it would continue running with an unintended compression result rather than immediately exiting cleanly. In the second part of this patch, the strcmp() function is replaced with strcasecmp() when comparing 'algo->name' with the 'algoname' parameter that was passed to the compress() function. strcasecmp() uses an identical function signature as strcmp() and is thus suitable as a drop-in replacement, but it differs in behavior: rather than only returning a result of 0 when the two NULL-terminated input strings are character by character identical, the strcasecmp() function applies a weaker concept of identity where characters of the latin alphabet (hexadecimal ranges 0x41 through 0x5a and 0x61 through 0x7a) are also considered identical to other characters that differ from them only in their case. This causes the -t parameter of cbfs-compression-tool compress to also accept lowercase spellings of the available compression algorithms, such as "lz4" instead of "LZ4" and "lzma" instead of "LZMA". As an unintended but harmless side-effect, mixed-case spellings such as "lZ4" or "LZmA" will also be recognized as valid compression algorithms. (Note that since the character "4" (hexadecimal 0x34) of the "LZ4" compression type name is not part of the above-mentioned ranges of latin alphabet characters, no new substitutions become valid for that part of the "LZ4" string with this patch.) Change-Id: I375dbaeefaa0d4b0c5be81bf7668f8f330f1cf61 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-21nb/intel/nehalem: Fix smashed stack in romstageMatthias Gazzari
Stack smashing was detected during raminit when not loading from MRC. Adding CAR_GLOBAL to a struct inside raminit was suggested in https://mail.coreboot.org/pipermail/coreboot/2018-May/086677.html in order to fix the problem. Adding CAR_GLOBAL to the ram timings variable solves the issue (adding it to the ram_training or raminfo struct had no effect). This is just a workaround and might need a proper fix in the future. Tested on Lenovo X201i with 2+2 and 4+4 GB RAM. Change-Id: I21b380db61be2aedc045201821d83e18e7d07ad1 Signed-off-by: Matthias Gazzari <mail@qtux.eu> Reviewed-on: https://review.coreboot.org/26388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-21util/docker: Update coreboot-sdk dockerfile dependencies listMartin Roth
- Remove archive utilities no longer needed by EM100 build - Remove duplicate libgmp-dev entry - Add graphviz needed for doxygen builds Tested building to verify dependencies: coreboot(what-jenkins-does), em100, chromeec, flashrom, SeaBIOS, TINT, memtest86+, tianocore, doxygen, ipxe, FILO, GRUB, libpayload, depthcharge Tested ROM in QEMU Change-Id: Idb5cf43807706b3298ee08f6707f495d3a79abb6 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26393 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-21util/testing: Update junit.xml to support coreboot buildsMartin Roth
Up to this point, junit.xml has only been used to build tools, as abuild has handled the coreboot builds. To add additional tests not covered by abuild, we need junit.xml to work with bare directories. This also requires updating the build directory (BLD_DIR) for existing builds using the junit.xml target. Change-Id: If6e27e02e25e20f48e5a9372373de6058ca378dd Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-05-21libpayload: Fix payload .bss corruptionKyösti Mälkki
Third call to newwin() corrupted payload context. Fix array indexing and check for boundary. Sample payload coreinfo was affected, loader_eax variable got corrupted on my particular build. Change-Id: Iee98901cf57f0689f65ac43aa7e60e8aea092500 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-20Documentation: Add lesson1 from the wikiMartin Roth
Convert the lesson1 document from the wiki to markdown, update it for Ubuntu 18.04, and extend it slightly with new information. Change-Id: Ieab60148f8bdd340e4c4c4c1dd7b6ed18fbd6ed7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Tested-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-20Makefile.inc: disable warnings on unaligned struct membersPatrick Georgi
We use packed structs with unaligned members all the time, which is the entire point of us using the packed attribute. Change-Id: Ib26b422ba83257d1a7f26134ee20217fad5823cd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-20sb/amd/cimx/sb900: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Id634edd7005db85690cdc93579c1f97588ffc5f8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20sb/amd/common: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ie16a1c131ec41eeccc0bf5235b3fc2341095d4a8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20nb/amd/agesa/family14: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I9841fa591c4051653267b9e7c2f5b347d6f25b74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20sb/amd/agesa/hudson: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I85aafdc204731734ba4f02551ba5ccdd6535df77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20nb/amd/agesa/family12: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I265130532965c1655c34fd7dab6ca9ef0e27beca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20sb/amd/pi/hudson: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Iace820ad788fde7b230f63d95543470ce925b451 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20sb/amd/cimx/sb800: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I2335b7e193663bb6c82bf267aaeb0b2367986f62 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-19lib/gnat: Drop Restriction `No_Exception_Propagation`Nico Huber
It turns out that even with the `-gnatp` switch to suppress runtime checks, the compiler is still allowed to generate them (it only doesn't have to). If we can't control generation of checks, we also can't make assumptions about propagation of their exceptions. The compiler warning that led to this change seems spurious, though (the check might be generated, but is dropped later). So we might revert this decision if the compiler can be fixed. Change-Id: I7470d74b1f96f90d0d15b24dfd636d5f1c778d46 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-19Documentation: Add mainboard section to indexJonathan Neuschäfer
Change-Id: Ib00bd6cdd13f164ca7eb07c9092e8d8fe17d23b1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/26266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-19configs: add PC Engines apu2 sample configurationPiotr Król
Change-Id: Ia131c8aec1235443465bc017e11f59f38bef76db Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/26118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-19mb/google/octopus: enable xdci controllerJagadish Krishnamoorthy
BUG=b:79343083 BRANCH=NONE TEST=On Yorp board, lspci should list xdci, 00:15.1 USB controller Change-Id: I3a4878389a1b5b7abcaccf6ab16b67848aaaee83 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/26358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-19mb/google/reef/variants/: Add new memory IDren kuo
Add a new RAM ID of memrory PN:K4F6E3S4HM-MGCJ BUG=b:78491470 TEST= emerge-coral coreboot chromeos-bootimage. Change-Id: Ic40e36ab222572945f8588eb3df063e4fe0dbeb5 Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/26365 Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-19via/vx900: Remove leftover codeKyösti Mälkki
Code is not used with EARLY_CBMEM_INIT and it appears to have been invalid register anyways. Change-Id: If0662937b38aec71292113ce8abd88da0b73feee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-19cpu/x86: Add support to run function on single APSubrata Banik
This patch ensures that user can select a specific AP to run a function. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: Iff2f34900ce2a96ef6ff0779b651f25ebfc739ad Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26034 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-19soc/intel/cannonlake: Add CONFIG_SMM_RESERVED_SIZE configSubrata Banik
This patch ensures to make SMM_RESERVED_SIZE for cannonlake platform else smm_subregion() returns 0 size. Change-Id: I6a95a244bbcf40d672fd11d1c62e01224b2554f2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2018-05-18util/cbmem: Fix compare function for qsortFurquan Shaikh
compare_timestamp_entries will fail for entries that are different by at least 2^32 since entry_stamp is 64-bit and the return for compare is 32-bit. This change fixes compare_timestamps by actually comparing the entries to return 1, -1 or 0 instead of doing math on them. TEST=Verified that "cbmem -t" sorts entries correctly on previously failing entries. Change-Id: I67c3c4d1761715ecbf259935fabb22ce37c3966e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-18arch/x86: Increase TIMESTAMP region size to 0x200Furquan Shaikh
With the recent change 4c518e1 (timestamp: Add timestamps for TPM communication) to add more timestamps for TPM communication, now we are overflowing the TIMESTAMP region in verstage. This change increases TIMESTAMP region size to 512 bytes to accomodate this. BUG=b:79888151, b:79974682 Change-Id: I94c5403f256f0176d10ac61e9e1f60adf80db08b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-05-18Makefile.inc: Ignore IASL empty resource template warningsMartin Roth
As I mention in the comment, this is valid ASL, which was added as a warning with the comment "This would appear to be worthless in real-world ASL code." While code using empty resource templates could probably be rewritten, this seems like an arbitrary choice to generate this as a warning, since it's valid. This gets rid of warnings such as this one: dsdt.aml 2975: Return (ResourceTemplate() {}) Warning 3150 - Empty Resource Template (END_TAG only) Which is generated by this code in google/rambi/acpi/mainboard.asl: Method (_CRS) { /* Only return interrupt if I2C1 is PCI mode */ If (LEqual (\S1EN, 0)) { Return (^RBUF) } /* Return empty resource template otherwise */ Return (ResourceTemplate() {}) } Change-Id: I9cfe9069c738a284aa85feada9d58e1aee97e433 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26352 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18libpayload: disable mouse on CHROMEOSPatrick Georgi
We already have that Kconfig flag, so I guess we should use it for consistency. Change-Id: I61ee6a97e369ccfe5c55d4414a5fa91c8d80ecf7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/26351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-18mb/google/eve: Describe USB devices in devicetreeDuncan Laurie
Describe the USB devices in the devicetree so they can get generated into the SSDT and presented to the OS. This was tested on an eve board and the resulting SSDT was verified to show the expected values in _UPC and _PLD. Change-Id: I292426f588ea74d61a5c4e4b01386bb18834c117 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18soc/amd/stoneyridge: Support ACPI USB code generationDuncan Laurie
To support generating USB devices in ACPI the platform needs to know how to determine a device name for each USB port, and for any root hubs that may be present. The AMD Stoney Ridge platform has separate controllers for USB 2.0 and USB 3.0. The USB 2.0 ports are connected through a hub to an EHCI controller while the USB 3.0 ports are directly connected to the xHCI controller. This topology is described in ACPI and the port names are exposed by the soc_acpi_name() function. The USB controllers are configured to scan for static USB devices in the devicetree and use the soc_acpi_name() function to identify them. Change-Id: I2bb677f84a49d2531929985dba319455b88e1686 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18soc/intel: Add support for USB ACPI code generationDuncan Laurie
To support generating USB devices in ACPI the platform needs to know how to determine a device name for each USB port, and for any root hubs that may be present. Recent Intel platforms route all ports to an XHCI controller through a root hub. This is supported by considering the root hub to be USB port type 0, the USB 2.0 ports to be type 2, and the USB 3.0 ports to be type 3. This was tested with a Kaby Lake platform by adding entries to the devicetree and checking the resulting SSDT. Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-18drivers/usb/acpi: Add a driver for generating USB ACPIDuncan Laurie
Add a support for generating USB port descriptors for ACPI based on their definition by the board in devicetree.cb. This will generate a _UPC and _PLD for each port, using a generic _PLD by default. The _PLD can also be customized for more accurate descriptions if necessary. This sample devictree.cb shows a USB 2.0 type-A port behind a root hub connected to an xHCI controller: device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device usb 0.0 on chip drivers/usb/acpi register "desc" = ""USB 2.0 Type-A"" register "type" = "UPC_TYPE_A" device usb 2.0 on end end end end end It will generate the following ACPI code in the SSDT: Scope (\_SB.PCI0.XHCI.RHUB.HS01) { Name (_DDN, "USB 2.0 Type-A") Name (_UPC, Package (0x04) { 0xFF, 0x00, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x1, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "RECTANGLE", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) } Change-Id: I7024390e407fda4b195211bd4755bb5ca53b2b37 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26173 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18acpi: device: Walk up the tree to find identifierDuncan Laurie
Instead of just checking the immediate parent for an device name, walk up the tree to check if any parent can identify the device. This allows devices to be nested more than one level deep and still have them identified in one place by the SOC. Change-Id: I9938fc20a839db91ff25e91bba08baa7421e3cd4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26172 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18nb/common/intel: Remove the mrc cache codeArthur Heymans
This is now unused, since all intel northbridges now use the equivalent in drivers/mrc_cache. Change-Id: I3e4b4afa53acc0a82b4ba961f13f816b04931fea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23485 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18nb/intel/nehalem: Use the common mrc cache driverArthur Heymans
The common mrc cache driver allows to save the raminit training results to a separate fmap region which is more manageable than a cbfsfile. Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18intel/fsp: Update Cannonlake FSP headerLijian Zhao
Update Cannonlake FSP header to version 7.x.2E.50, the following changes were made, Memory Init UPD: 1. Add GDXC configuration options. 2. Remove some internal graphics memory selections. 2. Remove Fixed mid option for SaGv. 3. Add DualDimm per channel board type. 4. Remove PEG IMR options. Silicon Init UPD: 1. Add CD clock selections of 675MHz. 2. Remove Pcode PreWake/Rampup/RampDn time selections. 3. Remove C3 state demotion/unDemotion selections. BUG=None TEST=Build and boot up on meowth platform. Change-Id: I08ffb14df9f32089dbf44fa5bd3fc58a5bedb90d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/26148 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18arch/x86/acpigen: Fix corner case in _ROM generatorPatrick Rudolph
In case the Option ROM isn't a multiple of 4KiB the last buffer was truncated to prevent a buffer overrun. But tests on nouveau showed that nouveau expects a buffer that has the requested size and is zero padded instead. Always return a buffer with requested size and zero pad the remaining bytes. Fixes nouveau on Lenovo W520 with Option ROM not being multiple of 4 KiB. Change-Id: I3f0ecc42a21945f66eb67f73e511bd516acf0fa9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Rikken <nico@nicorikken.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-05-18sb/intel/i82801bx: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I661b2435d9f0306b246a3e89aac24eb30c959085 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18sb/intel/i82801ax: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I5c18fdc24bd0432f6b7a1131af68c792d377c3ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18nb/intel/e7505: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I2176ea83fac30052c02d9f6e98c89c40436a38e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 06:52:59 +0000