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2021-03-05soc/intel/apollolake: Add `GPE0_STS_BIT` macroAngel Pons
The datasheet indicates that this bit is reserved. However, subsequent patches need to use this macro in common code, or else builds fail. To iron out this difference, mask out the bit in `soc_get_smi_status`, so that common code always sees it as zero. Finally, add an entry for the bit in `smi_sts_bits` for debugging usage, noting that it is reserved. Change-Id: Ib4408e016ba29cf8f7b125c95bfa668136b9eb93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik
Convert the lines starts with whitespace with tab as applicable. Change-Id: Ife7b27360661cbfd2c90e2b643ed31225ded228c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51250 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05mb/google/zork/var/vilboz: Update telemetry settingsJohn Su
Update telemetry settings for vilboz. VDD Slope : 26939 -> 27225 VDD Offset: 125 -> 187 SOC Slope : 20001 -> 26559 SOC Offset: 168 -> 89 BUG=b:177162553 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/51165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-03-05mb/google/volteer: Fix FPMCU pwr/rst gpio handlingNick Vaccaro
1. No gpio control in bootblock 2. Power on and then deassert reset at the end of ramstage gpio 3. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #3 and wrapping around to #2. This change affects the following volteer variants that include an FPMCU: 1. Drobit 2. Eldrid 3. Elemi 4. Halvor 5. Malefor 6. Terrador 7. Trondo 8. Voema 9. Volteer2 10. Voxel BUG=b:178094376 TEST=none Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and socBrandon Breitenstein
The original implementation of early tcss resulted in calling to mainboard then back to soc then back to mainboard to properly configure the muxes. This patch addresses that issue and instead just gets all the mux information from mainboard and does all config in the soc code. BUG=none BRANCH=firmware-volteer-13672.B TEST=Verified functionality is not effected and early TCSS still functions Change-Id: Idd50b0ffe1d56dffc3698e07c6e4bc4540d45e73 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05soc/intel/tigerlake: Fix NULL being passed for response bufferFurquan Shaikh
`pmc_send_ipc_cmd()` expects the caller to pass in a pointer to a valid request and response buffer. However, early_tcss driver was passing in a NULL pointer for response buffer which would result in invalid access by `pmc_send_ipc_cmd()`. Currently, the response buffer is not used in `update_tcss_mux()`. So, this change drops the passing of `rbuf` parameter to `send_pmc*` helpers and instead uses a local `rsp` variable in the respective functions. All the PMC functions used in early_tcss driver return some kind of response. These should be checked to return appropriate response code back to the caller. However, this needs to be done as a separate change. Change-Id: I215af85feed60b6beee17f28e3d65daa9ad4ae69 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-04soc/amd/cezanne/chipset.cb: clean up and change some aliasesFelix Held
With the aliases some of the comments are redundant. I'm still not sure if the Ethernet controller on the embedded SKUs supports 10G or only 1G. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1e432c12f92a622f8ee05be19acb2c304dd74afb Reviewed-on: https://review.coreboot.org/c/coreboot/+/51242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-04vc/amd/fsp/picasso: fix DDI enum name prefixFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12ec6a3c2704effc1a626181898a9ed7a17f0640 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51239 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04soc/amd/cezanne/smihandler: implement S3 entry SMI handlerFelix Held
Since the support for the GSMI ELOG isn't implemented in the SMI handler yet, the corresponding code isn't added to fch_slp_typ_handler in this patch. BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia27b2486dde1a373607ce895a975e873d9026ba1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-04soc/amd/cezanne: add SMU supportFelix Held
BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b9b4c3d57945ea7c3287cf47f3d9704f42ff24b Reviewed-on: https://review.coreboot.org/c/coreboot/+/51233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-04src/drivers/i2c/rx6110sa: Add official ACPI IDWerner Zeh
In commit 2609eaaa8f (src/drivers/i2c/rx6110sa: Omit _HID temporarily) the randomly assigned and therefore wrong ACPI ID for RTC RX6110SA was removed. In the meantime Seiko-Epson did a great job and registered an official vendor ID in the ACPI database [1]. Further on, Seiko-Epson has now assigned the unique Product Identifier for the RX6110SA, which is '6110'. The assignment of the Product Identifier is controlled by the vendor and there is no official database where this ID is stored in. It is up to the vendor to make sure that this ID stays unique. This patch adds this new vendor and product ID to the driver. Together with a pending Linux patch this RTC is now useable as ACPI device in Linux. [1] https://uefi.org/ACPI_ID_List?search=SECC Change-Id: I45838162f014a760520692c6dcaae329ad98547d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51176 Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Johannes Hahn <johannes-hahn@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04drivers/generic/max98357a: Use depends HAVE_ACPI_TABLESEric Lai
Replace if HAVE_ACPI_TABLES statement with depends HAVE_ACPI_TABLES. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie6ebfde49f0f3c205e174c5113feb75444dedba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-04drivers/generic/alc1015: add ALC1015 AMP driverEric Lai
Add ALC1015 AMP support. ALC1015Q-VB Datasheet Rev 0.1 BUG=b:177971830 TEST: ALC1015P driver can probe properly. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Id93845024aa2cded69acc88d594c222f2f821f79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51051 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04mb/google/volteer/variants/copano: Describe USB ports in devicetreehao_chou
Modify USB port to match schematics. And assigned USB2 port to type-c use. BUG=b:177481079 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Change-Id: I25412d16df8ad809c05635022c11bd8882d002c5 Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49980 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04soc/rockchip/rk3399/sdram: Add channel to error messageMoritz Fischer
When printing error information during DRAM training, be more verbose by printing the channel number. Change-Id: If4109bd0573e3d9f90d699d89350ddbcc48714d3 Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-04soc/rockchip/rk3399/sdram: Simplify error conditionMoritz Fischer
There is no need for explicit 0 comparison, any return value not equal to 0 is treated as error. Change-Id: I72612af4108a616b6247ee68c8ac2a53242b0853 Signed-off-by: Moritz Fischer <moritzf@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-03vc/amd/fsp/picasso: increase FSPS UPD block size from 0x152 to 0x202Nikolai Vyssotski
We will need more FSPS UPD space for PEI GOP changes coming. BUG=b:171234996 BRANCH=Zork Cq-Depend: chrome-internal:3609213, chromium:50576 Change-Id: I35d0bb0ee30e04f66882b6103acd9d673d040c07 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-03amd_blobs: update submodule pointerNikolai Vyssotski
Pick up build 0x26 Picasso FSP binaries. The changes include increased FSPS UPD block size from 0x152 to 0x202. Change-Id: I11fc199ca7bc6ee7431c59d35a60d9ebd977bf10 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-03MAINTAINERS: Add Jakub as maintainer for tests/Patrick Georgi
He practically is, so let's make it official. Change-Id: I8adae5071f94ff309834fcab17b5a722e5c44b10 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Dabros <jsd@semihalf.com>
2021-03-03soc/amd/cezanne/chipset.cb: rename alias for SATA controllersFelix Held
Renoir/Cezanne have two SATA controllers with 2 ports each, so call them sata_0 and sata_1. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51190 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/google/zork/var/vilboz: Update WiFi SAR for VilbozFrank Wu
Loading wifi_sar-vilboz-1.hex for vilboz360 LTE sku for the present. BUG=b:177684735, b:176168400 BRANCH=zork TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are in CBFS and loaded by iwlwifi driver. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-03mb/amd/majolica: Add eSPI supportZheng Bao
Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-03mb/google/brya: Add support for 2 new DRAM partsAmanda Huang
1) Micron MT53E1G32D2NP-046 2) Micron MT53E2G32D4NQ-046 BUG=b:181378727 TEST=none Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03util: Add new memory part to LP4x listAmanda Huang
Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes are derived from data sheets.Also, regenerate the SPD files for ADL SoC using the newly added parts. BUG=b:181378727 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03mb/google/brya: fix BT enumeration issueAamir Bohra
Current implementation exposes GPP_F4 cnvi reset pin as reset gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven by SoC. It should not be driven by driver. BUG=b:180875586 Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/common/block/smbus: Add config to use ACPIMaxim Polyakov
Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44865 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel: Guard macro parameters in pm.hAngel Pons
Guard against unintended operator precedence and associativity issues. Change-Id: I342682a57fde9942cdf7be10756ee21c10af802a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50917 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/cannonlake: Move `gpi_clear_int_cfg()` callAngel Pons
To allow unifying bootblock.c in follow-ups, move a function call. Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03soc/intel: Factor out common smmrelocate.cAngel Pons
There are seven identical copies of the same file. One is enough. Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/skylake: Always print ME FW SKUBenjamin Doron
State of ME firmware SKU is independent of power-down mitigation. Change-Id: I014c1697213efaefcb0c2a193128a876ef905903 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03soc/intel/skylake: Enable compression on FSP-SBenjamin Doron
Use LZ4 algorithm to compress FSP-S. This saves ~40 KiB and reduces the boot time by ~7 ms. LZMA would save a further ~1 KiB, but adds ~9 ms to the boot time. LZMA size: fsps_lzma.bin 0xb0dc0 fsp 146578 LZMA (188416 decompressed) LZMA decompression time: 15:starting LZMA decompress (ignore for x86) 388,716 (47,646) 16:finished LZMA decompress (ignore for x86) 406,167 (17,450) LZ4 size: fsps_lz4.bin 0x242dc0 fsp 147442 LZ4 (188416 decompressed) LZ4 decompression time: 17:starting LZ4 decompress (ignore for x86) 384,736 (47,864) 18:finished LZ4 decompress (ignore for x86) 384,796 (59) Change-Id: Idace01227cfd2312b2c4c4ea1e6aaac8c21cd6b0 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-03soc/intel/alderlake: Log internal device wake eventsTim Wawrzynczak
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI, south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-03soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devicesTim Wawrzynczak
Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47413 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03soc/intel/alderlake: Add PCIe root port wake sources to elogTim Wawrzynczak
Log PCIe root port wake events in the elog. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-03sb/intel/lynxpoint/lpc.c: Relocate lock bit writeAngel Pons
This lock bit can be set later, and should also be set for LynxPoint-H. This eases merging with Broadwell, which already sets this lock bit after `spi_finalize_ops()` in a dedicated finalisation function. Tested on Asrock B85M Pro4 (LynxPoint-H), the lock bit is now set. Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47036 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03AGESA boards: Captilize ASL namesPaul Menzel
ASL+ Optimizing Compiler/Disassembler version 20200925 remarks: IASL build/dsdt.aml Intel ACPI Component Architecture ASL+ Optimizing Compiler/Disassembler version 20200925 Copyright (c) 2000 - 2020 Intel Corporation dsdt.asl 222: Name(PSa, Package(){ Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (PSA_) dsdt.asl 228: Name(APSa, Package(){ Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (APSA) Execute the command below to fix all occurences: git grep -l PSa | xargs sed -i 's/PSa/PSA/g' Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03configs/config.google_volteer.build_test_purposes: Add fileAngel Pons
This is meant to build-test Crashlog and various debug options. Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com>
2021-03-03soc/intel/tigerlake: Re-use existing define in CrashLog implementationFrancois Toguo
TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS. This fix re-uses an already existing variable in crashLog. BUG=None TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin. Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/purism/librem_mini: Implement `die_notify`Angel Pons
Make the SATA LED blink when coreboot dies. GPIO functions aren't compiled in for postcar, so add a check to prevent linker failures. TEST: Try to boot Librem Mini WHL without RAM, observe blinking (and also blinding LED). Re-install RAM (and re-seat RAM a few times), boot to OS, and observe SATA LED operating normally, as expected. Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50013 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03mb/*/*: Don't select PCIEXP_HOTPLUGArthur Heymans
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced. Just change the default value to 'y'. Change-Id: Ie4248700f5ab5168bff551b740d347713273763c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03soc/intel: Backport SMRR locking supportAngel Pons
Backport commit 0cded1f116 (soc/intel/tigerlake: Add SMRR Locking support) to other client platforms. The SMRR MSRs are core-scoped on Skylake and Ice Lake, at least. Older platforms do not support SMRR locking, but now there's seven copies of the same file in the tree. A follow-up will deduplicate smmrelocate.c files into common CPU code. I cannot test Jasper Lake nor Elkhart Lake, but they should still work. As per documentation I do not have access to, Elkhart Lake seems to support SMRR locking. However, Jasper Lake documentation is unclear. Tested on Purism Librem Mini v1 (WHL-U i7-8565U), still boots and SMRR MSRs have the same value on all cores/threads (i7-8565U supports HT). Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-03mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG deviceArthur Heymans
Pineview does not support PEG. Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03mb/intel/d510mo/devicetree.cb: Indent with tabsArthur Heymans
This is a cosmetic change. Make the formatting consistent with the rest of the tree. Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03mb/gigabyte: Add GA-D510UDAngel Pons
Booted fine on the first try. Most things work properly, but I haven't tested them thoroughly. Native raminit chokes with a DIMM in the second slot, but the first slot works properly. Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-03lib/cbfs.c: Fix return value of failure to measureArthur Heymans
Returning an error on a failure to measure makes the system not bootable. Change-Id: Ifd20e543d3b30de045c0656eccdcc494c2fb10ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-03-03mb/google/dedede/var/drawcia: Re-tune override GPIO tableKarthikeyan Ramasubramanian
There is going to be an upcoming board version for Drawlat/man and Drawcia. Hence apply the override GPIO table without pad termination for board versions 6 or 8 alone. BUG=None BRANCH=dedede TEST=Build and boot to OS in Drawcia. Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-03mb/google/guybrush: Add SPDs to build for Guybrush variantMartin Roth
These files were automatically generated by the lpddr4 version of gen_part_id.go. BUG=b:178715165 TEST=Build Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3797ba6d52248961418000614a4f7885182521a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03mb/google/guybrush: Add generated LPDDR4x SPDsMartin Roth
These SPDs were generated by the lpddr4 version of gen_spd.go from the global_lp4x_mem_parts.json.txt file. BUG=b:178715165 TEST=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03util/spd_tools/lp4x: Add 2 new parts to global memory definitionMartin Roth
This adds the definitions for MT53E1G32D4NQ-046 WT:E used on Majolica, and the NT6AP256T32AV-J1 part used on Guybrush. BUG=b:178715165 TEST=Generate SPDs Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-06 15:23:01 +0000