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2021-04-20soc/intel/skylake: Move `SataTestMode` to KconfigAngel Pons
This option is not mainboard-specific, and should be user-visible. Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-20soc/amd/{common,cezanne}: Add uPEP deviceRaul E Rangel
The uPEP device is required to support S0i3. The device has been written in ASL to make it easier to read and maintain. The device constraints are purely informational. We use a dummy constraint like the Intel platforms to keep both linux and Windows functional. In order for this device to be used by the linux kernel the ACPI_FADT_LOW_PWR_IDLE_S0 flag must be set. So including it unconditionally doesn't cause any problems. The AMD Modern Standby BIOS Implementation Guide defines two UUIDs, one for getting the device constraints, and one for handling notifications. This differs from the Intel specification and the linux driver implementation. For this reason I haven't implemented any of the notification callbacks yet. BUG=b:178728116 TEST=Boot OS and verify _DSM is called: [ 0.226701] lps0_device_attach: ACPI: \_SB_.PEP_: _DSM function mask: 0x3 [ 0.226722] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: _DSM function 1 eval successful [ 0.226723] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list begin: [ 0.226724] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list end Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2deef47eabe702efe1a0f3747c9f27bcec37464b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52445 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19device/azalia_device.c: Add option to lock down GCAPAngel Pons
On Intel 6-series PCHs, the GCAP register is R/WO (Read / Write Once), and needs to be written to after the HD Audio controller is taken out of reset. Add a Kconfig option to read and write back GCAP in order to lock it down. Follow-up commits will select this option when switching platforms to use common Azalia code, to preserve original behaviour. Change-Id: I70bab20816fb6c0bf7bff35c3d2f5828cd96172d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-19soc/intel/common/block/smm: Drop stale commentAngel Pons
This comment is most likely a copy-paste leftover from Braswell. Change-Id: I49bfa3cc56539df0b47d2e2bd74b2bfc45421034 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19mb/clevo/cml-u/Kconfig: Use BOARD_CLEVO_L140CU_BASEFelix Singer
To make the L140CU able to be selected by other OEMs, use BOARD_CLEVO_L140CU_BASE for OEM independent options. BOARD_CLEVO_L140CU represents the standard Clevo mainboard without any OEM modifications, while BOARD_CLEVO_L140CU_BASE is used for the baseboard. Change-Id: Iee82eadebfc851619dbb64de09283c5ee55a499f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52241 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19mb/amd/majolica: use GPIO_40 as reset pin for NVME SSDNikolai Vyssotski
Default Majolica configuration uses GPIO_40 for NVME M2_SSD_RST# BUG=b:182100027 TEST=ls /dev/nvme* Change-Id: Idecc0ec7eaf903b29fea109d3688f3c249da62f5 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-19lib/rtc: Fix incomplete leap year macroJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Found-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: Ic434c969141c67ce317a5db0c8805de02c84eb08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-19sb/intel/common: Drop some PCH_LPC_DEV macrosAngel Pons
The macro definitions depend on __SIMPLE_DEVICE__ and are only used in the get_gpio_base() or lpc_get_pmbase() functions, which already guard PCH_LPC_DEV usage using __SIMPLE_DEVICE__ in preprocessor. Change-Id: I5d3681debe29471dfa143ba100eb9060f6364c93 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19soc/intel/baytrail/pmutil.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I0d5fa4451b356970cf9843a76d0fa4d2af4307da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19soc/intel/braswell/pmutil.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I2caa9cbb812e17f041c15654aef756e41fb71398 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19soc/intel/common/block/pcr: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I06f9c623947e48a7213e42507f4da51c12b425d7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19soc/intel/cannonlake/elog.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Ie2f02b9934d843c29d17a72a6bf3b2bae91ce8d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19soc/intel/braswell/smbus.c: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: Ic16fd74d4ddf96e29bcdada671dab0e590af74ef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19mb/clevo/cml-u: Rename `BOARD_CLEVO_L140CU_OPTIONS`Felix Singer
Rename `BOARD_CLEVO_L140CU_OPTIONS` to `BOARD_CLEVO_L140CU_BASE` to make clear that this option represents the baseboard. Change-Id: I76690626fddafc8e3c37ef760aeb4f064fb6b591 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52480 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19mb/clevo/kbl-u: Move memory init config to variant levelFelix Singer
Memory init config is board specific. Thus, move it to variant level and hook up variant romstage.c. Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19mb/clevo/kbl-u: Clean up codeFelix Singer
Change-Id: I98d806ebf126522689b2c101b75add733825fcf1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19mb/clevo/l140cu: Move FSP-M config hook to mainboard levelFelix Singer
Hook up FSP-M configuration on mainboard level instead of variant level being able to do common configuration there. Also, hook up variant romstage.c on mainboard level for variant specific configurations. Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19soc/intel/common/block/smbus: Define __SIMPLE_DEVICE__Angel Pons
Change-Id: I93f7918763d87f8fb50f39f9469694e73aeff37b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19drivers/intel/mipi_camera: Adding support for low power camera probeSugnan Prabhu S
Add a new configuration low_power_probe to avoid camera privacy LED blink during the boot. Change-Id: I27d5c66fb380ae6cd76d04ee82b7736407dac1b0 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52189 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19mainboard/ocp/tiogapass: Remove redundant PARALLEL_MP_AP_WORKMarc Jones
PARALLEL_MP_AP_WORK is set in the xeon_sp Kconfig. No need to set it here. Change-Id: I66d59fd7cbc3617eb739fdf2f3750f20ee701fbd Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19cpu/x86/smm/smm_module_loaderv2.c: Rename fileArthur Heymans
As v1 was dropped, rename v2. Change-Id: I4dd51804e9391284c7624c42ad8180a14b1a4c84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19cpu/x86/smm: Drop the V1 smmloaderArthur Heymans
Change-Id: I536a104428ae86e82977f2510b9e76715398b442 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19cpu/x86/smm_loaderv2: Use the permanent stack top during relocationArthur Heymans
Use the same stack location during relocation as for the permanent handler. When the number of CPUs is too large the stacks during relocation don't fit inside the default SMRAM segment at 0x30000. Currently the code would just let the CPU stack base grow downwards outside of the default SMM segment which would corrupt lower memory if S3 is implemented. Also update the comment on smm_module_setup_stub(). Change-Id: I6a0a890e8b1c2408301564c22772032cfee4d296 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19Revert "mb/google/mancomb: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 800193414148d5f39be42110fc2c76ad1ceb7d2f. EC software sync needs to be enabled in payload once the EFS2 requirements are met. BUG=b:185277224 TEST=Build. Cq-Depend: chromium:2829948 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ib22a89e221e1e057d82ef76b7008e5d3f14df5e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52451 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19Revert "soc/amd/cezanne: Add support to perform early EC sync"Karthikeyan Ramasubramanian
This reverts commit ad7c33abd21dfdde75c6ffa23c31cbe46826d2d5. With EFS2 already enabled in EC, enabling early EC sync is not required. Also a workaround has been added in payload to address any boot issues. BUG=b:185277224 TEST=Build and boot to OS in Guybrush in both normal and recovery mode. Cq-Depend: chromium:2832032 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I34f8433739754365c8e5a10fdf7e58e3d1e7e797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52419 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19Revert "mb/google/guybrush: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2 already enabled in EC, enabling early EC sync is not required. Also a workaround has been added in payload to address any boot issues. BUG=b:185277224 TEST=Build and boot to OS in Guybrush in both normal and recovery mode. Cq-Depend: chromium:2832032 Change-Id: I921dc5c814e5187dce283eeff43075b59885723a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18libpayload/keyboard: Reset to scancode set #2 on exitNico Huber
If we select scancode set #1 and keep that, it can confuse Linux with keyboards that don't return to set #2 when asked to load the defaults. This happens for instance with various integrated Think- Pad keyboards but was also seen with an external PS/2 one. The chosen configuration, scancode set #2 without translation, seems to be the default for many systems. So we can expect other payloads and kernels to work with it. Change-Id: I28d74590e9f04d32bb2bbd461b67f15014f927ec Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18libpayload/keyboard: Add a detention stateNico Huber
Instead of ignoring keyboards indefinitely when they failed to initialize, we wait 5s and then start over with the hotplug detection. As we always assume a present keyboard at first, we'd otherwise never have a chance to hot plug a device after the initial 30s timer ran out. Change-Id: I8dec4921b2e932442d52b5118cdcf27090633498 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18libpayload/keyboard: Implement hot (un)pluggingNico Huber
While we assume a keyboard is attached, we send an echo command every 500ms. If there is no data coming from the keyboard within 200ms, we assume it was detached. Correspondingly, if we assume no keyboard is attached, we run an echo command once per second. Change-Id: I2c75182761729bf30711305f3d8b9d43eafad675 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18tests: Add lib/coreboot_table-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I4d7d9ca43316bf514bb5ebd8909f441bcfa20eba Reviewed-on: https://review.coreboot.org/c/coreboot/+/52159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-04-18mb/google/hatch: Guard ChromeOS fmd selection on CHROMEOSMatt DeVillier
Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS is selected, so non-ChromeOS targets use the default x86 FMAP. Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18mb/google/mancomb: Remove PS/2 mouse configEric Lai
Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I02b375b6fc134e56b7f55e1421f694daa4aa994d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52407 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add GPIO override tableKarthikeyan Ramasubramanian
EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has a voltage rating of 3.3 V. The schematics has been updated to bridge the gap. So enable the speaker amplifier by default and add a gpio override table to disable the speakers before board version 2. Also update the codec ACPI HID name for the kernel machine driver to probe the codec successfully. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state is high. Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush: Enable AMD I2S Machine DriverKarthikeyan Ramasubramanian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for machine driver is populated. Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18drivers/amd/i2s_machine_dev: Make DMIC select gpio optionalKarthikeyan Ramasubramanian
The selector component in Sound Open Firmware (SOF) can consume all the mics and use the configuration in the Use Case Manager (UCM) to select the right channel. Hence dmic select gpio configuration is optional. BUG=b:182960979 TEST=Build and boot to OS in Guybrush. Ensure that the machine driver ACPI object is populated without DMIC select GPIO. Change-Id: Iba00b07c3656c487e33bab184fefee7037745e2d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52393 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18soc/amd/cezanne/Kconfig: add missing ACPI_BERT and ACPI_BERT_SIZEFelix Held
ACPI_BERT_SIZE is used in the FSP driver and the fsp_m_params.c. The latter one is planned to be deprecated though. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id1a250defbd31e255df9b7a7dd8488dc3182649b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-18soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`Furquan Shaikh
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is done") introduced a workaround in coreboot for `soc/intel/cannonlake` platforms to save and restore GPIO configuration performed by mainboard across call to FSP Silicon Init (FSP-S). This workaround was required because FSP-S was configuring GPIOs differently than mainboard resulting in boot and runtime issues because of misconfigured GPIOs. This issue has since been fixed in FSP (verified with FSP v1263 on hatch). However, there were still 4 boards in coreboot using `cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u and system76/lemp9 were tested to ensure that this workaround is no longer required. This change drops the workaround using `cnl_configure_pads()` and updates all mainboards to use `gpio_configure_pads()` instead. Signed-off-by: Furquan Shaikh <furquan@google.com> Tested-by: Angel Pons <th3fanbus@gmail.com> (Tested purism/librem_cnl) Tested-by: Michael Niewöhner <foss@mniewoehner.de> (Tested clevo/cml-u which is similar to system76/lemp9) Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/purism/librem_14: Update GPIO configMatt DeVillier
Update GPIO config based on review of latest schematics: - LAN/WLAN reset lines are NC - SDIO lines configured via GPP_G0-G7 - DMIC lines are wired directly to codec, not PCH, so GPP_D17-20 are set to NC - Pads GPP_H0-H3 are configured for I2S2 - Pads GPP_H7-H9 are straps for board revision, so treated as GPI - CPU_C10_GATE# is NC - PWRBTN# does not need an internal pull-up - GPP_C20-23 are configured for M.2 UART - SATAXPCIE1/2 and EC SCI/SMI lines do not need internal pull ups - GPP_C6/C7 set to I2C1 for future use - GPP_E15 changed from SCI to SMI, edge triggered Change-Id: If113cfeadf093e10dd84ab827ead594088f02ba1 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52389 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/purism/librem_14: Remove all PU/PD from NC GPIO padsMatt DeVillier
When a pad is configured as NC, it is set as a GPI with both TX and RX disabled, and as the pad is internally disconnected, no pull up or pull down is needed. Change-Id: Id551b8f6f5b8c772e17670b8b728b5e890ef0b21 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52388 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add FPMCU configrationIvy Jian
Enable CRFP in devicetree and configure GPIOs. BUG=b:182201937 BRANCH=None TEST=Boot into OS and confirm FPMCU is responding. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18src/drivers/ipmi: Add DEBUG_IPMI optionMarc Jones
IPMI debug was extra spewy, so add a debug option as SPI and other drivers have when they need to be debugged. Change-Id: I788d67c242cac23bde9750aa3e95e3276c3f1fd7 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18device/Kconfig: Adapt PCIEXP_HOTPLUG_BUSESNico Huber
The default of 32 buses per hotplug bridge is rather high. Especially for platforms that limit MMConf space to 64 buses: they run out of numbers if there is more than a single hotplug bridge. Lower the default to * 8 if MMConf is limited to 64 or less buses, * 16 if MMConf is limited to 128 or less buses. Change-Id: I06d522dd92ceea9f4798273b26f947a5333800c3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52069 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18util/kconfig_lint: Update handle_expressions()Nico Huber
More relational operators were added to Kconfig in 2015. Now we can make use of them. Change-Id: I640e5c3ee1485348f09fcb0b0d5035eb53a2c98e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18util/kconfig_lint: Turn handle_expressions() into a parserNico Huber
I wished there was a way to do this in smaller steps, but with every line fixed an error somewhere else became visible. Here is a (probably incomplete) list of the issues: * Only one set of parentheses was supported. This is a hard to solve problem without a real parser (one solution is to use an recursive RE, see below). * The precedence order was wrong. Might have been adapted just to give a positive result for the arbitrary state of the tree. * Numbered match variables (e.g. $1, $2, etc.) are not local. Calling handle_expressions() recursively once with $1, then with $2, resulted in using the final $2 after the first recursive call (garbage, practically). Also, symbol and expression parsing was mixed, making things harder to follow. To remedy the issues: * Split handle_symbol() out. It is called with whitespace stripped, to keep the uglier REs in handle_expressions(). * Match balanced parentheses and quotes when splitting expressions. In this recursive RE /(\((?:[^\(\)]++|(?-1))*\))/ the `(?-1)` references the outer-most group, thus the whole expression itself. So it matches a pair of parentheses with a mix of non-parentheses and the recursive rule itself inside. This allows us to: * Order the expression matches according to their precedence rules. Now we can match `<expr> '||' <expr>` first as we should and everything else falls into its place. * Remove the bail-out that silenced the undefined behavior. Change-Id: Ibc1be79adc07792f0721f0dc08b50422b6da88a9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18soc/intel/xeon_sp: Set SATA REGLOCKsMarc Jones
Set the SATA and SSATA REGLOCK as indicated by the Intel documentation. Change-Id: I90e6d0e3b5a38bcd5392e26cbbb6dc4aa6a8304b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18mainboard/ocp/deltalake: Add SATA device to device treeMarc Jones
Add the SATA device to the device tree so it may be found when trying to write SATA registers. Otherwise, it fails on "requests hidden 00:17.0 PCI: dev is NULL!" Change-Id: Ia309805ffd6e97d04b5cf4a0344eaac4c4d0adb6 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18soc/intel/xeon_sp: Set MSR locksMarc Jones
Set MSR locks as indicated by the Intel documents. The following MSRs settings are locked: MSR_FEATURE_CONFIG AES enable/disable lock TURBO_ACTIVATION_RATIO_LOCK This also adds PARALLEL_MP_AP_WORK to enable running on APs to set each CPU MSR. Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18Revert "drivers/spi: Stop using a variable-length array"Angel Pons
This reverts commit 59626b8670da326ab725e67b01dd1025b0a34a86. Reason for revert: Reported to cause boot-loops. Reason unknown. Change-Id: Id7f6211aaaf0401017176f63a17763f28d2744c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52424 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-17mb/prodrive/hermes: Fix SSDT MPTSPatrick Rudolph
MPTS is currently not executed by the AML interpreter. Use Method (\\_SB.MPTS) instead of Scope (\\_SB) Method (MPTS) ScopeEnd Tested on Prodrive Hermes. MPTS is now executed at S5. Change-Id: I9074eb4ba55aab3f9a47ae5e3c3ddd338406a5e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
2021-04-16psp_verstage: move svc to platform-specific dirKangheui Won
Since there are some differences between picasso PSP svc and cezanne PSP svc, each platform should have their own svc wrapper. Moreover cezanne PSP will drop unused parameters from update_psp_bios_dir and save_uapp_data so make wrapper around it. BUG=b:182477057 BRANCH=none TEST=build psp_verstage and boot on zork Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I69f998865fc3184ea8900a431924a315c5ee9133 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52307 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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