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2016-08-24soc/intel/apollolake: Add ASL methods for eMMCVaibhav Shankar
Implement PS0 and PS3 methods to support eMMC power gate in S0ix suspend and resume. BUG=chrome-os-partner:53876 TEST=Suspend and Resume using 'echo freeze > /sys/power/state'. System should resume from S0ix. Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16233 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-24vboot/vbnv_flash: fix return value check for rdev_writeat()Aaron Durbin
The return value check was incorect and checking for failure in the success path. Fix the return value check so that it actually checks for success. BUG=chrome-os-partner:56151 Change-Id: Ie7960b89a916dec261015c97c3e0552be56b5b5d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16303 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-24vboot/vboot_common: actually provide a writable region_deviceAaron Durbin
vboot_named_region_device_rw() is supposed to provide a writable region_device. However, it was calling fmap_locate_area_as_rdev() which only provides a read-only one. Fix this. BUG=chrome-os-partner:56151 Change-Id: I6279fde32132b1b6138292c3ef771c59709e00c6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16302 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-23arch/riscv: Add functions to read/write memory on behalf of supervisor/user modeJonathan Neuschäfer
Normally machine-mode code operates completely within physical address space. When emulating less privileged memory accesses (e.g. when the hardware doesn't support unaligned read/write), it is useful to access memory through the MMU (and with virtual addresses); this patch implements this functionality using the MPRV bit. Change-Id: Ic3b3301f348769faf3ee3ef2a78935dfbcbd15fd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16260 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23arch/riscv: Map the kernel space into RAM (2GiB+)Jonathan Neuschäfer
Change-Id: I273e9d20e02f0333f28e0fc2adcc7940578ea93e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16263 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23arch/riscv: Implement the SBI againJonathan Neuschäfer
Not all SBI calls are implemented, but it's enough to see a couple dozen lines of Linux boot output. It should also be noted that the SBI is still in flux: https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OFKM Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16119 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23arch/riscv: Enable U-mode/S-mode counters (stime, etc.)Jonathan Neuschäfer
Change-Id: Ie62f60b2e237fa4921384e3894569ae29639f563 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16262 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23arch/riscv: Fix unaligned memory access emulationJonathan Neuschäfer
Change-Id: I06c6493355f25f3780f75e345c517b434912696f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16261 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23memlayout: Ensure TIMESTAMP() region is big enough to avoid BUG()Julius Werner
The timestamp code asserts that the _timestamp region (allocated in memlayout for pre-RAM stages) is large enough for the assumptions it makes. This is good, except that we often initialize timestamps extremely early in the bootblock, even before console output. Debugging a BUG() that hits before console_init() is no fun. This patch adds a link-time assertion for the size of the _timestamp region in memlayout to prevent people from accidentally running into this issue. Change-Id: Ibe4301fb89c47fde28e883fd11647d6b62a66fb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16270 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-08-23arch/riscv: Delegate exceptions to supervisor mode if appropriateJonathan Neuschäfer
Change-Id: I1c8127412af0f9acc5b5520dc324ac145e59a4bd Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16160 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23arch/riscv: Print the page table structure after constructionJonathan Neuschäfer
A new Kconfig option, DEBUG_PRINT_PAGE_TABLES, is added to control this behaviour. It is currently only available on RISC-V, but other architectures can use it, too, should the need arise. Change-Id: I52a863d8bc814ab3ed3a1f141d0a77edc6e4044d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16015 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23src/mainboard: Remove unnecessary whitespace before "\n"Elyes HAOUAS
Change-Id: I9789b0b3339435fbe30c69221826bf23c9b3c77b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16283 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23arch/arm & arm64: Remove unnecessary whitespace before "\n"Elyes HAOUAS
Change-Id: Ibec78b25c0f330fc8517654761803e8abf203060 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16282 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23src/southbridge: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
Change-Id: I42cc5b8736e73728c5deec6349e8d2a814e19e83 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16281 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Omar Pakker
2016-08-23src/cpu: Capitalize CPU, APIC and IOAPIC typo fixElyes HAOUAS
Change-Id: I82e0736dc6b44cfcc57cdfdc786c85c4b6882260 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16276 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-23src/northbridge: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
Change-Id: I6a533667c7c8ff5ec6ab9d4e1cfc51e993a90084 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16280 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-23src/include: Capitalize APIC and SMMElyes HAOUAS
Change-Id: I9b3a2cce6c6bb85791d5cde076d5de95ef0e8790 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16278 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-23emulation/qemu-i440fx: add cmos.default fileAntonello Dettori
Add cmos.default file in order to ease future testing and debugging of cmos related code. Change-Id: I7c6a0aa4e38bb08a520e4838fa216c81b50f2917 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16247 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23soc/intel/apollolake: Use CONFIG_NHLT_DMIC_2CH_16B for dmicSaurabh Satija
Update the config variable that gets set to use DMIC 2 channel blob for intel/apollolake platforms. This flag is set in mainboard. Change-Id: Ic6deb9f08d345cc45351d61a7597bc7075ee20f9 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/16251 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-23nvramcui: refactor codeAntonello Dettori
Split the main() into a couple of smaller functions in order to more easily extend the payload. Change-Id: I4c2b144e2a28c6f15e360d55c49974675e6a80d2 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16248 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-23drivers/spi: be sure to call spi_init() before spi_flash_probe()Aaron Durbin
It's necessary to call spi_init() prior to calling spi_flash_probe() such that the SPI drivers can do any work required prior to performing SPI transactions. It could be argued that the drivers should handle such situations, however the SPI API implementations seem to assume the callers ensured spi_init() was called before any SPI transactions. This fixes systems that failed to boot introduced by [1]. Issue tracked in https://ticket.coreboot.org/issues/67. [1] I2aa75f88409309e3f9b9bd79b52d27c0061139c8 https://review.coreboot.org/16200 BUG=chrome-os-partner:56151 Change-Id: I2d8d5ac685833521f1efe212b07a4b61ba0d9bc3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16297 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-08-22mb/asus/kgpe-d16: Add TPM supportTimothy Pearson
The ASUS KGPE-D16 accepts an optional Infineon LPC TPM module. Expose the TPM LPC device to the host operating system. Change-Id: If500e9162bf1e233ccaa35db79452daa59a34f2f Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16269 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-22util/scripts: Support cygwin in ucode conversion toolMarshall Dawson
Check for the existence of TMPFILE with a .exe extension and if found rename it with no extension. This allows the program to be run and removed properly. Change-Id: I26928f9b8bf82d1c07fa456a88d624f7a8838bd3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/15437 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-21mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cbTimothy Pearson
Change-Id: I49925040d951dffb9c11425334674d8d498821f0 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16268 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-213rdparty/blobs: Update to get AGESA binary for pcengines/apu2Martin Roth
The AGESA binary for PC Engines' APU2 board was just added to the blobs directory. Update the submodule pointer to allow access. Change-Id: Ic2995f253d12d17e229526cb71dea5bf65fa36f9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16253 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-08-20intel/skylake: Do not halt in poweroff if in SMMFurquan Shaikh
Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered preventing the system from entering sleep state. Fix this by calling halt only if ENV_SMM is not true. BUG=chrome-os-partner:56395 Change-Id: I3addc1ea065346fbc5dbec9d1ad49bbd0ae05696 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16259 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-20google/chromeec: Ensure data is ready before reading itFurquan Shaikh
Before reading the data provided by EC to the host, ensure that data ready flag is set. Otherwise, it could result in reading stale/incorrect data from the data buffer. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified that lidclose event is read correctly by host on reef. Change-Id: I88e345d64256af8325b3dbf670467d09f09420f0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16258 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-20intel/apollolake: Do not halt in poweroff if in SMMFurquan Shaikh
Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered preventing the system from entering sleep state. Fix this by calling halt only if ENV_SMM is not true. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified lidclose behavior on reef. Change-Id: If116c8f4e867543abdc2ff235457c167b5073767 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16257 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-20intel/apollolake: Fix typo in gpi_status_getFurquan Shaikh
sts_index is calculated incorrectly because of wrong use of parenthesis. This lead to wrong bit being checked for EC_SMI_GPI on reef and lidclose event was missed. BUG=chrome-os-partner:56395 BRANCH=None TEST=Verified that lidclose event is seen and handled by SMM in coreboot on reef. Change-Id: I56be4aaf30e2d6712fc597b941206ca59ffaa915 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16256 Tested-by: build bot (Jenkins) Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-20google/reef: Save DIMM info from SMBIOS memory HOBRavi Sarawadi
Add support for SMBIOS memory HOB save. Add DIMM 'part_num' info to be saved as part of SMBIOS memory HOB. BUG=chrome-os-partner:55505 TEST='dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: I53b4a578f31c93b8921dea373842b8d998127508 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-20soc/intel/apollolake: Save DIMM info from SMBIOS memory HOBRavi Sarawadi
Read FSP produced memory HOB and use it to populate DIMM info. DIMM 'part_num' info is stored statically based on memory/SKU id. BUG=chrome-os-partner:55505 TEST='dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: Ifcbb3329fd4414bba90eb584e065b1cb7f120e73 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-20drivers/intel/fsp2_0: Add SMBIOS memory HOB supportRavi Sarawadi
Add SMBIOS memory GUID and functions to retrieve HOB. BUG=chrome-os-partner:55505 TEST='dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: Ie7e2239bb691c748d9fd852c3dc8cdc05243b164 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-19rockchip/rk3399 & gru/kevin: support sdram 933MHz on kevinLin Huang
We should be running faster. Faster = better. BRANCH=None BUG=chrome-os-partner:54873 TEST=Boot; stressapptest -M 1028 -s 10000 Change-Id: I7f855960af3142efb71cf9c15edd1da66084e9d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 51bfd2abb1aba839bd0b5b85e9e918f3cc4fd94d Original-Change-Id: Iec9343763c1a5a5344959b6e8c4dee8079cf8a20 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/362822 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19vboot/vbnv_flash: make I/O connection agnosticAaron Durbin
There's no need to be SPI specific w.r.t. how the flash is connected. Therefore, use the RW boot device to write the contents of VBNV. The erasable check was dropped because that information isn't available. All regions should be aligned accordingly on the platform for the underlying hardware implementation. And once the VBNV region fills the erase will fail. BUG=chrome-os-partner:56151 Change-Id: I07fdc8613e0b3884e132a2f158ffeabeaa6da6ce Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16206 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19vboot: provide RW region device supportAaron Durbin
Explicitly provide a RW view of an vboot FMAP region. This is required for platforms which have separate implementations of a RO boot device and a RW boot device. BUG=chrome-os-partner:56151 Change-Id: If8bf2e1c7ca9bff536fc5c578fe0cf92ccbd2ebc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16205 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-08-19drivers/elog: use region_device for NV storageAaron Durbin
Instead of assuming SPI backing use a region_device to abstract away the underlying storage mechanism. BUG=chrome-os-partner:55932 Change-Id: I6b0f5a7e9bea8833fb1bca87e02abefab63acec3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16204 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19lib/fmap: provide RW region device supportAaron Durbin
Explicitly provide a RW view of an FMAP region. This is required for platforms which have separate implementations of a RO boot device and a RW boot device. BUG=chrome-os-partner:56151 Change-Id: Ibafa3dc534f53a3d90487f3190c0f8a2e82858c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16203 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19soc/intel/skylake: use SPI flash boot_device_rw() for ealy stagesAaron Durbin
If the boot device is SPI flash use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system. BUG=chrome-os-partner:56151 Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16202 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19soc/intel/apollolake: use SPI flash boot_device_rw() for ealy stagesAaron Durbin
If the boot device is SPI flash use the common one in the early stages. While tweaking the config don't auto select SPI_FLASH as that is handled automatically by the rest of the build system. BUG=chrome-os-partner:56151 Change-Id: If5e3d06008d5529dd6d7c05d374a81ba172d58fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16201 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19drivers/spi: provide optional implementation of boot_device_rw()Aaron Durbin
On many x86 platforms the boot device is SPI which is memory mapped. However, in order to write to the boot device one needs to use the SPI api. Therefore, provide a common implementation of boot_device_rw() which has no mmap() functionality. It only reads, writes, and erases. This will be used in the existing infrastructure but in a SPI agnostic way. Two options are added: 1. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP 2. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY The former is auto-selected when COMMON_CBFS_SPI_WRAPPER is not selected. The latter can be used to include the implementation in the early stages such as bootblock, verstage, and romstage. BUG=chrome-os-partner:56151 Change-Id: I2aa75f88409309e3f9b9bd79b52d27c0061139c8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16200 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19drivers/spi: include SPI flash modules for all stagesAaron Durbin
It shouldn't matter if COMMON_CBFS_SPI_WRAPPER is selected to include the SPI flash support in all stages. Therefore, include the SPI flash support files in all the stages. While there include the same set of files for all stages. They were out of sync for some reason. BUG=chrome-os-partner:56151 Change-Id: I933335104203315cbbcf965185a7c176974e6356 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16198 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19drivers/spi: ensure SPI flash is boot device for coreboot tablesAaron Durbin
The spi_flash_probe() routine was setting a global varible unconditonally regardless if the probe was for the boot device or even if the boot devcie was flash. Moreover, there's no need to report the SPI information if the boot device isn't even SPI. Lastly, it's possible that the boot device is a SPI flash, but the platform may never probe (selecting SPI_FLASH) for the actual device connected. In that situation don't fill anything in as no correct information is known. BUG=chrome-os-partner:56151 Change-Id: Ib0eba601df4d77bede313c358c92b0536355bbd0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16197 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19util/lint: Add a tool to verify a single newline at the end of filesMartin Roth
This takes way too long to run - currently about 30 seconds to look at the entire coreboot tree. Change-Id: I403934014b422528715ea95ff652babe5e18c88b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15976 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-19qemu-riscv: Remove obsolete CSR - send_ipiMartin Roth
This aligns the code in qemu-riscv with the code in spike-riscv. The previous code gives an error in the updated toolchain as the send_ipi CSR is no longer valid. This gave the build error: src/mainboard/emulation/qemu-riscv/qemu_util.c:64: Error: Instruction csrw requires absolute expression Change-Id: Iac0f66e8e9935f45c8094d5e16bedb7ac5225424 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16244 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-08-19soc/intel/skylake: make SPI support early stagesAaron Durbin
Using malloc() in SPI code is unnecessary as there's only one SPI device that the SoC support code handles: boot device. Therefore, use CAR to for the storage to work around the current limiations of the SPI API which expects one to return pointers to objects that are writable. Additionally, include the SPI support code as well as its dependencies in all the stages. BUG=chrome-os-partner:56151 Change-Id: I0192ab59f3555deaf6a6878cc31c059c5c2b7d3f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16196 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-08-19soc/intel/apollolake: make SPI support early stagesAaron Durbin
Using malloc() in SPI code is unnecessary as there's only one SPI device that the SoC support code handles: boot device. Therefore, use CAR to for the storage to work around the current limiations of the SPI API which expects one to return pointers to objects that are writable. BUG=chrome-os-partner:56151 Change-Id: If4f5484e27d68b2dd1b17a281cf0b760086850a7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16195 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19lib/cbfs_spi: provide boot_device_rw() supportAaron Durbin
Provide the RW boot device operations for the common cbfs SPI wrapper. The RW region_device is the same as the read-only one. As noted in the boot_device_rw() introduction patch the mmap() support should not be used in conjuction with writing as that results in incoherent operations. That's fine as the current mmap() support is only used in the cbfs layer which does not support writing, i.e. no cbfs regions would be written to with any previous or outstanding mmap() calls. BUG=chrome-os-partner:56151 Change-Id: I7cc7309a68ad23b30208ac961b1999a79626b307 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16199 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19lib/boot_device: add RW boot device constructAaron Durbin
The current boot device usage assumes read-only semantics to the boot device. Any time someone wants to write to the boot device a device-specific API is invoked such as SPI flash. Instead, provide a mechanism to retrieve an object that can be used to perform writes to the boot device. On systems where the implementations are symmetric these devices can be treated one-in-the-same. However, for x86 systems with memory mapped SPI the read-only boot device provides different operations. BUG=chrome-os-partner:55932 Change-Id: I0af324824f9e1a8e897c2453c36e865b59c4e004 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16194 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-19Kconfig: introduce writable boot device notionAaron Durbin
Indicate to the build system that a platform provides support for a writable boot device. The following will provide the necessary support: COMMON_CBFS_SPI_WRAPPER users soc/intel/apollolake soc/intel/baytrail soc/intel/braswell soc/intel/broadwell soc/intel/skylake The SPI_FLASH option is auto-selected if the platform provides write supoprt for the boot device and SPI flash is the boot device. Other platforms may provide similar support, but they do that in a device specific manner such as selecting SPI_FLASH explicitly. This provides clearance against build failures where chipsets don't provide SPI API implementations even though the platform may use a SPI flash to boot. BUG=chrome-os-partner:56151 Change-Id: If78160f231c8312a313f9b9753607d044345d274 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16211 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-19drivers/spi: move cbfs_spi.c locationAaron Durbin
The common boot device spi implementation is very much specific to SPI flash. As such it should be moved into that subdirectory. It's still a high-level option but it correctly depends on BOOT_DEVICE_SPI_FLASH. Additionally that allows the auto-selection of SPI_FLASH by a platform selecting COMMON_CBFS_SPI_WRAPPER which allows for culling of SPI_FLASH selections everywhere. BUG=chrome-os-partner:56151 Change-Id: Ia2ccfdc9e1a4348cd91b381f9712d8853b7d2a79 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16212 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
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