summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2017-09-20vboot: remove init_vbnv_cmos()Aaron Durbin
Instead of having each potential caller deal with the differences of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the correct logic within the callee, cmos_init(), for handling the vbnv in CMOS. The internal __cmos_init() routine returns when the CMOS area was cleared. BUG=b:63054105 Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20google/kahlee: Prevent AGESA memory clearMarc Jones
The Linux Pstore area must not be cleared on a reboot. Set the option to not clear the memory in AGESA. BUG=b:64193190 BRANCH=none TEST=Memory clear isn't called in AGESA. Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21596 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20google/kahee: Fix number of memory channelsMarc Jones
Kahlee has a single memory channel, not two. This corrects DMI type 17 reporting and the memory clear functions. BUG=b:65403853, b:64193190 BRANCH=none TEST=AGESA DMI reports the correct number of DIMMs. Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-20util/cbfstool: Add "expand" command to make CBFS span an fmap regionPatrick Georgi
vboot images come with multiple regions carrying CBFS file systems. To expedite hashing (from slow flash memory), the FW_MAIN_* regions are truncated since they typically have pretty large unused space at the end that is of no interest. For test purposes it can be useful to re-engage that space, so add a command that creates a new empty file entry covering that area (except for the last 4 bytes for the master header pointer, as usual). BUG=b:65853903 BRANCH=none TEST=`cbfstool test.bin expand -r FW_MAIN_A` creates a new empty file of the expected size on a Chrome OS firmware image. Change-Id: I160c8529ce4bfcc28685166b6d9035ade4f6f1d1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21598 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20util/docker: Update coreboot-sdk dockerfileMartin Roth
- Fix typo in comment - Aphabetize package list and put each package on a single line - Add environment variables into coreboot user's .bashrc file - Add openssl, qemu, and shellcheck to installed packages Change-Id: I37771be5d3ecaa61d76d99e689b422144a6d7dc6 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/21582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
2017-09-20util/lint: update checkpatch & spelling.txt to upstream versionsMartin Roth
- Update checkpatch.pl to version 0547fa58 (checkpatch: add 6 missing types to --list-types) - Update spelling.txt to version d9f91f8 (scripts/spelling.txt: add a bunch more spelling mistakes) - Fix an additional unescaped left brace in a regex - causes warnings in new versions of perl. Change-Id: Ic443099e90a46280f18d58799afc72d00dc83793 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/21581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-20device/dram/ddr2.c: Improve error returning and debug outputArthur Heymans
This patch outputs decoding errors with BIOS_WARNING instead of depending on CONFIG_DEBUG_RAM_SETUP. Returns SPD_STATUS_INVALID on invalid settings for tRR, bcd and tCK and doesn't try to create a valid setting if an invalid setting is detected. Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-20nb/i945/raminit: Use common ddr2 decode functionsArthur Heymans
This simplifies computing dram timings a lot. This removes computation of rank size based on columns, rows, banks,... and uses the information in SPD byte 31. The result of this is that dimms with multiple asymmetric ranks are not supported anymore. These however are very rare and most likely never tested on this platform. This also uses i2c block read instead of byte read to speed up the raminit. The result is less time is being spend reading SPDs. It still keeps smbus read byte as a backup if i2c block read were to fail. Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-20board_status: Tell user where to find output when results are uploadedDavid Hendricks
If results are uploaded the temporary directory in which they are stored gets deleted, yet we currently point to the deleted directory in the output. This patch fixes it so that we point to the actual location in the local repository where uploaded results are found. Change-Id: I1f42c3296ec1d19fcfa4911307e07e67de289895 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/21415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-20soc/intel/cannonlake: Add PMC pci driversLijian Zhao
Add PMC pci driver on top of PMC common code, also include pmc init code reference from skylake. Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-20nb/intel/i945/early_init.c: Replace numbers with macrosElyes HAOUAS
Change-Id: I270d17a2eff2c6664bf936425a6ed344be3feabe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/21524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-19mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT tableBora Guvendik
Change-Id: Id0b2b9e9ae2755ed89cee337a1a085fc4e95b073 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19soc/intel/cannonlake: Add PCIE IRQsBora Guvendik
Change-Id: Iea99baaa58d2212e7d09a19aaac9d303226f7c5e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19soc/intel/common/block: Add pci device id for CNL-YBora Guvendik
Change-Id: I2820a39a34a80d066ca5cb364f67dbde0203803e Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19AGESA binaryPI: Clean up amdfamXX.h includeKyösti Mälkki
Change-Id: Iba8b8d33e1f10e28745234988d97d4fafd04c798 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-19ec/quanta/it8518: add missing HID to SIO deviceMatt DeVillier
The ACPI spec requires devices with children to have an HID, and Windows enforces this strictly. Without the SIO device having an HID, Windows will not detect the attached PS2 keyboard and trackpad. Therefore, add the proper HID. TEST: boot Windows on google/stout, observe PS2 keyboard and trackpad detected and functional. Change-Id: I61d7341c15483f8e1fe0e485a25591ceb92eaae1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-19ec/quanta/it8518: correct ACPI battery data fed into ToString()Matt DeVillier
ToString() requires the input buffer data to be null-terminated, but the data returned by the EC is not, leading Windows to fail to report any battery data at all. Correct this by concatenating a null terminator (0x00) to the end of the buffer data before inputting to ToString() where needed TEST: boot Windows on google/stout, observe battery data reported correctly. Change-Id: I974afcd6ff1c617301d0897d6bd1fe14200aa3b9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-19ec/purism/librem: fix battery present rateMatt DeVillier
EC ACPI code is calculating the drain rate, but does not store it in the battery status package before returning it. Correct this omission, and set the drain rate to a preset minimum if calculated value is less. Taken from vendor firmware ACPI dump. Change-Id: I52837d5879112ab3103976bda28906fac8f880ec Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-19sb/intel/bd82x6x: Add awareness of ME's Alt Disable ModeNathaniel Roach
me_cleaner now allows setting a bit in the PCH straps - AltMeDisable tells the ME to stop execution after BUP - disabling the 30 minute watchdog - but also "breaking" the ME. The ME reports opmode = 2. This means the ME will not respond when we wait for an acknowledgement about the DRAM being ready. The current code waits 5 seconds for a response, that in this case, never comes. If the ME is reporting opmode 2, don't delay or wait for a response from the ME. Tested on my X220, this patch fixed the five seconds before the payload executed. Verified using the timestamp patch. Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-19amd/stoneyridge: Add northbridge definitionsMarshall Dawson
Begin adding D18F1 definitions to northbridge.h. Change-Id: I4fa2f9a4af8fbb3c2919ffb5dca34cbe333bc958 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-17ifdtool: Refactor some codeBill XIE
Add find_fcba(), find_frba(), find_fmba(), find_fpsba() and find_fmsba() to replace those copy-pasted addressings. This commit is one separated from the original I6d05418c. Change-Id: I98965711e4cb9792e5cc86cc4c1035559e0274f5 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-17ifdtool: redesign some structuresBill XIE
Redesign some array-like structures as true arrays, and rewrite functions to dump them as loops. This commit is one separated from the original I6d05418c. Change-Id: I161c9a2ae83d26e658d67d0804e943fff95fe076 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-17ifdtool: merge region_filenames with region_name(s)Bill XIE
There is no reason to keep a separate region_filenames array, so I merge it into region_name(s). This commit is one separated from the original I6d05418c. Change-Id: I38489c6d3b3c161e9b0281188e6cdd0b62e38335 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21509 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-17ifdtool: Const-correct and redesign some functionsBill XIE
Const-correct some functions which do not write back, and use pointers to access existing region_t variables. The last changeset is dismantled this time. This commit is only focused on const-correctness. Change-Id: I6d05418c8b32fa31dcd038a3e56f9aefe13fa9c4 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21288 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-17board_status: Add option to set cbmem pathDavid Hendricks
This allows the user to specify a custom path for cbmem on the DUT. Change-Id: I2c28737d6efaae238fd6831cd3d00b2142b39a4c Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/21565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-17cpu/x86/sipi_vector.S: Use correct op suffixDamien Zammit
clang wont compile `cmp` asm opcode because it's ambiguous, use the correct op suffix `cmpl` Change-Id: I82da5a9065b382e182dc7d502c7dca2fc717543b Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-17via/cn700: Fix clang error with missing mainDamien Zammit
According to clang, main has no prototype for bcom/winnetp680 so add it into corresponding raminit.h Change-Id: I8a55267901986757a4fa88ee13460ffbed3eeadc Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16mb/google/poppy: Add lens_focus property for OV13858 camera moduleV Sowmya
Add lens_focus property with reference to VCM device for OV13858 camera module to register the corresponding v4l2 sub-device asynchronously. BUG=b:64133998 BRANCH=none TEST=Build and boot soraka. Dump DSDT and verified that it has the required entries and verified the camera functionality. Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21512 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-16google/lulu,gandof: set kb backlight on bootMatt DeVillier
Set keyboard backlight to 75% on boot, except when resuming from S3. This enables the backlight at a reasonable level prior to the OS driver taking over, providing early proof-of-life and enhanced usability in grub etc. Uses same method as other google boards with a keyboard backlight (chell, link, samus). 75% value determined based on user feedback. TEST: boot google/lulu,gandof boards, observe keyboard backlight enabled in pre-OS environment. Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16soc/intel/common: smm.h: Fix copyright yearJonathan Neuschäfer
Intel obviously didn't exist in 201 :-) Change-Id: I230d3b92ec6832fcea056fd3d099147002274d73 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16payloads/external: Clone GRUB2 over HTTPSJonathan Neuschäfer
Since the git:// protocol is unencrypted and unauthenticated, there's a security risk associated with using it: A man-in-the-middle attacker could replace e.g. the master branch with malicious code. Mitigate this risk somewhat by cloning GRUB2 via HTTPS. Change-Id: Ice8f8d108e7dfa1a1ecd58d9735944fa9570ace8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-16google/reks: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/reks (Lenovo Chromebook N22/N42) as a variant of the cyan Braswell basebaseboard. - Add board-specific code as the new reks variant - Add new I2C touchscreen device and SPD files to the baseboard for potential reuse by other variants Sourced from Chromium branch firmware-reks-7287.133.B, commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1"" Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16google/edgar: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/edgar (Acer Chromebook 14 CB3-431) as a variant of the cyan Braswell basebaseboard. - Add board-specific code as the new edgar variant - Add common code to the baseboard which will apply to all variants other than cyan Sourced from Chromium branch firmware-edgar-7287.167.B, commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16mainboard/intel/glkrvp: Add support for audioHannah Williams
This patch adds the below: 1) Add correct SSP endpoint config for spk and headset 2) Update GPIO config for jack detection 3) Update GPIO config for I2S pins TEST=sound card binds TEST=cross checked SSDT entries from /sys/firmware/acpi/tables/ TEST=Jack interrupt works Change-Id: I32022ddacd79917730080889c040f842e0c9e6b9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/19799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-16soc/intel/apollolake: Leave Hda enabled for GLKHannah Williams
Audio was disabled during initial stages, this patch enables back. It was disabled to unblock other validation tests. TEST=lspci lists audio controller Change-Id: I5d3872e86623763e20ee6464897f47792c731642 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/21529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-16device/dram/ddr2: Fix decoding tRRArthur Heymans
Bit 7 is set on all options so only the default option in the switch statement is returned. Change-Id: I6a698ec9c15a2611a34c5965edf93638553775f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15mainboard/intel/cannonlake: Add ec entry into flashmapLijian Zhao
Add EC entries into chromeos.fmd file. BRANCH=None BUG=None TEST=Flash image and confirm system can get out of reset successfully. System will not be able to reach reset vector if flash map described in coreboot does not match intel flash map generated from fit. Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21526 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15util/scripts/cross-repo-cherrypick: improve cros-side rewritePatrick Georgi
Sometimes the BUG/BRANCH/TEST metadata isn't separated by a newline from the later git/gerrit metadata, which messes up further processing. Add that newline to minimize the amount of human intervention required. Change-Id: I37171bf6764b64e0ab0e81297a03f4d8b7744256 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15soc/amd/stoneyridge: Improve code qualityRichard Spiegel
Remove empty functions. In function pointer structure "device_operations", replace the 0 equality by NULL equality. Files: hda.c, sata.c and usb.c Change-Id: I9f8dc7681ab2e651872e69a8b2e990e59ebe80c9 Signed-off-by: Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21522 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15mb/google/poppy: enable AER for PCIe root port 0Rizwan Qureshi
Enable PCIe Advanced Error Reporting for PCIe root port 0. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21425 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-15soc/intel/skylake: Move UNCORE PRMRR base and mask defines.Pratik Prajapati
UNCORE PRMRR BASE and MASK MSRs are not common, so move to SOC specific header file and rename the #define to start with MSR_* Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15soc/intel/common/sgx: use SOC specific API to get PRMRR base and maskPratik Prajapati
Use soc_get_uncore_prmmr_base_and_mask() API to get PRMRR base and mask. Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21246 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15soc/intel/common/sgx: Define and use soc_fill_sgx_param()Pratik Prajapati
To remove chip.h dependency from SGX common code - Create API soc_fill_sgx_param() and use it in sgx.c - Implement same API for skylake/kabylake - define sgx_param structure Also include intelblocks/sgx.h instead of soc/msr.h Change-Id: I358f0817bec5dd6cd147a645675b5688969a04e0 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15MAINTAINERS: Remove extra unnecessary spaceSumeet Pawnikar
Remove extra unnecessary space at end of line. Change-Id: I27688c3b8df71b875f1dc1020465d838756362be Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/21521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15MAINTAINERS: Add Julius as LZ4 maintainerJulius Werner
I imported the LZ4 compression code and want to keep an eye on it to ensure that our sources stay in sync with upstream. Change-Id: I249ce24f6630d66d451d993198cd267478e5743e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/21488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15MAINTAINERS: Add INTEL FSP DENVERTON-NS SOC & HARCUVAR CRBMariusz Szafranski
Add Intel FSP Atom C3000 SoC ("Denverton" and "Denverton-NS") and Harcuvar CRB to the list. Change-Id: I1c4bfd0900e8d425b95b5ef6c541b1e988846667 Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com> Reviewed-on: https://review.coreboot.org/21515 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
2017-09-15google/cyan: convert to variant configurationMatt DeVillier
Setup cyan to be the baseboard for other Google Braswell boards, to be added in subsequent commits: - Keep code common to all Google Braswell boards in the baseboard, and separate out the board-specific bits into the new cyan variant. - Define the I2C ACPI devices such that they can be easily reused for other variants. - Switch the trackpad/touchscreen interrupts from edge to level, for better performance/compatibility, as was done with all previous Google boards. - Add code to the baseboard to allow optional variant-specific parameters to be used for both memory and silicon init. - Remove superfluous includes, replace some hardcoded values with variables, and correct typos/formatting errors. Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14mainboard/intel/cannonlake_rvp-u: Configure USB portsPratik Prajapati
Configure USB2, USB3 and Type-C ports for CannonLake-U RVP Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14mainboard/intel/cannonlake_rvp-y: Configure USB portsPratik Prajapati
Configure USB2, USB3 and Type-C ports for CannonLake-Y RVP Change-Id: Ic3b6b481cb33bfefb267910a5e649877d900d109 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14src/soc/intel/cannonlake: Define USB configuration paramsPratik Prajapati
Define USB2, USB3 and Type-C configuration for CannonLake. Change-Id: I42243950366d672e886158eb1934350f47b4ff1f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 04:57:14 +0000