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2019-07-02security/memory: Clear memory in ramstagePatrick Rudolph
* Add architecture independend way of clearing all DRAM * Implemented in ramstage as MTRRs need to be set to speed up clearing. Takes up to 15 seconds per GiB otherwise. * Use memset_pae on x86 * Add quirks for FSP1.0 Tested on P8H61M-Pro: * Clears 4GiB in less than 1 second Tested on wedge100s: * Clears 8GiB in 2 seconds Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02cpu/x86/pae/pgtbl: Add memset with PAEPatrick Rudolph
To clear all DRAM on x86_32, add a new method that uses PAE to access more than 32bit of address space. Add Documentation as well. Required for clearing all system memory as part of security API. Tested on wedge100s: Takes less than 2 seconds to clear 8GiB of DRAM. Tested on P8H61M-Pro: Takes less than 1 second to clear 4GiB of DRAM. Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02soc/intel/icelake: Disable HDA based on devicetreeSubrata Banik
Change-Id: I28c2beca4bc26ddb896e68886571ebdc82276b48 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-02QC common: fix compiler complaint, missing <string.h>T Michael Turney
Change-Id: I5b5b7bc61dd82fb1b866857d60926b057fae3715 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33445 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-01util/cbmem: Update banner string regular expressionYou-Cheng Syu
Banner string format has been changed (CB:30935). We should update our regular expression correspondingly. Also add "verstage" into the stage search list since some boards (e.g., Kukui) might start console initialization at verstage. Change-Id: I16eba3ac5e203e80b0bfd42a4294401dbccd4463 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-01util/ifdtool: Enable -Wmissing-prototypesJacob Garber
Change-Id: Idc31144024f785a42cbad78bf2c965d08dcc5178 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-01util/ifdtool: Make internal functions staticJacob Garber
These functions are only used in ifdtool, so they can be made static. Change-Id: Ia48bfecb89a7445dbd0f140acb5ac0592da2ebe7 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-01util/cbfstool/ifittool: use strtol function instead of atoiPandya, Varshit B
Fix error "Invalid option -A" by adding "A" to options list. Also, atoi does not parse hex string, for instance 0x200 is interpreted as 0, and this causes a failure when updating second FIT table using -j option. Use strtol instead of atoi BUG=none BRANCH=none TEST=Build and boot hatch after enabling dual bootblock feature. Change-Id: Ib227437f88ffcccda1ce2f20a9ab098e5aa091c7 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-01mb/up/squared: Add kernel cmdline parametersFelix Singer
Since ttyS0 isn't used for UART0, configure ttyS4 as default Change-Id: Ia0469226253b08328807d5401c05633296e43d22 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33785 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-01Use 3rdparty/intel-microcodeArthur Heymans
Instead of maintaining this in 3rdparty/blobs use the 3rdparty/intel-microcode which is maintained by Intel. This allows for some finegrained control where family+model span multiple targets. Microcode updates present in 3rdparty/blobs/soc/intel/{baytrail,broadwell} are left out since those contain updates not present in the Intel repo. Those are presumably early CPU samples that did not end up in products. The following MCU are get a new revision: old: sig 0x000306c3, pf_mask 0x32, 2018-04-02, rev 0x0025, size 23552 sig 0x00040651, pf_mask 0x72, 2018-04-02, rev 0x0024, size 22528 sig 0x000206a7, pf_mask 0x12, 2018-04-10, rev 0x002e, size 12288 sig 0x000306a9, pf_mask 0x12, 2018-04-10, rev 0x0020, size 13312 sig 0x000706a1, pf_mask 0x01, 2018-05-22, rev 0x0028, size 73728 sig 0x000506c9, pf_mask 0x03, 2018-05-11, rev 0x0032, size 16384 sig 0x000506ca, pf_mask 0x03, 2018-05-11, rev 0x000c, size 14336 sig 0x000806e9, pf_mask 0xc0, 2018-03-24, rev 0x008e, size 98304 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000906ea, pf_mask 0x22, 2018-05-02, rev 0x0096, size 97280 sig 0x000906eb, pf_mask 0x02, 2018-03-24, rev 0x008e, size 98304 sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432 sig 0x000506e3, pf_mask 0x36, 2018-04-17, rev 0x00c6, size 99328 sig 0x000906e9, pf_mask 0x2a, 2018-03-24, rev 0x008e, size 98304 sig 0x000406e3, pf_mask 0xc0, 2018-04-17, rev 0x00c6, size 99328 new: sig 0x000306c3, pf_mask 0x32, 2019-02-26, rev 0x0027, size 23552 sig 0x00040651, pf_mask 0x72, 2019-02-26, rev 0x0025, size 21504 sig 0x000206a7, pf_mask 0x12, 2019-02-17, rev 0x002f, size 12288 sig 0x000306a9, pf_mask 0x12, 2019-02-13, rev 0x0021, size 14336 sig 0x000706a1, pf_mask 0x01, 2019-01-02, rev 0x002e, size 73728 sig 0x000506c9, pf_mask 0x03, 2019-01-15, rev 0x0038, size 17408 sig 0x000506ca, pf_mask 0x03, 2019-03-01, rev 0x0016, size 15360 sig 0x000806e9, pf_mask 0xc0, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000906ea, pf_mask 0x22, 2019-04-01, rev 0x00b4, size 98304 sig 0x000906eb, pf_mask 0x02, 2019-04-01, rev 0x00b4, size 99328 sig 0x00050665, pf_mask 0x10, 2019-03-23, rev 0xe00000d, size 19456 sig 0x000506e3, pf_mask 0x36, 2019-04-01, rev 0x00cc, size 100352 sig 0x000906e9, pf_mask 0x2a, 2019-04-01, rev 0x00b4, size 99328 sig 0x000406e3, pf_mask 0xc0, 2019-04-01, rev 0x00cc, size 100352 Change-Id: Idcfb3c3c774e0b47637e1b5308c28002aa044f1c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-01security/tpm/tss/tcg-2.0/tss.c: Add debug message to tlcl_lib_init()Frans Hendriks
No message is reported in tlcl_lib_init() when tis_init() or tis_open() returned an error value. Add debug string. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I522e488ddd3a1bd94a1a8c8470c757bd79c6d5c5 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-01util/superiotool/nuvoton.c: Minor tag update/removalPavel Sayekat
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Change-Id: Ic193f31b9776683849578bf9009c51bf22d1dae6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-01intel/fsp_rangeley: Use fixed FSB/BCLK value 100 MHzKyösti Mälkki
Prior to commit d731a24 src/cpu/intel: Set get_ia32_fsb function common value of 200 was silently used as a default for fsp_rangeley (model_406dx) in cpu/x86/lapic/apic_timer:set_timer_fsb(). After the commit, get_ia32_fsb() returns -2, eventually resulting with divide-by-zero in timer_monotonic_get(), as get_timer_fsb() returns 0. Add Rangeley CPUID model 0x4d to get_ia32_fsb() as a fix, using BCLK = 100 MHz based on the comments in northbridge/intel/fsp_rangeley/udelay.c Change-Id: I306f85dba9b1e91539fc0ecc9b2ae9d54f82be6c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-01Kconfig: Enable RAMPAYLOAD for x86Subrata Banik
This patch makes CONFIG_RAMPAYLOAD default enable upon selection of HAVE_RAMPAYLOAD kconfig from mainboard for x86 platform. Without this CL, CONFIG_RAMPAYLOAD is still disabled although mainboard has selected CONFIG_HAVE_RAMPAYLOAD. Change-Id: I40308bbf970a0dbe5f7e2086ed8a7a70c2a3a32c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33859 Reviewed-by: ron minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-30pci_ids.h: Add AMD Picasso IDsMarshall Dawson
Change-Id: I4ac67d1577229e63424dd7fd0ff84d1acfe826c3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-06-29libpayload: cbgfx: Run cbgfx_init() before we need it for draw_box()Julius Werner
calculate_color() uses the 'fbinfo' global that is initialized by cbgfx_init(), so we need to run the latter before we can run the former or we get a null pointer access. Change-Id: I73ca8e20ca36f64d699379d504fd41dc2084f157 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-06-28sb/amd/sb{700,800}: Clean up index manipulationsJacob Garber
It looks like in days gone by that these switches were once parts of loops that incremented 'index' as they went along. However, we don't have any loops anymore, so remove the needless increments and streamline the rest of the assignments. Change-Id: Iaabee984333c273af7810f9c11ed26bbb2a995d1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-28device: Tidy up add_more_links()Jacob Garber
- Add documentation comment - Use 'unsigned int' to make checkpatch happy - Return early if no more links need to be added - Add error handling if malloc fails - Clean up whitespace Change-Id: I70976ee2539b058721d0ae3c15edf279253cd9b7 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229634 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33238 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28device,nb/amd: Deduplicate add_more_links()Jacob Garber
This function is duplicated in many AMD northbridge files, and all the definitions have started to diverge somewhat. This moves a single copy into device utils and deletes the rest. The function definition from nb/amd/amdfam10 was chosen to be kept, since it contains several fixes from commit 59d609217b (AMD fam10: Fix add_more_links) that the others don't have. For the ease of diffing, the checkpatch lints and other small cleanups will be done in a follow-up patch. Change-Id: I5ea73126092449db3f18e19ac0660439313072de Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33237 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28nb/intel/pineview: Remove unused codeJacob Garber
All the clocks are switched on anyway, so this series of if statements isn't needed. Change-Id: I654043fd6736caa6890fd697015c577ddaa7cd41 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 13473{27-30} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-28device/dram: Inline value into print statementJacob Garber
By default printram() expands to nothing in normal builds, and so scan-build thinks that the assignment to reg8 is unused. Inline the value of reg8 into the print statement to silence the warning. Change-Id: I921fe08949c4135367bee9646b3b365097fab19e Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-28cpu/amd/family_10h-family_15h: Remove dead assignmentJacob Garber
Pstate_num is initialized later when it is used as a loop index, so this duplicate assignment can be removed. Change-Id: I71429bd3306139a823ed39e751d779e4d874f657 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-28sb/amd/rs780: Remove dead assignmentJacob Garber
We return immediately after, so this assignment can be removed. Change-Id: I2a317ada0132a40b623402055b3b995bde80ddf5 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: scan-build 8.0.0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-28MAINTAINERS: Add myself as a maintainer for apple boardsEvgeny Zinoviev
Change-Id: I33bf45c81cc4be157ea71806900a545ee68ecee8 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-28{soc,northbridge}/Kconfig: Remove unused CACHE_MRC_SIZE_KBElyes HAOUAS
Change-Id: Ie922832bc7641a44a53c0cda8d808579c66420b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-28soc/intel/cannonlake: fix use of legacy 8254 timerMatt DeVillier
FSP sets the use of the 8254 timer via the Enable8254ClockGating UPD, which defaults to enabled, overriding what is set by coreboot. Per the FSP integration guide, this UPD needs to be disabled when a legacy OS is booted (ie, when SeaBIOS is used as the payload). Add a Kconfig option to set the UPD properly based on payload selection, and remove the existing coreboot code in lpc.c since it is either ineffective or being overridden by FSP. Test: build/boot out-of-tree WHL board with both SeaBIOS and Tianocore, ensure 8254 timer usage set correctly for each. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-28asus/am1i-a: Enable UART according to CONFIG_UART_FOR_CONSOLEMike Banon
It has been observed by me and Elisenda Cuadros / Gergely Kiss [1] that the boot process of this board is super slow when UART 0 is being used - even if nothing is connected to it. Enable UART according to CONFIG_UART_FOR_CONSOLE - and, if UART 0 is selected, it will be initialized at romstage and this problem will not happen. [1] https://mail.coreboot.org/pipermail/coreboot/2018-February/086132.html Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I6579aa8fd092da84f8afdcc33496db45c582919f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-28mb/google/kohaku: Correct trackpad i2c addressSeunghwan Kim
Correct i2c address of trackpad. It should be 0x20. BUG=None BRANCH=None TEST=Verified trackpad works on pre-evt system Change-Id: I7ded21ce8ff9e907e436777a27edb4273512011d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-06-28payloads/external/LinuxBoot: Update x86_64 defconfigPatrick Rudolph
* Add support for Linux 5.x ** Select PCI, which isn't the default anymore with 5.x ** Select google firmware driver, which wasn't build any more * Add support for Intel LPSS uart ** Select MFD and MFD_INTEL_LPSS_PCI ** Increase console count to 32 * Add support for coreboot framebuffer ** Select FB_SIMPLE * Add support for eMMC/SDHCI ** Select MMC_SDHCI_* * Add support for u-root's localboot ** Select KEXEC_FILE_LOAD ** Select FIRMWARE_MEMMAP Stats: * Kernel size 1.9MiB * U-root (core + systemboot) 4.6MiB Tested on Intel APL Up² board: * Fixes non working console on APL Up2 board and eMMC bootmedia shows up. * Allows to boot GNU/Linux from eMMC using 'localboot' Change-Id: Ib5bd33531741e588ac7d5ff6a02b0482f6655ddf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-28lib/gnat: Enable -WerrorNico Huber
We want to catch warnings as early as possible. Change-Id: Ifdb2ff8f7973d557a437ac127e073306f76ca6f6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33848 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28lib/gnat: Use ADAFLAGS instead of CFLAGSNico Huber
Commit 6d7564cdfe (Move -Wlogical-op into xcompile) introduced GCC_ADAFLAGS_<arch> but forgot to use them for libgnat. Fix that. Change-Id: Ia9079f01bb3c2a08296a3d3cc32fdf4ae5bb60c7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33847 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28mb/emulation/qemu-riscv: Use generic 8250 uart driverPatrick Rudolph
Drop hacked uart code and use the generic 8250 uart driver for ns16550a. Tested on qemu-system-riscv64: * The UART is still working. Change-Id: I6efda913fa39e0cfa466b52c570572aca90dacdf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33735 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-28arch/riscv/mcall: Drop debug codePatrick Rudolph
The printk has no effect as console_init() hasn't been called. Also drop unused variables and headers. Change-Id: I5bf5a8822c69bbcc3de1de460d19585b8330649f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx>
2019-06-28qualcomm: qclib: Ensure interface table entry name is terminatedJulius Werner
This string is printed in dump_te_table() so we should make sure it's properly null-terminated. This fixes Coverity issue 1401305. Change-Id: I45827f552c2d8a4e01b50a699ac88ee457043282 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-27libpayload: Re-initialize UART RXPrudhvi Yarlagadda
UART RX needs to be re-initialized in libpayload as it is getting reset at the end of coreboot. Change-Id: I7820bd7afd2e5f81e21a43f330ed42d3a732d577 Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-27mainboard: Add support for ASUS P8Z77-M PRO desktop mainboardVlado Cibic
Add support for ASUS P8Z77-M PRO desktop mainboard Working: - Tianocore and SeaBIOS boot - PS/2 keyboard and mouse - Audio - S3 Suspend, shutdown and reboot - USB2 / USB3 - Gigabit Ethernet - SATA3, SATA2 and eSATA - NVME - CPU Temp sensors - TPM - Native raminit and also MRC - PCIe GPU in all PCIe slots (16x/8x/4x) (linux) - Integrated graphics with both libgfxinit and Intel Video OpROM (all connectors VGA/DVI-D/HDMI) Signed-off-by: Vlado Cibic <vladocb@protonmail.com> Change-Id: I47d24ac8b236f929c3160f9a769b971d83710f9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/33328 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-27mb/upsquared: Align partitions to 4KiBFelix Singer
This fixes warnings while booting coreboot. Change-Id: If1e99b74ded5f743a3ad4fc829ae9747276c483a Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33784 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-27mb/asrock/h110m: set serirq_mode to continuous modeMaxim Polyakov
By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port from the SurerIO chip don't work correctly after the LPC controller (PCI 0:1f.0) initialization. Console output is broken. The patch fixes this bug by overriding the serirq_mode option in the devicetree.cb to set Continuous SIRQ mode Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33801 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-27drivers/pc80/tpm: add support for TPM emulator SwTPM 2.0 moduleTsung Ho Wu
Add software TPM 2.0 emulator to tpm device probe list. SwTPM: https://github.com/stefanberger/swtpm Tested on qemu q35 with MAINBOARD_HAS_LPC_TPM and MAINBOARD_HAS_TPM2 set in qemu-q35 Kconfig. Qemu: see qemu flags at https://s3hh.wordpress.com/2018/06/03/tpm-2-0-in-qemu/ How to see it work. Ubuntu 18.04: 1. Install SwTPM from https://github.com/stefanberger/swtpm 2. Add MAINBOARD_HAS_LPC_TPM and MAINBOARD_HAS_TPM2 to src/mainboard/emulation/qemu-q35/Kconfig and rebuild coreboot.rom 3. mkdir -p swtpm0 4. swtpm socket --tpmstate dir=swtpm0 --tpm2 --ctrl \ type=unixio,path=swtpm0/swtpm-sock --log level=20 & 5. qemu-system-x86_64 -machine q35 -m 2G \ -chardev socket,id=chrtpm,path=swtpm0/swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm -device \ tpm-tis,tpmdev=tpm0 -pflash build/coreboot.rom \ -serial $(tty) -display none 6. Check boot log and search 'Found TPM'. Change-Id: I5f58d2c117afbd057bb91697912db826db1d67a1 Signed-off-by: Tsung Ho Wu <tsungho.wu@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33302 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-27security: Add memory subfolderPatrick Rudolph
Add files to introduce a memory clearing framework. Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by platforms, that are able to clear all DRAM. Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user selectable to always clear DRAM on non S3 boot. The function security_clear_dram_request tells the calling platform when to wipe all DRAM. Will be extended by TEE frameworks. Add Documentation for the new security API. Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2019-06-27vboot: remove vboot_handoff stepJoel Kitching
Depthcharge no longer reads this data structure, and uses the vboot workbuf in vboot_working_data instead. Since vboot2 downstream migration is not yet completed, the vboot2 -> vboot1 migration code is still required, but has been relocated to depthcharge. BUG=b:124141368, b:124192753 TEST=make clean && make runtests BRANCH=none Change-Id: I769abbff79695b38d11fb6a93c2b42f64d4bafde Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33535 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-26mb/google/hatch: Add a GPIO to enable/disable FPMCU powerPhilip Chen
A FPMCU power-control pin (GPP_C11) is added to the latest hatch reference schematic. Even though this is not implemented in hatch rev1 board, the future hatch family boards with FPMCU should all have this control pin. On the old boards without this control pin, GPP_C11 is a floating TP, and thus this patch should be backward-compatible. BUG=b:130307667, b:135216932 TEST=build Signed-off-by: Philip Chen <philipchen@google.com> Change-Id: I6a84eeb6aab562258e749a8a5d09dadfa0e43587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-26mb/google/hatch: Remove pulls on NC padsFurquan Shaikh
There is no need to add internal termination (PU/PD) on the not-connected pads. This change gets rid of the terminations on the NC pads. Change-Id: I3df538d7127e5ef75e6e6ff9db3524e26f0450ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-06-26mb/google/hatch/variants/baseboard: Update PL2 power limit valueSumeet Pawnikar
Update PL2 power limit value from 44W to 64W. BUG=None BRANCH=None TEST=Build and Boot hatch EVT Change-Id: I3f4b5ab8bf0ce9464c322c148843f5a3e8d706d9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-06-26soc/intel/cannonlake/Kconfig: Don't have all variants select ↵Arthur Heymans
SOC_INTEL_CANNONLAKE This allows to use Kconfig options to differentiate between SOC variants. Change-Id: Ica11c68377e3d0dc8a8f48198e01a74d7bebe642 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33559 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-26cbfstool/fit: need inttypes.h for PRIx64Joel Kitching
This is causing coreboot build in Chromium OS to fail. BUG=None TEST=emerge-eve coreboot BRANCH=none Change-Id: I4faa140b3046651b4ed0a9aeefe437048c6ef0da Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-26mb/up/squared: Remove unnecessary codeFelix Singer
This patch removes unnecessary code which configures default FSP values. Change-Id: If7dae4f24a9fcb01d2d47063dd3a0f4ce6c120d2 Signed-off-by: Felix Singer <felix.singer@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-25atlas: enable GEO_SARCaveh Jalali
BUG=b:131634035 BRANCH=none TEST=verified SAR data shows up in ACPI SSDT table. Change-Id: I65ef59c9616b1cae3fa4c4b18bbfe4ed098d2891 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-25intel/945 boards: Use smp_write_pci_intsrc()Kyösti Mälkki
Radically reduces line lengths and splits '(bus<<2) | INT' to separate parameters. Change-Id: I0cfd714da3d2773affdb34d1dab2ac32879e2cfd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30740 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-25soc/intel/dnv: Fix value of B_PCH_GPIO_RX_SCI_ROUTEPatrick Havelange
The value for that macro should be 1<<19. This is confirmed by the Intel doc and also by N_PCH_GPIO_RX_SCI_ROUTE. See Intel Atom® Processor C3000 Product Family Datasheet (February 2018) : https://www.intel.com/content/www/us/en/products/docs/processors/atom/c-series/c3000-family-datasheet.html Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com> Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33573 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-13 05:51:29 +0000