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2020-08-12sb/intel/bd82x6x: Remove incorrect RCBA registersAngel Pons
These were probably copy-pasted from some ICHx southbridge, and then some were corrected because native PCH init uses them. Delete the definitions which are unused and are invalid for this southbridge. Change-Id: I0be72f76c7fcc63316ae8566891e0732456a8c55 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12sb/intel/lynxpoint: Remove incorrect RCBA registersAngel Pons
These were probably copy-pasted from some ICHx southbridge. However, datasheet shows that some of these are located elsewhere, and some others have disappeared completely. As they aren't in use, drop them. Change-Id: I2d09547bdbfd5f8f72ce3541347d9fec28630c79 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-12sb/intel: Remove inexistent references to IDE controllerAngel Pons
This device doesn't exist on these southbridges. Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-12volteer: Create lindar variantJulia Tsai
Create the lindar variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.2). BUG=b:161089195 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_LINDAR Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> Change-Id: I08923cde932b7304bcb01cd747530c87949e4692 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-12soc/intel/common/block/sata: Add common SATA driverSubrata Banik
Enable PCI_COMMAND_MASTER for SATA controller to ensure device can behave as a bus master. Otherwise, the device can not generate PCI accesses. BUG=b:154900210 TEST=Able to build and boot CML and TGL platform. Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12mb/prodrive/hermes: Add multifunction device for UART 2Christian Walter
On CNP-H, only four I2C controllers are available, so PCI devices 19.0 and 19.1 are missing. However, PCI device 19.2 still exists as UART 2. That function 0 is missing means UART 2 can only be used in ACPI mode. Both devices need to be marked as hidden on the devicetree so that the allocator takes UART 2 into account. Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-12soc/intel/tigerlake: Add IRQs for LPSS uartPatrick Rudolph
Values are taken from pci_irqs.asl. The common code will make use of those defines to generate ACPI SSDT code for LPSS uarts operating in "ACPI mode". Change-Id: I5ef93493965834cda30d70918e65de3129e547b7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiBFurquan Shaikh
This change reorganizes flash map layout for zork to allow WP_RO to grow to 8MiB. This is to allow more space for the firmware UI screens in RO. Following changes are made in the layout: 1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for MRC cache. Next section can start on 64K boundary immediately after MRC cache. 2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB each. Each region is currently at ~2MiB of usage. 3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size supported by coreboot. 4. SMMSTORE is restricted to 4K. 5. RW_LEGACY region is dropped down to ~1.9MiB. BUG=b:161949925 TEST=Verified that write-protection for RO still works fine, device boots in recovery and non-recovery mode. Also, verified that the dump of fmap looks correct: dump_fmap -h firmware/image-trembyle.serial.bin name start end size WP_RO 00800000 01000000 00800000 RO_SECTION 00804000 01000000 007fc000 COREBOOT 00875000 01000000 0078b000 GBB 00805000 00875000 00070000 RO_FRID 00804800 00804840 00000040 FMAP 00804000 00804800 00000800 RO_VPD 00800000 00804000 00004000 RW_LEGACY 0061d000 00800000 001e3000 SMMSTORE 0061c000 0061d000 00001000 RW_NVRAM 00617000 0061c000 00005000 RW_VPD 00615000 00617000 00002000 RW_SHARED 00611000 00615000 00004000 VBLOCK_DEV 00613000 00615000 00002000 SHARED_DATA 00611000 00613000 00002000 RW_ELOG 00610000 00611000 00001000 RW_SECTION_B 00310000 00610000 00300000 RW_FWID_B 0060ff00 00610000 00000100 FW_MAIN_B 00312000 0060ff00 002fdf00 VBLOCK_B 00310000 00312000 00002000 RW_SECTION_A 00010000 00310000 00300000 RW_FWID_A 0030ff00 00310000 00000100 FW_MAIN_A 00012000 0030ff00 002fdf00 VBLOCK_A 00010000 00012000 00002000 RW_MRC_CACHE 00000000 00010000 00010000 SI_BIOS 00000000 01000000 01000000 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Joel Kitching <kitching@google.com>
2020-08-12mb/google/kukui: revise per-device memory mapping tableHung-Te Lin
In order to help identifying right DRAM info (especially in user space), we want to unify the mapping table and do the device-specific mapping by a virtual offset based on build config. BUG=b:161768221,b:159301679 BRANCH=kukui TEST=emerge-jacuzzi coreboot Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-12soc/mediatek/mt8192: Add PLL and clock init supportWeiyi Lu
Add PLL and clock init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-12soc/mediatek/mt8192: Add gpio driverCK Hu
Add MT8192 GPIO driver. Signed-off-by: Po Xu <jg_poxu@mediatek.com> Change-Id: I4b230aebc9eb4ca1bbf444c3a2f30159d707f37b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43959 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12soc/mediatek/mt8183: Transfer ddr geometry type to dram blobHuayang Duan
BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I3a677195f5036321939c60c8f9f1bace7c4a2e3f Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-08-11amd/picasso/acpi: Add power resources for UART0Kangheui Won
Follow-up for a31a769 - "amd/picasso/acpi: Add power resources for I2C and UART". Now PSP properly handles UART0 D3, we can shutdown UART0. BUG=b:158772504 TEST=suspend_stress_test for 50 cycles, * echo 1 > /sys/module/acpi/parameters/aml_debug_output * dmesg | grep FUR to check on&off for FUR0 [ 2413.647500] ACPI Debug: "AOAC.FUR0._OFF" [ 2413.736265] ACPI Debug: "AOAC.FUR0._ON" Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11cpu/intel: Remove Core 2 Duo E8200 CPUID from model_6fxAngel Pons
With a CPUID of 10676, it is clearly model_1067x... Wait, it's already there, but the comment is wrong. This ID isn't for Core Duo CPUs. Change-Id: Ia4b73537805e2a8fa9e28bde76aa20a524f8f873 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-11soc/intel/common/block/gspi: Recalculate BAR after resource allocationJes Klinke
The base address of the memory mapped I/O registers should not be cached across resource allocation. This CL will evict the cached value upon exiting the BS_DEV_RESOURCES stage. Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKsJonathan Zhang
CPX-SP has a CSTACK and 3 PSTACKs. Clean up the HOB header file to remove reference to non-existing PSTACKs. Adjust mainboard code accordingly. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic52b01cd89fb5b3fce64686d91f017f405566acd Reviewed-on: https://review.coreboot.org/c/coreboot/+/44279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-11xeon_sp/cpx: Enable PCH thermal device via FSPJohnny Lin
Tested=On OCP Delta Lake, OpenBMC sensor-util can see PCH Temp readings. Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44075 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11soc/amd/picasso: Correct processor ACPI scopeJason Glenesk
Change namespace from _PR to _SB. Cq-Depend: chrome-internal:3208104 BUG=b:153242529 TEST=Boot a trembyle with change applied and dump SSDTs to ensure processors are in _SB scope. Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44325 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11soc/amd/common/espi_util: espi_send_command: improve error messageFelix Held
It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the command failed, so we expect that one to be set. Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: espi_std_io_decode: fix edge case bugFelix Held
When address and data register for the SIO control register access is passed as one I/O region with a size of 2, the corresponding special decode enable register should be used instead of a generic one to save the rather limited generic ones for other decode ranges. Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: simplify espi_std_io_decode functionFelix Held
We can just return at all places where the ret variable was written before its value gets returned at the end of the function. Change-Id: Id87f41c0d9e3397879ac3d15b13179cca1a1263f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: make decode enable parameter uint32_tFelix Held
Since this is a bit mask applied to the raw value of a 32 bit register, this should be a 32 bit unsigned type. Change-Id: I9d9930963d8c827a84dc1f67e2f2fa8f95ab40f2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/common/espi_util: make reg parameter unsignedFelix Held
Th register number passed to the low level read/write functions should never be negative. Change-Id: I5d7e117b3badab900d030be8e69ded026d659f8a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-11soc/amd/stoneyridge/acpi: clean up global NVSFelix Held
Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge. This patch removes the unused fields. Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-11mb/google/zork: config ddi for dirinbozKevin Chiu
dirinboz does not support native HDMI, config DDI as below: DDI0: eDP DDI1: DP DDI2: DP BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: I9dffdf5654680e3c2c0b259ee82a471f8ff14f56 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11mb/google/zork: fix incorrect DRAM SPD table load for dirinbozKevin Chiu
BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: Ia736b0f25824eebe4ef25a11646f82963611e3b3 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11mb/google/zork: move USB OC pin mapping to trembyle base boardFelix Held
The USB OC pin mapping is similar enough to move it to the base board and just have two overrides for trembyle, which is based on an older version of the schematics, and one override for woomax, which doesn't use one USB port. BUG=b:163081097 Change-Id: I7e305d7e6f51d7ef7a4c699e3bacc6bcd699d2f2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-11nb/intel/sandybridge/raminit: Add commentsPatrick Rudolph
Add comments found when testing ECC scrubbing code. This is a cosmetic change. Change-Id: I7975f6070c2002930eec407a6b101a1295495b25 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40947 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11nb/intel/sandybridge/raminit: Fix ECC scrubPatrick Rudolph
The scrubbing method was never correct nor tested. Fix that by observations made on mrc.bin. Tested on HP Z220 with ECC memory and Xeon E3 CPU: The whole memory is now scrubbed. Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40721 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11nb/intel/sandybridge/raminit: Add ECC debug codePatrick Rudolph
* Add ECC test code when DEBUG_RAM_SETUP is enabled * Move ECC scrubbing after set_scrambling_seed() to be able to observe what has been cleared in the test routine. If clearing happens before set_scrambling_seed the data is XORed with a different PRN. Data read from memory will look random instead of all zeros. * ECC scrubbing must happen after dram_dimm_set_mapping() The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In normal mode the ECC bits are calculated and stored on write transactions. * Move method out of try_init_dram_ddr3(). This satisfies point 2 and point 3 of the list above. Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10mb/google/volteer: Pull up GPP_D16 instead of driving itCaveh Jalali
The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to GPP_D16 but there is a RTS5261 requirement to pull up this pin and not drive it at power on. We can meet this requirement without breaking other boards by changing GPP_D16 to be a no-connect with an internal pull up. Other boards use this signal as an enable input, so changing this to pull up is OK. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-10mb/google/volteer/var/terrador: Update gpio settings for Proto2David Wu
Based on latest schematic and gpio table of terrador, update gpio settings for terrador Proto2. BUG=b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I64b4fcbaabc487206d14d794af319e6df6f99581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-10mb/tgl: Enable SaGv for TGL-UP3 RVPShreesh Chhabbi
BUG=none BRANCH=none TEST=Build and boot TGL-UP3 RVP with QS silicon successfully. Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43276 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-10superio/ite: allow 24 MHz clock for external sensor interfaceMichael Büchler
The interface selection register of the environment controller (EC) gives the choice between "Internal generated 32 MHz" and "24 MHz" for the "SST/PECI Host Controller Clock Selection". Previously the chip was always configured for the 32 MHz clock. Add an option that can be set from devicetree.cb to allow using the 24 MHz clock. Without this setting the automatic fan control on an Acer Aspire M3800 was slow to respond to temperature changes. Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/44166 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-10superio/ite: configure EC for fans to full at thermal limitMichael Büchler
This applies to the automatic fan control mode of the environment controller (EC). Previously the affected bit was always cleared while the default value is 1 according to datasheets. Add a variable that can be set per mainboard in devicetree.cb. In the IT8783E datasheet that bit is marked as reserved. Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Change-Id: Ie74102ac0d54be33558c161c9c84594d121772b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-08-10mb/lippert: Put files under variants/Angel Pons
This isn't reproducible for some reason, but it is relatively simple. Change-Id: I507229be71ac2c589c7ecd81495d38ce363d26a7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43275 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-10mb/lippert: Unify mainboardsAngel Pons
Do it quick and dirty but in a reproducible manner. Variants will be set up properly in subsequent commits. Tested with BUILD_TIMELESS=1, both Lippert FrontRunner-AF and Toucan-AF remain identical. Change-Id: I71ff50099787e7806a9ab67429890a1c77061929 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43274 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-10soc/intel/apollolake: Rename UART irqsPatrick Rudolph
Use the same names as on other intel socs. Will be used in intel common uart driver. Change-Id: Ia418fefb3f925fe4d000683b5028682cf0b68a9b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/apollolake: Add irq.hPatrick Rudolph
Move defines from soc_int.asl to soc/irq.h. The common code uart driver expect it to exist. Change-Id: I000a041120daa8cbe1ca4e4aab48a206bb3e9245 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/cannonlake/acpi/serialio.asl: Don't advertise unavailable devicesPatrick Rudolph
On PCH-H the I2C4 0:19.0 device isn't usable and thus 0:19.1 and 0:19.2 can't be detected using standard PCI probing. Remove I2C4, I2C5 and UART2 from generic ASL code on PCH-H platforms that advertise its PCI conformance by the _ADR attribute. Change-Id: I89f9ab7d4afb2e7d1b1e24d072adf99e0da6fecf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10soc/intel/common: Include Alder Lake SATA controller device IDsSubrata Banik
Document Number: 619501, 619362 Change-Id: Id3440b415ca80edebb6880b8b48f6094ebea4ae4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-09soc/intel/{icl.tgl,jsl}: Remove SMRAM register programmingAamir Bohra
SA SMRAMC register PCI offset 0x88 is deprecated for ICL, JSL and TGL. Removing the register programming for these platforms. The write to this register does not take effect and remains configured to 0, even when programmed. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-083rdparty/intel-microcode: Update submodule to 20200616 releaseAngel Pons
Change-Id: Ia250765e2cb81d6a39ad00ebbab20e7b87fa42d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43758 Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt socJonathan Zhang
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to VT-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable VT-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. [CB:44075] was submitted to enable it in coreboot. e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel not working. There is a change in IIO UDS Hob. TESTED=booted YV3 config A, and rebooted it. Access the target OS remotely. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-08mb/google/zork/trembyle: comment why USB OC pin mapping is differentFelix Held
Change-Id: I68b7529733e604ac45919a54e094be7eeb044458 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-08soc/intel/skylake: Enable CIO depending on devicetree configurationFelix Singer
Currently, CIO gets enabled by the option Cio2Enable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the CIO controller. All corresponding mainboards were checked if the devicetree configuration matches the Cio2Enable setting, and missing entries were added. Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08soc/intel/skylake: Enable SA IMGU depending on devicetree configurationFelix Singer
Currently, SA IMGU gets enabled by the option SaImguEnable, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SA IMGU controller. All corresponding mainboards were checked if the devicetree configuration matches the SaImguEnable setting, and missing entries were added. Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08soc/intel/skylake: Add IMGU definitions to pci_devs.hFelix Singer
Change-Id: Iee7393ae7e2aca94151c242894c64ac902f4d437 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08soc/intel/skylake: Enable SDXC depending on devicetree configurationFelix Singer
Currently, SDXC gets enabled by the option ScsSdCardEnabled, but this duplicates the devicetree on/off options. Therefore, depend on the devicetree for the enablement of the SDXC controller. All corresponding mainboards were checked if the devicetree configuration matches the ScsSdCardEnabled setting, and missing entries were added. Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-08-08mb/asrock/h110m: remove unused Device4Enable from devtreeMaxim Polyakov
This option has been removed from the parameters structure for Intel Skylake CPU (commit 9c1c009). Change-Id: I9dc6649ad693d18fdc85046ebbcc730a17fed0bf Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 23:16:49 +0000