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2021-01-31soc/amd/cezanne: add soc/cpu.h with CPUID define for Cezanne A0 steppingFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b6d8b0c5ff5e58f6ab487d9fe724534f0108f83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30sb/intel/ibexpeak: Drop invalid ME finalisation functionAngel Pons
Was copied from bd82x6x and none of the PCI IDs matches that of Ibex Peak (PCI_DID_INTEL_IBEXPEAK_HECI1 = 0x3b64). Remove the code. This allows dropping the me_8.x.c dependency, which never made sense. Change-Id: I54df1e080048c0599dbee687ec617fb724cb6634 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-30soc/intel/broadwell/pch: Drop some `config_of` usesAngel Pons
There's no need to die here. Also simplifies merging with Haswell. Change-Id: I3d4bc79b32279180442dbc82126e297f11f1fb80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-30soc/intel/broadwell: Move `ramstage.c` to PCH scopeAngel Pons
The remaining code in this file is PCH-specific. Change-Id: I0e4924e680db9c25aeb222bdd478b3282a77b34f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49946 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel/broadwell: Make `broadwell_init_pre_device` staticAngel Pons
This small function is only used in one place. Change-Id: Ieccdca60fb7837b6406a6b2fd7ebae86958a1afe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49945 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel: Replace `SA_PCIEX_LENGTH` Kconfig optionsAngel Pons
Use the existing `MMCONF_BUS_NUMBER` and `MMCONF_LENGTH` symbols. Change-Id: I88dcc0d5845198f668c6604c45fd869617168231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-30device: Drop `mmconf_resource_init` functionAngel Pons
All uses of `mmconf_resource_init` have been replaced in previous patches with `mmconf_resource`, which uses Kconfig symbol values. Change-Id: I4473268016ed511aa5c4930a71977e722e34162a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-30nb/intel/i945: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/gm45: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I635f3615f566502f79bbd81f9f743ce63bba3b1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49758 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/x4x: Define and use MMCONF_BUS_NUMBERAngel Pons
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Moreover, the ASL reservation for MMCONFIG was only for 64 busses. Change-Id: I7366a5096aacd92401535be020358447650b4247 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49759 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/pineview: Define and use MMCONF_BUS_NUMBERAngel Pons
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhereAngel Pons
Bootblock enabling needs some special handling. Also, the definition of the `get_pcie_bar` function is incorrect for Ironlake, so remove it. With this patch, using 64 and 128 for MMCONF_BUS_NUMBER should work. However, it has not been tested. Using 256 busses should still work. Change-Id: Ic466ddc7b80f60af5cbff53583281440f02974c7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49761 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: Id88c18129bb773d979ad84bd0bb47188d74d4bc4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49762 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/haswell: Define and use MMCONF_BUS_NUMBERAngel Pons
Change-Id: I0d6338f763a78895b1ae14d1ab68253851b6c283 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49763 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel/broadwell: Define and use MMCONF_BUS_NUMBERAngel Pons
Note that ACPI MCFG generation reported too many busses. Change-Id: I5acd26bac675cc818df46f60887f90b76f4580a2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50034 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel/broadwell: Use common SMBus codeAngel Pons
Change-Id: I74b21bfde4b76ccb0d432b00c25095f708b1d761 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50030 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30device/Kconfig: Introduce MMCONF_LENGTHAngel Pons
This is necessary because ASL Memory32Fixed values cannot contain operations, even if they can be evaluated to constants. Add a sanity check in pci_mmio_cfg.h to ensure consistency with MMCONF_BUS_NUMBER. Change-Id: I8f0b5edf166580cc12c1363d8d6b6ef0f2854be9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50033 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel/{baytrail,broadwell} Fix building with refcode blobsAngel Pons
Because the refcode blobs are not redistributable, refcode.c is not build-tested. Commit 6271dd8459 (soc/intel/baytrail,broadwell: Use resume_from_stage_cache()) broke building with refcode blobs. Fix a variable redeclaration error by swapping the order of the code, and use consistent names for the variables. Change-Id: Ic8dda8d35086d977b536686e8c80b7961c37860c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-30sb/intel/bd82x6x: Clean up early_thermal.cAngel Pons
Use proper types in readXp functions, define `PCH_THERMAL_DEV`, clean up comments a bit, and use `RCBA32_AND_OR` instead of read32/write32. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: I95e054d6e52706e06e313068e61484f6cb9a64e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50038 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30nb/intel/ironlake: Use RCBA macrosAngel Pons
Use defined RCBAx macros over readX/writeX calls. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I87cae75268ef5f329001706e4771e98653d40cd1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50037 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30libpayload/arm*: Add 64bit memory access primitivesPatrick Georgi
Add read64 and write64 for consistency with x86. BUG=b:178785769 Change-Id: I342e3a23201d0b804ea5ecfe47ee3e4bb516de4c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-30mb/amd/majolica: Add an empty bootblock function to handle GPIOZheng Bao
Change-Id: I35da3812a424ea1beef86d043a756a87e6afdaa3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50117 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30util/testing/Makefile.inc: Fix up license headerAngel Pons
Drop unnecessary leading empty lines in comment. Change-Id: Idc0f9d1548336dc2df2d59b18af8d717efa60b68 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-01-30mb/amd/majolica: Add an empty function of mainboard bootblockZheng Bao
Change-Id: I985405b51c81d1e5a3a593bfb759e9850beb2244 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-30drivers/intel/fsp2_0: factor out and improve UPD signature checkFelix Held
In case of a mismatch print both the UPD signature in the FSP and the expected signature and then calls die(), since it shouldn't try calling into the wrong FSP binary for the platform. Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I469836e09db6024ecb448a5261439c66d8e65daf Reviewed-on: https://review.coreboot.org/c/coreboot/+/50090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-30soc/amd,intel: Drop leftover GNVS includesKyösti Mälkki
Change-Id: Ia55d53a9a40846db335aabbe4df8e87f6172f712 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-30soc/amd/stoneyridge/southbridge: replace southbridge prefix with fchFelix Held
This aligns the function names with Picasso and Cezanne. Also move the fch_* functions in the header file in the order they get called. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49db8021edae5e537f043bf52eea1be54dc46eca Reviewed-on: https://review.coreboot.org/c/coreboot/+/50124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-30soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP callsFelix Held
Cezanne doesn't have ACPI support yet, but in this case the function always returns 0, so it can already be used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1f5e1f31bf1e52988fcef90daf7b93169e21cbb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50126 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/amd/picasso/chip: add missing acpi/acpi.h includeFelix Held
acpi_is_wakeup_s3() is defined in acpi/acpi.h Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53916cd15bb28484eb06be4d43f26152de159391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50125 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30soc/intel/common/block: Create PCIE related macrosSubrata Banik
Add generic PCIE RP related macros for SoC layer to use. Change-Id: I84d02daded5cfe11120f099dc80c00ac0ec795f1 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-30soc/intel/alderlake: Remove pch.h from SoC directorySubrata Banik
Remove unnecessary include of soc/pch.h from - bootblock/pch.c - bootblock/report_platform.c - bootblock/uart.c Define PCIE_CLK_XXX macro inside chip.h for mb/devicetree.cb to consume. Change-Id: Ic08ef586d4590462434ba2c64e21dd802ccc6800 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50132 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-30mb/intel/adlrvp: Remove unnecessary whitespaceSubrata Banik
Change-Id: I46af3e789de10ca6951b9e17f286c094c08a477f Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-30soc/amd/piasso/data_fabric: rename data_fabric_read_reg32Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib1b4da8f5daac2bae5e54f213accda03e121297d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-30soc/amd/picasso/data_fabric: factor out indirect address/index writeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id7bda8843a5ed0775424a056a05a6c4cb8269e49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-29soc/amd/cezanne: add empty ramstage FCH supportFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-29soc/amd/picasso/fch: replace southbridge prefix with fchFelix Held
Also move the fch_* functions in the header file in the order they get called. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b6c6ad744b26f8488015c38a84d7e21c7d7687a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50093 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29soc/amd/cezanne/chip: add FSP silicon init driver callFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3dea23de0c7ce2fca4382e9fd4ec88aecaa55fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50092 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29docker/coreboot-jenkins-node: Add GNU parallelPatrick Georgi
Change-Id: I958e65f3c758e7e46d6b628a05009c1b4727d40a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50087 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29soc/intel: Remove duplicate call to acpi_wake_source()Kyösti Mälkki
With SOC_INTEL_COMMON_BLOCK_ACPI=y the call was made twice, possibly in the order: common/block/acpi.c: acpi_wake_source() common/acpi_wake_source.c: acpi_wake_source() In this order later call would reset pm1i and gpei in GNVS. Remove the implementation in block/acpi.c and rename existing acpi_wake_source.c to block/acpi_wake_source.c. Change-Id: I74fdae63111e3ea09000d888a918ebe70d711801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-29mb/emulation/qemu-q35: Consolidate host bridge definitionsAngel Pons
Move all Q35 register definitions into the q35.h header. Note that real hardware does not have EXT_TSEG_MBYTES, because it is QEMU-specific. Change-Id: I4c86ac0bb05563dee111b9b4a4a71c1c31198acd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50024 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29mb/emulation/qemu-q35: Rename headerAngel Pons
The emulated northbridge is Q35. GM35 does not exist. Tested, still boots. Change-Id: Id8e114a43b54b71087d09d143176ed94329ab7af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29mb/purism/librem_bdw: Turn comments into codeAngel Pons
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: Iec84fc2b43c23ea85f5cf13d9f0bace73e448c97 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-29soc/intel: Drop CMEM from GNVSKyösti Mälkki
Already tagged as obsolete_cmem in <soc/nvs.h> files. Change-Id: I8ba2a79f866fa07f1b4ae7291c72c91db5027911 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50043 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-29soc/intel/baytrail,broadwell: Use resume_from_stage_cache()Kyösti Mälkki
Change-Id: Ie7b8bd02c3bb92c6ab9071941abbd90afef82601 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-29stage_cache: Add resume_from_stage_cache()Kyösti Mälkki
Factor out the condition when an attempt to load stage from cache can be tried. Change-Id: I936f07bed6fc82f46118d217f1fd233e2e041405 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-29mb/emulation/qemu-q35: Rename PICF to PICM in ASLKyösti Mälkki
Change-Id: I395056a164b6597b6fb3dfda0d85f9a0374cd893 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-29ACPI: Do minor improvements on GNVSKyösti Mälkki
Reorder the support functions to make a bit more sense, allocations happen first. Add related comments about the bootstate these are to be called from. Change-Id: Ie6d66f6e4c30519dee4520f6e9dec3c8c678ab57 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-29drivers/intel/fsp1_1: Drop s3_resume parameter to load_vbt()Kyösti Mälkki
Change-Id: Iaba88026906132b96fe3db3f05950df0e7eef896 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-29intel/fsp1_1: Declare fsp_load() as staticKyösti Mälkki
The function has only one local call-site. Change-Id: I623953796e6cd3a8e5b4f72293d953b61f14a5a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49999 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 23:04:34 +0000