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2021-01-28mb/hp/abm: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'Build/dsdt.dsl' are identical. Change-Id: Ie93dd1f6de1357cb3f448ed79a33b688abd91731 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/asrock/imb-a180: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' are identical. Change-Id: I100b6c596d8a1dd74f096f71675026618da32e6f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/amd/thatcher: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: If1869d091f9c78db7e308143d96b5d3046510ac8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46152 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/amd/parmer: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I563cd549858429049223677ebc503f9c9304baa0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46149 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/amd/padmelon: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I88c1c907916c3de51f6b3b72f7a49e90a1b1a383 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46148 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/cezanne/Kconfig: move selections in alphabetical orderFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I99ac82b717e5efb6521040e88a3cfa5f09910be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50010 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/picasso: allow USB_PD port setting overrideChris Wang
Allow to override the RFMUX setting if the board does not use PD chip. BUG=b:177389383 BRANCH=none TEST=Build; Check the USB_PD port been override. Change-Id: Idd559b67668846805005a6e00f5a84655310f348 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49932 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28util/lint: Add test for documentation in util dirsMartin Roth
Make sure that any new directories added to the util directory get documentation added. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8bb415c72cf05b91c84f0a945d7767134a74c44c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48967 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28Update util.md documentationMartin Roth
This is the new output of the util_readme.sh script. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia46924474f75692192ef4b52aab714f5071f9534 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48966 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/biostar/a68n_5200: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: I122f27bf7e7b809802efdbd443694b3d6e715108 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28mb/elmex/pcm205400: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are same. Change-Id: I1cec4049adac74270641736709774156628b2539 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28treewide: Remove unused #includes of spi_winbond.hDaniel Gröber
We want to add some function declarations as static_testable to this header but including it in a .c file outside of tests will yield a gcc warning like: error: 'function' declared 'static' but never defined [-Werror=unused-function] It seems these includes aren't necessary anyways so we just remove them. Change-Id: I17147136579140b94728ceb1c369b1348714bc53 Signed-off-by: Daniel Gröber <dxld@darkboxed.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-01-28cpu/intel/socket_LGA775: Align CAR DCACHE_RAM_BASE to SIZEArthur Heymans
This fixes a regression introduced by Commit 985821c (cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE) where the CAR base is not aligned to its size. Change-Id: If54cb178e86426e1491dda4047302632d876a8f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50029 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28docker/coreboot-jenkins-node: Add zephyr-sdk toolchainPatrick Georgi
There are efforts to replace Chrome EC with Zephyr. To ensure Chromebook specific Zephyr developments (that can eventually be built as part of a coreboot build just like Chrome EC now, and are built with coreboot-sdk) don't break with Zephyr's toolchain, add the toolchain to our builders so we can do some sanity checking. Change-Id: I645a298bc350ebe7651c08aea630bdc6b93856aa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-28util/docker: Split build into multiple partsPatrick Georgi
Take the test build entirely out of the image creation process. This also allows splitting up the build steps a bit, providing more break points in case some build/test fails. Change-Id: Ie05d4a09f79350fd3e5415430da1edbcb3bcb443 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28util/docker: Don't try to test-build non-existing crostools targetPatrick Georgi
Change-Id: Id6afbff1fd91744da3ba1d5e3e9aa339c46b29b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28gitconfig/test: Adapt test to current tree layoutPatrick Georgi
The test expects a README file to exist under revision control, but we converted it to markdown, together with a rename over 2 years ago in commit ee8780eb7880477. Change-Id: I7768e116a10cb373ca35fa1c874a5949dabaa111 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28mb/system76/oryp5: Fix up DSDTPatrick Georgi
We started depending on dsdt_top.asl in dsdt.asl but this newly added board wasn't adapted yet, so have it catch up. Change-Id: If00280a33fd9e5c3ef1b3d07c41e81ed18013714 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50021 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/intel: Remove selection of ME_REGION_ALLOW_CPU_READ_ACCESSSridhar Siricilla
The patch removes selection of ME_REGION_ALLOW_CPU_READ_ACCESS config in the SOC_INTEL_CSE_LITE_SKU Kconfig definition since the ME_REGION_ALLOW_CPU_READ_ACCESS Kconfig selection is done based on the SOC_INTEL_CSE_LITE_SKU Kconfig in the southbridge/intel/common/firmware/Kconfig. TEST=Verified build for JSL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I9969cce0d433657dd27bab71c132356fb28a35c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50012 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28southbridge/intel: Define default value for ME_REGION_ALLOW_CPU_READ_ACCESSSridhar Siricilla
The patch defines default value for ME_REGION_ALLOW_CPU_READ_ACCESS config. It sets value 'y' if CSE Lite SKU is integrated, otherwise value 'n'. The config ME_REGION_ALLOW_CPU_READ_ACCESS ensures host has read access to ME region when the LOCK_MANAGEMENT_ENGINE is enabled and CSE Lite SKU is integrated. TEST=Verified build for JSL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I680a23e27ae2bf4d85bf919134c47882f308af56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49891 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/emulation/qemu-q35: Solve lint-001 errorFrans Hendriks
lint-001-no-global-config-in-romstage error on D0F0_PCIEXBAR_LO. DOF0_PCIEXBAR_LO is defined in bootblock.c and romstage.c. Place D0F0_PCIEXBAR_XX in local gm35.h. BUG = N/A TEST = Build and boot QEMU x86 q35/ich9 Change-Id: Ia5ac9eb797de996186282193647313b9f7b42624 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
2021-01-28xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devicesJohnny Lin
The values can be used during SMBIOS type 16 creation. Tested=On OCP Delta Lake, dmidecode -t 16 to verify. Handle 0x000A, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: Single-bit ECC Maximum Capacity: 1146 GB Error Information Handle: Not Provided Number Of Devices: 6 Change-Id: Id8f92dc96a7a3eb2e6db330adda98a7fe6d516c8 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28util/amdfwtool: Add "all" target to MakefilePatrick Georgi
The test-tools make target requires it. Change-Id: I20819f8d587e6b3a472cdc32751e9edf505d5ba6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28docker/coreboot-sdk: clone coreboot submodules when doing test buildPatrick Georgi
Change-Id: I2315beda31bdc8edc92d21b6665eb5ebd07da2e6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-28mb/google/dedede/var/galith: Add Wifi SAR for convertiblesFrankChu
Add wifi sar for galith Using convertible mode of fw config to decide to load custom wifi sar or not. BUG=b:176206495 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Cq-Depend: chromium:2649378,chrome-internal:3559387 Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I0f9a7ddedef550317da4bf798317619ffd1fa979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-28mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematicsSubrata Banik
1. GPP_E5 => Remove unused GPIOs 2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-28mb/google/parrot: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: Ie802b540cea13000227c969bbc262f034d1b6b84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-28soc/amd/common: Handle I2C resource only if base address is definedZheng Bao
Change-Id: I767ad58f442bc5561bda4dd1de2d9593c8434615 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-28mb/google/asurada: Improve boot time by raising little CPU frequencyYidi Lin
Raise little CPU to 2GHz at romstage to improve boot time. BUG=b:177389446 TEST=observe boot time by `cbmem` Before: 1,062,359 us After: 907,458 us Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I723a916d7f708627525ef11e3c5ea0b381f269aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/49935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28cpu/intel/microcode: Add caching layer in intel_microcode_findPatrick Rudolph
Cache the found microcode for faster subsequent accesses. Change-Id: Ic40d57964600f8f20ddb26c7d1691b043fd89f29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49896 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/mediatek/mt8192: Implement dram all channel calibrationHuayang Duan
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I62cc654d5a6b861f72eec66e09d24483b993f0e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28soc/mediatek/mt8192: Add mt6315_romstage_initYidi Lin
Initialize pmif_arb in romstage. BUG=b:177389446 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I3ffe7277c9ecb04269c832693d42799ba1711384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28soc/mediatek/mt8192: Add function to raise the CCI frequencyWeiyi Lu
Implement mt_pll_raise_cci_freq() in MT8192 to raise the CCI frequency. Usage: mt_pll_raise_cci_freq(1400UL * MHz); Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I084cd7888b1dcfdeaef308b8bb3677d034497a30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-28mb/google/dedede/var/sasuke: Configure GPP_G7 as nativeSeunghwan Kim
Configuring GPP_G7 as NC causes SD card detection issue on sasuke. So we'd like to remove the GPP_G7 override and keep the baseboard configuration as native function (SDIO_WP). BUG=b:175831709 BRANCH=firmware-dedede-13606.B TEST=Built and verified SDR104 SD card operation on sasuke Change-Id: If73337b482f04fd263caaa6fed0e54aa87bd876e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-28bayhub bh720: Factor out common HS200 init codeAngel Pons
Except for one debug print in sarien, both functions are identical. Move them to driver code to avoid unnecessary redundancy. Change-Id: I82635a289e3c05119eab4ee1f7a6bf3a8a1725c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-28drivers/elog: Correct code styleFrans Hendriks
lint report errors Solve the POINTER_LOCATION errors BUG = N/A TEST = N/A Change-Id: I65926abd6bbaff1efce39efad9ec92c4f364b533 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49971 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28cpu/intel/common/fsb.c: Correct code styleFrans Hendriks
lint report warning Solve the RETURN_VOID BUG = N/A TEST = N/A Change-Id: I3b8088494049b5c3244531a4a77af4153edbdff4 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28cpu/amd/agesa/family15tn/fixme.cFrans Hendriks
lint report errors and warnings Solve the next issues: - BRACES BUG = N/A TEST = N/A Change-Id: I27a712ec93c216fc3aa836baa53d6e2f2e68d3a3 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-01-28mb/google/asurada: Add config for spherionYu-Ping Wu
BUG=b:178440482 TEST=emerge-asurada coreboot BRANCH=none Change-Id: Ica09b73f97509db065c93c6be757c0d77c9b7a87 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-01-28mb/emulation/qemu-i440fx: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I9157d9fc61339792dbbc45e82e1cb04fa51c6aae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46077 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/emulation/qemu-q35: Convert to ASL 2.0 syntaxElyes HAOUAS
Generated 'build/dsdt.dsl' files are identical. Change-Id: I4e0f64def6c4c712793d3b2ede99dd74f9046fcb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46163 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/google/volteer: Add GL9755 support to DrobitWayne3_Wang
Add the GL9755 support to drobit and also fixes the S0ix can't into C3~C9 problem BUG=b:174348200 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com> Change-Id: I52df6b2cdebfaf8a5eb010c4af1a2cf3d918f5e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49921 Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28mb/google/brya: Add variants overridetree.cb path and remove unused registersEric Lai
Add variants overridetree.cb path remove unused registers BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2940332044aa4c2de6d58f5d0d2a2a7c1b2c3478 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-28mb/google/zork: add MST details to trembyle devicetreeShiyu Sun
Added device hid info to the MST RTD2141b device on trembyle. BRANCH=zork BUG=b:147402710 TEST=Build and flash BIOS image, see 10EC2141 appears under /sys/bus/i2c/devices Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Change-Id: I97a67f9dbc31cd788d579252d7d355b24d97ca30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2021-01-28soc/intel/xeon_sp/skx: Add soc_acpi_nameMarc Jones
Add the soc_scpi_name to the soc pci_ops. This is used by ACPI table generation and required by the intel common XHCI device. Change-Id: Idc09d53f14dfb1e42f904dfd4e87e8c09e155135 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2021-01-28mb/system76/oryp5: Add System76 Oryx Pro 5Tim Crawford
Tested with TianoCore payload (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both NVMe ports - SATA port - All USB ports - Webcam - Ethernet - Integrated graphics - Internal microphone - S3 suspend/resume - Flashing with flashrom - Booting to Ubuntu Linux and Windows Not working: - Discrete/Hybrid graphics - Internal speakers These two require new drivers to work correctly, which will be added and enabled later. Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402 Signed-off-by: Tim Crawford <tcrawford@system76.com> Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28arch/x86/smbios: Update SMBIOS type 16 Extended Maximum CapacityTim Chu
Update Extended Maximum Capacity field in SMBIOS type 16 so that maximum dimm size can be over 2TB. Tested=Execute "dmidecode -t 16" to check maximum capacity is over 2TB. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I61901c815f9d0daae102e5077a116c0de87240ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/49828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-28acpi/acpigen.c: Remove unused and incorrect functionsJakub Czapiga
acpigen_write_name_zero() and acpigen_write_name_one() are not implemented correctly, and are not used anywhere. Drop them in favor of the more flexible acpigen_write_name_integer() function. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I116fd41624a8e8b536d18d747f21d3131b734dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/49834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28ACPI: Move include for <vc/google/chromeos.asl>Kyösti Mälkki
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Separate ChromeOS NVS in ASLKyösti Mälkki
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 14:55:49 +0000