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2016-10-25arch/x86/acpigen: Add support for _DSM method generationFurquan Shaikh
Add acpigen_write_dsm that generates ACPI AML code for _DSM method. Caller should provide set of callbacks with callback[i] corresponding to function index i of DSM method. Local0 and Local1 should not be used in any of the callbacks. BUG=chrome-os-partner:57846 Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17090 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25drivers/i2c/generic: Re-factor SSDT generation codeFurquan Shaikh
1. Export i2c_generic_fill_ssdt to allow other device-specific i2c drivers to share and re-use the same code for generating AML code for SSDT. In order to achieve this, following changes are required: a. Add macro I2C_GENERIC_CONFIG that defines a structure with all generic i2c device-tree properties. This macro should be placed by the using driver at the start of its config structure. b. Accept a callback function to add any device specific information to SSDT. If generic driver is used directly by a device, callback would be NULL. Other devices using a separate i2c driver can provide a callback to add any properties to SSDT. 2. Allow device to provide _CID. BUG=chrome-os-partner:57846 Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17089 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-25arch/x86/acpigen: Add more functions to ACPIGEN libraryFurquan Shaikh
1. If (LEqual (Op1, Op2)) 2. ToBuffer (src, dst) 3. ToInteger (src, dst) 4. Buffer (n) { op1, op2 .... } 5. Return ( ) BUG=chrome-os-partner:57846 Change-Id: I24fe647c690b2dd4849f0c53b2672ac7a2caa2de Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17088 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25mainboard/google/reef: Add PowerResource for ELAN touchscreenFurquan Shaikh
Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:55988 Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-25soc/intel/apollolake: Implement GPIO ACPI AML generating functionsFurquan Shaikh
Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio BUG=chrome-os-partner:55988 Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17082 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-25drivers/i2c/generic: Enable support for adding PowerResource for deviceFurquan Shaikh
Add support to allow a device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: 1. Reset GPIO - Optional, GPIO to put device into reset or take it out of reset. 2. Reset delay - Delay after reset GPIO is de-asserted (default 0). 3. Enable GPIO - Optional, GPIO to enabled device. 4. Enable delay - Delay after enable GPIO is asserted (default 0). BUG=chrome-os-partner:55988 Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17081 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-10-24mainboard/emulation: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I627338505fe1273366bc8f6f528d829b3162b371 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16916 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24mainboard/amd/tilapia_fam10: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I7515288190ca57a321fb8ffe57a1181b638c336a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16978 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24mainboard/amd/serengeti_cheetah*: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I2fae9e02e2fccaff97f2441fd17f8960e8ab9786 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16975 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24mainboard/amd/mahogany: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: Ife9c0b8a1ab55fe683c88e34239d7f5806e1ff9b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16971 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24mainboard/amd/lamar: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I765814450b82755f84c010f63bc8f919bb0cd4c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16970 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24nb/i945/Kconfig: select the correct VGA_BIOS_ID for 945GCArthur Heymans
Change-Id: I48ae27c5460020b9118e6ade1a3e610b542999c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17040 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-24RISCV: Clean up the common architectural codeRonald G. Minnich
This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload, entering main() with no supporting assembly code for startup. The Harvey port is not complete so it just panics but ... it gets started. We provide a standard payload function that takes a pointer argument and makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual memory setup code. We now use the _stack and _estack from memlayout so we know where things are. As time goes on maybe we can kill all the magic numbers. Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17058 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-24arch/x86/acpigen: Add support for interacting with GPIOsFurquan Shaikh
Since reading/toggling of GPIOs is platform-dependent task, provide an interface with common functions to generate ACPI AML code for manipulating GPIOs: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio Provide weak implementations of above functions. These functions are expected to be implemented by every SoC that uses ACPI. This allows drivers to easily generate ACPI AML code to interact GPIOs. BUG=chrome-os-partner:55988 Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17080 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-24arch/x86/acpigen: Add new functions to acpigen libraryFurquan Shaikh
Add functions to support generation of following AML operations: 1. PowerResource 2. Store 3. Or 4. And 5. Not 6. Debug 7. If 8. Else 9. Serialized method BUG=chrome-os-partner:55988 Change-Id: I606736b38e6a55ffdc3e814b6ae0fa367ef7595b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17079 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-24arch/x86/acpigen: Clean up acpigen libraryFurquan Shaikh
Instead of using hard-coded values for emitting op codes and prefix codes, define and use enum constants. With this change, it becomes easier to read the code as well. BUG=chrome-os-partner:55988 Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17078 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-24drivers/i2c/generic: Return correct name for acpi_nameFurquan Shaikh
Return config->name if it is not NULL. BUG=chrome-os-partner:55988 Change-Id: I9ae229949b73de6f991383daae8d962d6cf457a7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17077 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-21mainboard/amd/db-ft3b-lc: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I2a3bf53e6bc4084305238fa176ae46161da4be8f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16967 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-21mainboard/amd/bimini_fam10: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I4e628cbe11da32d291c4b8e4c7be91e9b0a86ad9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-21mainboard/amd/bettong: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I137b27ffb0e54a9ca6b0bd3a454b1d99b3e1c22b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16907 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-21marvell/mvmap2315: Compose BOOTBLOCK regionDaisuke Nojiri
This patch adds a Makefile rule for mvmap2315 to install a BDB and bootblock code in the BOOTBLOCK region. The resulting BDB has a header and data both signed by a RSA-4096 key. BUG=chrome-os-partner:57889 BRANCH=none TEST=emerge-rotor coreboot and examined the output binary. Booted coreboot.rom. Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/16747 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-213rdparty/vboot: update to latest master for rotor supportMartin Roth
This pulls in the bdb support for futility so that rotor can build. Change-Id: Icfa432fb840bea3e1616933ed02cf34a681fa3ce Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17061 Tested-by: build bot (Jenkins) Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2016-10-21Makefile.inc: Don't share amdfwtool between platformsMartin Roth
amdfwtool currently gets built for a specific size of ROM chip. This should be updated to be passed in on the amdfwtool command line, but until that's done, stop sharing the tool between builds. This caused a problem for abuild when we tried changing the default rom to one that used a 256KB rom chip. That wasn't large enough for all of the files included by amdfwtool on several platforms, causing build failures. Change-Id: Ib08f3283e5be956f995a4a416a70b12a32462882 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17070 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-20util/inteltool: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: Id42a2901cf76e6b867f62a752a38bbd6f6e5f54e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17059 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-20util/inteltool: Use tabs for indentsElyes HAOUAS
Change-Id: I9d27c276053c51021166f4b22d150060e415d08f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17025 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-20kunimitsu: Add choice to select FSP driverNaresh G Solanki
Add choice to select between FSP 1.1 & FSP2.0 driver to be used. Change-Id: Ied7eab6f4a2191e0bcf220cde5ca519a3c3e2d76 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-20mainboard/google/reef: add snappy variantWisley Chen
Create the initial Snappy variant which refers to the Reef device. Snappy, an Apollolake-platform, is deviated from reference board Reef. BRANCH=master BUG=None TEST=Built & booted Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6 Reviewed-on: https://review.coreboot.org/17043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-19intel/broadwell: "free" memory after usePatrick Georgi
While we stub out free(), tools like coverity scan have no idea, and it might change in the future. So free it. Change-Id: I1d93a6f45b64445662daa95b51128140ad0a87e2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1260716 Reviewed-on: https://review.coreboot.org/17055 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-10-19nb/i945/gma.c: use IS_ENABLED instead of #if, #endifArthur Heymans
Change-Id: Ib58126e1c9001ed679e161d6d06241fac762bdb3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17049 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19soc/intel/skylake: Allow selecting FSP driver in KconfigNaresh G Solanki
Enable mainboard Kconfig to select between FSP 2.0 & 1.1 driver to be used. If mainboard Kconfig selects MAINBOARD_USES_FSP2_0 the FSP2_0 driver is used else FSP1_1. Change-Id: I724aaa87c2b0b8f6ddb18f61af9c37176ef632f2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/17044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-19winbond/w83627ehg: Remove unnecessary valueElyes HAOUAS
Change-Id: I5f88f34d1c040ac6ed413cfaf8ceb45a358c117c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19nb/i945/raminit: Add fix for clock crossing for 800MHz FSB CPUArthur Heymans
The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect. The result is that 800MHz FSB CPUs now properly work with 667MHz RAM. Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas Elyes. Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17038 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19nb/i945/raminit: Add fix for 1067MHz FSB CPUsArthur Heymans
Previously the 945gc raminit only worked for 533MHz FSB CPUs. This extends the tRD_Mclks in drt0_table for other FSB speeds. The values are taken from the vendor bios of Gigabyte ga-945gcm-s2l. The result is that 1067MHz FSB CPUs now boot without problems. 800MHz FSB cpus still don't get past romstage. Change-Id: I13a6b97d2e580512155edf66c48405a153121957 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17034 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19util/msrtool: Use tabs for indentsElyes HAOUAS
Change-Id: Ib1aa4ad04dc8a584a751677aac5652cfa2e457df Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17031 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-19nb/gm45,x4x/gma.c remove writes to nonexisting FDI registersArthur Heymans
This removes writes to FDI related registers since there is no FDI link on these targets. This is likely a remainder from copying code from later targets. TESTED on Thinkpad x200 (gm45) Change-Id: Id67fdc999185fa184a9ff0e5c3fc9bced04131ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16993 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-19nb/i945,gm45,x4x/gma.c: fix unsigned arithmeticsArthur Heymans
This issue was found by Coverity Scan, CID 1364118. Change-Id: Iba3c0f4f952729d9e0987d928b63ef8b8fe8841e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16992 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-10-19nb/gm45,x4x/gma.c: Compute p2 in VGA init instead of hardcoding itArthur Heymans
According to: "Intel ® 965 Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller PR" the p2 divisor needs to be 10 when the dotclock is below 225MHz and 5 when its above 225MHz. Change-Id: I363039b6fd92051c4be4fdc88788f27527645944 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16991 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19mb/asus/kcma-d8,kgpe-d16: use MAINBOARD_DO_NATIVE_VGA_INITArthur Heymans
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG should only occur together with MAINBOARD_HAS_NATIVE_VGA_INIT. It seems to be used to just have to have the option to be able to select SEABIOS_VGA_COREBOOT. This patch makes these boards use MAINBOARD_DO_NATIVE_VGA_INIT and MAINBOARD_HAS_NATIVE_VGA_INIT to have it select SEABIOS_VGA_COREBOOT by default when SeaBIOS is chosen. Change-Id: If0a36af1883a3d62b16a61483733be981a85e5e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16981 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-19Select SEABIOS_VGA_COREBOOT when native graphic init is selectedArthur Heymans
Change-Id: I19db898a5e76bf9c151934c7979316fb3737e881 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16965 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-18rk3399: display: Use edid_set_framebuffer_bits_per_pixel() helperJulius Werner
This refactoring was already carried into RK3288 with commit 6911219 (edid: Add helper function to calculate bits-per-pixel dependent values) but it seems that the code for RK3399 was copy&pasted from it too early to pick this up. Fix that so that future Rockchip SoCs can copy&paste the right thing. Change-Id: I5050c58d18db38fffabc7666e67a622d4a828590 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17050 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-18arch/riscv: In trap handler, don't print SP twiceJonathan Neuschäfer
The stack pointer (SP) is already printed in print_trap_information. Don't print it again in handle_misaligned_{load,store}. Change-Id: I156cf5734a16605decc2280e54e6db3089e094a2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16996 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-18Revert "[WIP] console/Kconfig: Calculate COM port base addresses only on x86"Ronald G. Minnich
This reverts commit 2c8f3bd91b54e85b4d2e24894ee8bbbfb9ad8a31. I mistakenly commited a WIP, sorry. Change-Id: I3c66c688dbfd903ecf5303abcdf6b5ded84585c7 Reviewed-on: https://review.coreboot.org/17028 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-18northbridge/via/vx800: Convert 'for (;;)' to 'die'Elyes HAOUAS
Change-Id: I3f99190401d8df1415328da9c3b928194593901c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16989 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-18mainboard/google/reef: Configure PERST pin for reef DVTVaibhav Shankar
Configure GPIO 122 as PERST on DVT. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:55877 TEST=S0ix functional on DVT Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Change-Id: Iab18b2de621a1a9226c78493f6defa15081db875 Reviewed-on: https://review.coreboot.org/17030 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-17libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaultsJulius Werner
Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914 Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17024 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-17libpayload: Replace majority of timer drivers with a generic oneJulius Werner
Currently every non-x86 platform supported by libpayload needs to provide its own timer driver. Most of the ones we have accumulated there look almost identical: For the frequency, return a preset constant. For the value, read a 32-bit register, possibly read another 32-bit register and shift+OR it with the previous one, then return that. Let's replace this with a single .c file that can easily handle all of those cases. Menuconfig convenience can still be maintained by providing several presets that select different defaults for the driver's configuration options (register address(es) and frequency). Removes an "enabled" check from Samsung MCT driver since coreboot always unconditionally enables that timer anyway. CQ-DEPEND=CL:344809 BRANCH=None BUG=None TEST=Booted Oak and Veyron, observed how dev-mode delay was still ~30s Change-Id: I61cb7d2ffd4902aa841c57f9afa9cd991f770acd Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Commit-Id: a036af6 Original-Change-Id: I9784e7c6aa5abd6d92478ea7ec1cf42c9a437546 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347749 Reviewed-on: https://review.coreboot.org/17023 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-17ec/lenovo/h8: fix whitespaces/tabsAlexander Couzens
Change-Id: Ib60061fa60e81e36234355aeecd6fefad8f5fed1 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/17037 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-10-17cbfstool: Fix typo in help textPatrick Georgi
Change-Id: Ic5a3be1128f2f9a53d21e0a2c577192962260df6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/17018 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-17util/cbfstool: Allow overwriting CBFS regions with raw data on requestPatrick Georgi
Add a --force/-F option and enable it for cbfstool write, where it has the effect of not testing if the fmap region contains a CBFS or if the data to write is a CBFS image. Change-Id: I02f72841a20db3d86d1b67ccf371bd40bb9a4d51 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-16soc/apollolake: Add soc core initRavi Sarawadi
Skip FSP initiated core/MP init as it is implemented and initiated in coreboot. Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767 Reviewed-on: https://review.coreboot.org/16587 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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