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2019-08-02soc/intel/icelake: Make use of common thermal code for ICLSubrata Banik
This patch ports CB:34522 and CB:33147 changes from CNL to ICL. TEST=Build and boot dragonegg Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34649 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/skylake: Make use of common thermal code for SKLSubrata Banik
This patch ensures skylake soc is using common thermal code from intel common block. TEST=Build and boot soraka Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-01soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registersDavid Wu
Clear the GPI Interrupt Status & Enable registers to prevent any interrupt storms due to GPI. BUG=b:138282962 TEST=Ensure that the Interrupt status & enable registers are reset during the boot-up when the system is brought out of G3, S5 & S3. Ensure that the system boots fine to ChromeOS. Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-31mb/google/hatch: Initialize SSD GPIOs in bootblockShelley Chen
Moving these to bootblock as we are seeing some instances where devices are rebooting into the recovery broken screen with the 0x5a error (no bootable storage device in system). This needed to be done for KBL platforms and never got transferred to hatch. Please reference https://review.coreboot.org/c/coreboot/+/23647 BUG=b:137681648 BRANCH=None TEST=Run autotest faft_bios and faft_ec suites Change-Id: I8cf09c26d77d890f5d0490709504e9edf485a93f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34484 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2Seunghwan Kim
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku. More fine-tuning will happen later. BUG=b:1704071 BRANCH=none TEST=build Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34397 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/intel/skl: Add C232 chipset and reorder IDsFelix Singer
This patch ... - adds the PCH ID for C232 chipset, - renames "Premium" chipset to "HM170" (because of same IDs), - reorders the Skylake-H PCH IDs ascending by hex values. Used documents: - Intel 332690-005EN Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31inteltool: Add GPIO support for Skylake-H chipsetsFelix Singer
PCH IDs: - H170, Z170, Q170, Q150, C232, QM170, HM170 Used documents: - Intel 332690-005EN Change-Id: I33bf67c0c9d8a5a079fcc78f24a43bc421b2910c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31drivers/crb: Add CRB driver for TPM2 supportChristian Walter
Add the Command Response Buffer which is defined in the TPM 2.0 Specs. CRB can be specified with MAINBOARD_HAS_CRB_TPM, even though it is actually SoC/SB specific. Change-Id: I477e45963fe3cdbc02cda9ae99c19142747e4b46 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-31src/drivers/intel/ptt: Add PTT SupportChristian Walter
Add function which checks if Intel Platform Trust Technology / Intel integrated TPM is enabled/active. Change-Id: If93bb5e1a3a59b5045f4e44359683876fb387a71 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34380 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31lib/bootmem: Prepare for OpenSBIPatrick Rudolph
Add a new bootmem memory type OpenSBI. It's similar to BL31 on aarch64. Required for OpenSBI integration. Change-Id: I5ceafd5a295f4284e99e12f7ea2aa4c6d1dbb188 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-07-31soc/intel/cannonlake: Enable FSP to use coreboot stack for cometlakeAamir Bohra
FSP v1263 for CML supports FSP to use coreboot stack. This change selects common stack config, that enables coreboot to support share stack with FSP. BUG=b:133398276 Change-Id: I4098a4374363ca6f3c86c396d097f9eabc9a28fe Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34130 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOCRichard Spiegel
Stoney Ridge is family 15h models 70h-7Fh, Merlin Falcon is family 15h models 60h-6Fh. Add changes based on config parameter SOC_AMD_MERLINFALCON to make the code backward compatible with Merlin Falcon. BUG=none. TEST=Tested later with padmelon board. Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33624 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/intel/common/block/lpss: Correct the PCI device referenceAamir Bohra
The initial implementation was assigning the devfn as PCI device reference directly which was incorrect. Change-Id: Iad57e9bc6b2acf1823ee38116aea8a93feece6f9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-31device: Constify `dev` argument to (probe|find)_resource()Nico Huber
Change-Id: I7abca61db61d2f2df149ca601631c45d8c4f342e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34613 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31util/release/genrelnotes: Emit more markdown-ish outputPatrick Georgi
It's better to format lists with bullet points. Change-Id: I503ef2dea9146d67c220236b8a5b64c2ba2d794f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34504 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31util/release: Make sure intel-microcode ends up in the blobs tarballPatrick Georgi
Change-Id: Ib41c196cf543070e237d240cf31e019c9b2bf339 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34503 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch/variants/hatch: Set PCH Thermal Threshold value to 77 deg CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=133345634 BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Hatch. Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/intel/cannonlake: Enable PCH Thermal Sensor configuration for S0ixSumeet Pawnikar
Enable PCH thermal sensor for dynamic thermal shutdown for S0ix state. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: I50796bcf9e0d5a65cd7ba63fedd932967c4c1ff9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34522 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31soc/intel/common/block: Enable PCH Thermal Sensor for threshold configurationSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE. Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33129 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/kukui: Enable config for coreboot displayYongqiang Niu
BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31521 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/octopus: Override DDI1 DDC SDA/SCL for HDMIWisley Chen
The device Dorp uses the variant Meep, and supports HDMI. -sku33 (HDMI) -sku34 (HDMI + keyboard backlight) -sku35 (HDMI + Touchscreen) -sku36 (HDMI + keyboard backlight + Touchscreen) BUG=b:136522841 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I59ba2e56cf2f83ca9d533454570bcdd39c0a2e7c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34509 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/octopus: Override VBT selection for DorpWisley Chen
For dorp HDMI sku, select VBT which enables HDMI output. -sku33 (HDMI) -sku34 (HDMI + keyboard backlight) -sku35 (HDMI + Touchscreen) -sku36 (HDMI + keyboard backlight + Touchscreen) Cq-Depend: chrome-internal:1502253 BUG=b:136522841 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I62262378f85bb899073ffac7804be876e649e429 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-07-30Documentation/releases/checklist: Add instructions for crossgcc sourcesPatrick Georgi
We keep a mirror in case any of the originals disappear, but we also have to remember to update it. Change-Id: Ib4be91d1d508d3d5dba7ace1d167d8e528d58b3d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-30soc/intel/cnl: Only print ME status one timeTim Wawrzynczak
There were two hooks in the boot state machine which dumped the ME status to the debug UART, which is unnecessary. Removed the hook for the BS_OS_RESUME_CHECK state, leaving just BS_PAYLOAD_LOAD, which is called before FspNotifyEndOfFirmware, as required. BUG=b:138463532 BRANCH=none TEST=Boot up, check cbmem to ensure the ME status messages are only printed one time. Change-Id: I86bc6e33de4096f33023730ffabb25715c985de0 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-30mb/google/hatch: Enable chipset_lockdown coreboot config for hatchSubrata Banik
This patch enables lockdown configuration for hatch family (hatch, kindred, helios and kohaku) BUG=b:138200201 Change-Id: Ia6dc90156dc76fde490b25cf833da3cf80f664f2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-30soc/intel/cannonlake: Allow coreboot to handle required chipset lockdownSubrata Banik
This patch disables FSP-S chipset lockdown UPDs and lets coreboot perform chipset lockdown in ramstage. BUG=b:138200201 TEST=FSP debug build suggests those UPDs are disable now. Change-Id: I7e53c4e4987a7b0e7f475c92b0f797d94fdd60f4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-07-30AUTHORS: Move src/acpi copyrights into AUTHORS fileMartin Roth
As discussed on the mailing list and voted upon, the coreboot project is going to move the majority of copyrights out of the headers and into an AUTHORS file. This will happen a bit at a time, as we'll be unifying license headers at the same time. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id3382d19088cba2703350339b0bd0cfb3c0e63b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-30soc/intel/cannonlake: Add new PCI IDsFelix Singer
* PCH IDs: H310, H370, Z390, B360, C242, HM370 * IGD IDs: Another variant of UHD-Graphics 630 * MCH/CPU IDs: Used at i3-8100 Used documents: * 337347-005 TESTED=Gigabyte Z390M Gaming Change-Id: I5be88ef23359c6429b18f17bcffbffb7f10ba028 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34600 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30mb/google/hatch: Add option to enable WiFi SAR configsFurquan Shaikh
This change adds a user selectable option to enable all WiFi SAR configs that apply to hatch. BUG=b:138177048 Change-Id: I4b72f90896841e7c556d4a1b8cdad8ca89d01021 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-07-30nb/amd/amdht: Use standard coreboot assertionsJacob Garber
The amdht code currently relies on an idiosyncratic ASSERT() macro, which actually doesn't do anything right now, and even it did would only print a janky error message. Replace this with the normal ASSERT() macro from <assert.h>. The default behaviour now is to print an error message but do nothing else, and failed assertions will only halt if you enable FATAL_ASSERT, in which case, well, you asked for it. Change-Id: I6db7565171a345f9afbc9fb37cff8fda58f942df Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1402076 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-07-30soc/intel/{broad,cannon,sky}: Fix possible out-of-bounds readsJacob Garber
There will be a possible out of bounds array access if power_limit_1_time == ARRAY_SIZE(power_limit_time_sec_to_msr), so prevent that in the index check. This issue was fixed for other cpus in commit 5cfef13f8d (cpu/intel: Fix out-of-bounds read due to off-by-one in condition). Based on the discussion for that commit, also remove the magic constant 28 in favour of the index of the last array element. Change-Id: Ic3f8735b23a368f8a9395757bd52c2c40088afa1 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229673 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-30vc/cavium/{bdk,include}: Clean up bdk_phys_to_ptr() callsJacob Garber
The bdk_phys_to_ptr() function converts a uint64_t address to a void * pointer. Judging by the comments, the old implementation had a check that would refuse to convert a null pointer, which required several workarounds when trying to convert the address 0 to a pointer. This isn't the case for coreboot though, which implements this function as a simple (void *) cast, so we can remove the old workarounds. Change-Id: I6537d1699e6726c1fb155d69a51e14da856232de Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1393962 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-30vc/cavium/bdk/libdram: Add array bounds checkJacob Garber
Ensure that best_en_idx is within bounds before accessing the _en array. Change-Id: Ifa6259e28875a8cf8199896bda7982370ccaa277 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1393971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-30vc/cavium/bdk/libdram: Remove unused assignmentJacob Garber
The total number of errors is only needed after a final tuning run at the end of this function, so we can remove this unneeded store for earlier runs. Change-Id: I62adb38ccba98d90bcf8ccd13998762b9b694111 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1393967 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-07-30mb/emulation/qemu-riscv: Protect CBFS from payload loaderPatrick Rudolph
The virt machine is special as it doesn't emulate flash and it puts the coreboot.rom at start of DRAM. The payload loader doesn't know about CBFS in DRAM and overwrites the CBFS while decompressing payloads, resulting in undefined behaviour. Mark the region as SRAM to make sure the payload won't overwrite the CBFS while decompressing. As payload is always decompressed to DRAM, it wouldn't touch SRAM memory regions. Change-Id: I36a18cb727f660ac9e77df413026627ea160c1e1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-29mb/emulation/qemu-riscv: Fix regressionPatrick Rudolph
Fix regression introduced in bd4bcab "lib: Rewrite qemu-armv7 ramdetect". The detected DRAM size is in MiB, thus needs to adjusted accordingly before passed to ram_resource. Wasn't seen earlier as everything works, except payload loading. Change-Id: I4931372f530e7b4e453a01e5595d15d95a544803 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-29configs: Add test-build for up squared with vboot enabledChristian Walter
It would be useful if we have at least one "new" board on which we actually built vboot, in order to notice if something breaks. Change-Id: I16c7867e3f0f4e1f2e6ae3918c30789e39881b85 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-07-29util/inteltool: Add H110 GPIO supportPavel Sayekat
Change-Id: I0ce22da3d201c2443bb5a7fcfd779c2c6ee71577 Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34602 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29Revert "src/security/vboot: Add option to skip display init with vboot 2.0"Christian Walter
This reverts commit 598af2e2c2785c00eb4290cdcefe1082b2a6f858. Reason for revert: This commit breaks every board with VBOOT enabled if the platform is apollolake, broadwell, skylake, baswell, baytrails or icelake. The reason is, that the SoC selects VBOOT_MUST_REQUEST_DISPLAY by default, and this has a dependency now on VBOOT_MAY_SKIP_DISPLAY_INIT. This will only be auto-selected if it is a CHROMEOS platform. Change-Id: I3872d9aa993326ded135d8a5d950d5b1b1eddf34 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34308 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29src/superio/nuvoton: Add support for NCT5539DPavel Sayekat
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015). Change-Id: I7e979bde53ce3dac1a4f74e7e51a3c6a0149051c Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33842 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29Revert "soc/intel/common: Set controller state to active in uart init"Christian Walter
This reverts commit 46445155ea21b0aa9106e12a00b9b1d89887a461. Reason for revert: Breaks coreboot. Either no UART working or the complete boot process stops. Platform: Intel Apollolake, tested on Up Squared Change-Id: If581f42e423caa76deb4ecf67296a7c2f1f7705d Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-29soc/qualcomm/qcs405: Handle invalid QUP and BLSPJacob Garber
Print an error message and return if an invalid QUP or BLSP is encountered. This prevents a possible null pointer dereference of spi_clk. Change-Id: I374e15ce899c651df9c2d3e0f1ec646e33d4bdb2 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1401086 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-29soc/intel/baytrail: Prevent unintended sign extensionsJacob Garber
Consider the following assignment: u64 = s32 For positive values this is fine, but if the s32 is negative, it will be sign-extended in the conversion to a very large unsigned integer. This manifests itself in two ways in the following code: First, gpu_pipe{a,b}_port_select are defined as int, and can have the values 1 or 2. In the case when they have the value 2, the shift 2 << 30 will be a negative number, making it susceptible to the sign-extension problem above. Change these variables to something more reasonable like a uint8_t, which is unsigned. Second, in any bit shift, any variable with width less than an int will be implicitly promoted to an int before performing the bit shift. For example, the variable gpu_pipea_power_on_delay is a uint16_t, and if its highest bit is set, the shift gpu_pipea_power_on_delay << 16 will become negative, again introducing the above problem. To prevent this, cast all smaller variables to a u32 before the shift, which will prevent the implicit promotions and sign extensions. Change-Id: Ic5db6001504cefb501dee199590a0e961a15771b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1229699, 1229700, 1229701, 1229702 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34487 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29Makefile: Don't create build directory for additional targetsRaul E Rangel
BUG=b:112267918 TEST=Ran make help and verified build directory is no longer created Change-Id: I4bb066b5c3b3d9a7bb19291ef928042b90f10440 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-29src/mainboard/{cavium,sifive}: Use $(obj) instead of buildRaul E Rangel
The build directory might not exist in the src dir. BUG=b:112267918 TEST=make what-jenkins-does Change-Id: I2d4fa6cc455592f92070796cd065cd66646d5ba9 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-29soc/nvidia/tegra124: Assert divisor is non-zeroJacob Garber
The logic for the calculation of plld.m is rather complicated, so do a sanity check that it is non-zero before doing the division. Change-Id: I60f49b8eed47a3de86713304bde7a4d3f3d935dd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1260981 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-29vc/cavium/bdk/libdram: Print unknown voltagesJacob Garber
volt_str is used to print information about the RAM configuration in report_common_dimm(), so let's print out "unknown voltage" if the voltage isn't recognized rather than a garbage value. Change-Id: I8e85917fd682e166172fbf10597bde4a8a11dfc7 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1393958, 1393982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-29haswell: reinitialize EHCI debug hardware after raminitIru Cai
Tested on Lenovo ThinkPad T440p. Change-Id: I54b0c9dbb64819f0f502783b632470d27ed0b2b1 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34358 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29util/amdfwtool: Correct fletcher32 algorithmMarshall Dawson
Change the fletcher32 checksum calculation to match PSP and AGESA implementations. The symptom of the failure has only been noted in Picasso's BIOS Directory Table, when a BIOS binary image of different sizes were passed to amdfwtool. The PSP halts the boot process with the bad BDT checksum, and if allowed to continue, AGESA asserts later due to a failed BDT verification. This version has been verified to produce the same result as found at https://en.wikipedia.org/wiki/Fletcher%27s_checksum. TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom is unchanged. Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-29mb/google/octopus: Add keyboard backlight supportWisley Chen
Dorp device support keyboard backlight, so enable it. BUG=b:138413969 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: If0c7b22b4be2a5d5216404a6944ac887883e9a47 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 04:40:58 +0000