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2021-05-18payload/tianocore: Drop TIANOCORE_TARGET_IA32Lijian Zhao
Since upstream edk2 totally drop 32-bit support for UefiPayload, totaly drop it. Test: Build and run qemu successful boot up into EFI shell with UEFIPAYLOAD option. Change-Id: Iadd9a3c455fad4eede8a0a017415acd2c57fba04 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54189 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18mb/google/dedede/var/cret: Enable/disable LTE function based on FW_CONFIGDtrain Hsu
Enable/disable LTE function based on LTE bit of FW_CONFIG. The LTE function settings are included GPIO settings, USB port settings and power off sequence. BUG=b:187797408 BRANCH=dedede TEST=Build and test the change on cret. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Ib926e99aaf9df433a7cff71180ee55431d69f718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-05-18mb/intel/adlrvp: Disable EC sync for adlrvp_ext_ecMaulik V Vaghela
Since we have TPM disabled on ADLRVP, if we enable EC sync, it keeps rebooting with hash error. Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-05-18amdfwtool:cezanne: use correct bootloader binary for whitelist supportNikolai Vyssotski
PSP whitelist bootloader (PSPBTLDR_WL_FILE) should be copied to type 0x73 entry and not type 0x01 (stage1 bootloader). We will also need to change WHL BL filename (Type0x01->Type0x73) in a separate CL. BUG=b:181135622 Change-Id: I71539a2065546547edc8a2621474cd1388b6434b Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-18mainboard: Drop useless `acpi_tables.c` filesAngel Pons
The `tcrt` and `tpsv` values in GNVS can be used to implement thermal management in ACPI. However, not all mainboards use these values. On mainboards where `tcrt` and `tpsv` are not used in ACPI tables and are the only values set in the `mainboard_fill_gnvs` function, remove them as well as the entire `acpi_tables.c` file. Most files come from autoport, which unconditionally generates this file. Change-Id: If2315ddd9700e2da0a24ffecc20acb5c1a1d688e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-18mb/ocp/deltalake: Rearrange slot table for remapping type 9 Slot IDJohnny Lin
Change-Id: I07bdf7f85f8411e04da8a94da7de1e7b93c9e921 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-05-18mb/google/cherry: Pass reset gpio parameter to BL31Yidi Lin
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=execute `echo b > /proc/sysrq-trigger` to reboot system Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-18soc/mediatek/mt8195: enable ARM64_USE_ARM_TRUSTED_FIRMWAREYidi Lin
Enable ATF configuration to support multi-core. TEST=boot to kernel with multi-core support. BUG=b:177593590 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Id1ef29894fa3a6022574c3874dee62617133b12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/53898 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18amdfwtool: Remove the misleading option charactersZheng Bao
Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2021-05-17Documentation/gerrit: Describe core developer responsibilitiesPatrick Georgi
Change-Id: I8885e9fb401838229ead72b97394f3e2343aabed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-16soc/amd/*/Makefile.inc: Strip the quotesZheng Bao
PSP_SOFTFUSE_BITS used to be like this: 15 0 29 "28 6" It causes internal shell report error: /bin/sh: -c: line 0: unexpected EOF while looking for matching `"' /bin/sh: -c: line 1: syntax error: unexpected end of file /bin/sh: -c: line 0: unexpected EOF while looking for matching `"' /bin/sh: -c: line 1: syntax error: unexpected end of file Change-Id: I716f19d37fb57b9ef3fc7259c6dcca7d21022d32 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-16soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwardsBora Guvendik
DisableDimmMc0Ch0 upds changed to DisableMc0Ch0 in new FSP releases. The definition of the upd also changed. Changed FSP meminit code to work based on new definition of the UPDs. Before: 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs After: 0:Enable, 1:Disable TEST=Boot to OS Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I5af11ae99db3bbe3373a9bd4ce36453b58d62fec Reviewed-on: https://review.coreboot.org/c/coreboot/+/54036 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar
The headers added are generated as per FSP v2162_00. Previous FSP version was v2117_00. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Remove DisableDimmMc*Ch* Upds in FspmUpd.h - Add DisableMc*Ch* Upds in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid compilation failure other change related to UPDs name change will be part of next patch in relation chain. BUG=b:187189546 BRANCH=None TEST=Build and boot ADLRVP using all the patch in relation chain. Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16sb/intel: Drop outdated SMBus I/O BAR commentAngel Pons
The SMBus I/O bar is not relocated because it's reported to the allocator as a fixed resource. Drop these out-of-date comments. Change-Id: I0149764fd231b3a4e56a5a9b7f4ae61f7954cf7a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-16Documentation/distributions: List System76Paul Menzel
Copy the text from the [Web site](https://coreboot.org/users.html). Change-Id: I805f558514eb50580b5bd79bd4f964e66a15158d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-16vboot/secdata_tpm: Create FWMP space in corebootAseda Aboagye
This commit has coreboot create the Chrome OS Firmware Management Parameters (FWMP) space in the TPM. The space will be defined and the contents initialized to the defaults. BUG=b:184677625 BRANCH=None TEST=emerge-keeby coreboot Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I1f566e00f11046ff9a9891c65660af50fbb83675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
2021-05-16vboot/secdata_tpm: Rename set_space()Aseda Aboagye
The name `set_space()` seems to imply that it's writing to a TPM space when actually, the function can create a space and write to it. This commit attempts to make that a bit more clear. Additionally, in order to use the correct sizes when creating the space, this commit also refactors the functions slightly to incorporate the vboot context object such that the correct sizes are used. The various vboot APIs will return the size of the created object that we can then create the space with. BUG=b:184677625 BRANCH=None TEST=`emerge-keeby coreboot` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I80a8342c51d7bfaa0cb2eb3fd37240425d5901be Reviewed-on: https://review.coreboot.org/c/coreboot/+/54308 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16Update vboot submodule to upstream/main (e681c37)Aseda Aboagye
This commit updates the vboot submodule from commit 57c0c5b: cgpt: Move all GPT on SPI-NOR infra behind a flag to e681c37: change node locked version expectations Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Ifd130e3f66f1819f59f00703f0ad0c2278b544bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/54307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-05-16nb/intel/gm45: Guard even more macro parametersAngel Pons
Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Icb9d6e8bdafdac7ad820b1629d04e7bdfbcd4b3f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-16mb/google/mancomb: enable DDI0-DP portIvy Jian
Configure DDI-0 connector type to DP. BUG=b:187856682 TEST=Build and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ic8af14509b0d246c5c2da6e1a48991384471e69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-15Update arm-trusted-firmware submodule to upstream masterYu-Ping Wu
Updating from commit id 7ad39818b: 2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration) to commit id 96404aa27: 2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration) This brings in 861 new commits. Change-Id: I912545022e4320b86ab8a382144c02e315d0c835 Signed-off-by: Yu-Ping Wu <yupingso@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-05-14mb/google/volteer: Configure TCSS OC pinsNick Vaccaro
TCSS OC pins have not been correctly configured for volteer. This patch fills the value from devicetree to correct the OC pins mapping. BUG=b:184660529 BRANCH=None TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and verify CpuUsb3OverCurrentPin UPDs get set correctly. Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro
We need to change OC pin for type C USB3 ports and it depends on the board design. Allowing it to be filled by devicetree will make it easier to change the mapping based on the board design. BUG=b:184660529 TEST="emerge-volteer coreboot" compiles without error. Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-14Documentation/distributions: Order vendor list lexicographicallyPaul Menzel
Change-Id: Id1f27d68124de745ff0eaad669ee86ce0b57ec09 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-05-14Documentation/distributions: Separate all vendors by exactly one blank linePaul Menzel
Change-Id: Ib1718dfa174e2a4e9c2c4b5564e196e8483a8f3c Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-14Documentation/distributions: Separate parenthesis by dashesPaul Menzel
Change-Id: I5d6095c6d8423e3a67f027f23d4c00dcb34a50cb Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-14mb/google/cherry: Add DRAM calibration supportRex-BC Chen
Initialize and calibrate DRAM in romstage. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-05-14mb/google/dedede/var/boten: Modify DPTF parametersStanley Wu
DPTF parameters from thermal team. 1. Modify TSR1 sensor as charge sensor. 2. Modify P-state parameter BUG=b:180641150 BRANCH=dedede TEST=build and verified by thermal team. Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52755 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela
Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/zork: update DRAM table for berknip/dirinboz/gumbozKevin Chiu
Add Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb index was generated by gen_part_id BUG=b:180986354 TEST=none Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-05-14mb/amd/majolica: Disable IO ports 0x60/0x64Raul E Rangel
I suspect there is additional initialization required to enable the 8042 keyboard controller on the EC. By removing the range we no longer encounter long 20 second delays when reading the IO ports. Since depthcharge polls the IO ports it makes it seem like depthcharge locked up. BUG=b:182100027 TEST=Boot majolica with depthcharge to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-05-14mb/clevo/n130wu: Use device alias names in devicetreeFelix Singer
Switch to device alias names in devicetree. Remove unnecessary comments since the names are self-explanatory. Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-05-14tests: Add lib/spd_cache-test test caseJakub Czapiga
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ic9a1420e49e1e80d180117c931e630e54c90cd75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-05-14soc/intel/alderlake: Add known GPIO virtual wire informationDeepti Deshatty
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at least some of their groups; add the known information into the community definitions. This patch is ported form tigerlake. Change-Id: I2f1e2413d06e8afe4233d7111763cb45b78f845b Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14soc/intel/alderlake: Add known CPU Port IDs for GPIO communitiesDeepti Deshatty
Change-Id: Id5fa5b10edeb3445a2d2453d9122376041577598 Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14soc/intel/alderlake: Add IOM PCR PIDDeepti Deshatty
Required for accessing IOM REGBAR space. Change-Id: I883acfa6aa41758e3c8636c94fbee920397fce8b Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/volteer/var/volteer: add specific wifi SAR for voltaSheng-Liang Pan
volta will use different wifi SAR from voxel. Using clamshell mode of fw config to decide to load volta wifi sar. BUG=b:184820057 TEST=build and verify wifi power as expect. Cq-Depend: chrome-internal:3824093 Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I000aefca63346c70556688f232ca54360b3badef Reviewed-on: https://review.coreboot.org/c/coreboot/+/54051 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14src/acpi: Add initial support for HMATJonathan Zhang
Add initial HMAT (Heterogeneous Memory Attribute Table) support based on ACPI spec 6.4 section 5.2.27. Add functions to create HMAT table (revision 2) and create HMAT Memory Proximity Domain Attribute (MPDA) Structure. TESTED=Simulated HMAT table creation on OCP DeltaLake server, dumped the HMAT table and exmained the content. HMAT table and one MPDA structure are added. OCP Delatake server is based on Intel CooperLake Scalable Processor which does not support CXL (Compute Express Link). Therefore solution level testing is not done. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/brya: Use FW_CONFIG LTE_PCIE to turn on/off the PCIE6Eric Lai
PCIE6 only needed when use the PCIE LTE. BUG=b:180166408 BRANCH=none TEST=FM350 can/can't be detected when enable/disable this config. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9dce05fdb6eb956a054d3815ff706b94f0d3fc37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/brya: Add the first FW_CONFIG fields to brya0Tim Wawrzynczak
1) USB sub-board 2) SD sub-board 3) GSC 4) Keyboard backlight 5) Audio sub-board 6) LTE module Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I74ca5ab5366a17e9e1784ec872b9cd77f8663c7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54097 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14acpi: Add acpigen_write_thermal_zoneRaul E Rangel
BUG=b:186166365 TEST=Compiles Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icf88477143049119036c00276f9a01985dc0b4d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14mb/google/mancomb: Update HUB_RST_L setting in GPIOIvy Jian
Configure USB HUB_RESET_L gpio to high. BUG=b:187485847 TEST=Build and boot from USB to OS, check the USB function. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I94e4806c7463030df31f8d819510f9533a622f2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-14mb/google/guybrush,mancomb: select GOOGLE_SMBIOS_MAINBOARD_VERSIONIvy Jian
Select GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. BUG=b:187904819 TEST=1. emerge-guybrush coreboot chromeos-bootimage 2. flash the image to the device and check board rev by using command `dmidecode -t 1 | grep Version` Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I48dc83d85cfc49e2e4155e389814fce08693c4bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-14vendor/mediatek: Add MT8195 dram initialization codeRyan Chuang
This is the DRAM initialization code from the reference implementation released by Mediatek for MT8195. The DRAM calibration code can be taken as a standalone library, used by different boot loaders for initializing DRAM and following a different coding style (coreboot was using Linux Kernel coding style), so we have to put it in vendor code folder. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Change-Id: Iada3ec5ae8a39a8e9253caba550c834d486dddcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/54230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-05-14soc/mediatek/mt8195: Initialize DRAM in romstageRex-BC Chen
Initialize DRAM in romstage and configure to support fast calibration. Change-Id: I89b87be62c8e88ae4a620d56aa7a35e47f97952d Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54229 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14soc/mediatek: Remove duplicate enum declarationRex-BC Chen
Remove dram_cbt_mode in dramc_soc.h. TEST=emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idc4a3887c9cc3f77cbdd7282e2977f6df858817d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Xi Chen <xixi.chen@mediatek.com>
2021-05-14soc/amd/cezanne: Enable GFX HDA FSP UPDKarthikeyan Ramasubramanian
By default, FSP disables the GFX HDA. Enable it to support HDMI Audio functionality. BUG=b:186479763 TEST=Build and boot to OS in guybrush. Ensure that the GFX HDA is enumerated in lspci output. 04:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device 1637 Change-Id: I42cb26c44bbca3d937c5d52736c42468139f7b07 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54100 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14cbfs: Increase mcache size defaultsJulius Werner
The CBFS mcache size default was eyeballed to what should be "hopefully enough" for most users, but some recent Chrome OS devices have already hit the limit. Since most current (and probably all future) x86 chipsets likely have the CAR space to spare, let's just double the size default for all supporting chipsets right now so that we hopefully won't run into these issues again any time soon. The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under the assumption that Chrome OS images have historically always had a lot more files in their RO CBFS than the RW (because l10n assets were only in RO). Unfortunately, this has recently changed with the introduction of updateable assets. While hopefully not that many boards will need these, the whole idea is that you won't know whether you need them yet at the time the RO image is frozen, and mcache layout parameters cannot be changed in an RW update. So better to use the normal 50/50 split on Chrome OS devices going forward so we are prepared for the eventuality of needing RW assets again. The RW percentage should really also be menuconfig-controllable, because this is something the user may want to change on the fly depending on their payload requirements. Move the option to the vboot Kconfigs because it also kinda belongs there anyway and this makes it fit in better in menuconfig. (I haven't made the mcache size menuconfig-controllable because if anyone needs to increase this, they can just override the default in the chipset Kconfig for everyone using that chipset, under the assumption that all boards of that chipset have the same amount of available CAR space and there's no reason not to use up the available space. This seems more in line with how this would work on non-x86 platforms that define this directly in their memlayout.ld.) Also add explicit warnings to both options that they mustn't be changed in an RW update to an older RO image. BUG=b:187561710 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-05-13mb/google/brya: enable DPTF functionality for bryaSumeet R Pawnikar
Enable DPTF functionality for Alder Lake based brya BRANCH=None BUG=b:188028732 TEST=Built and tested on brya board Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-13mb/google/zork/var/shuboz: update USB OC pin mappingKane Chen
modify USB OC pin setting for Shuboz/Jelboz/Jelboz360 Shuboz/Jelboz: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_PIN_1" # USB A1 usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 Jelboz360: usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0 usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0 usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1 BUG=b:182879559 BRANCH=zork TEST=emerge-zork coreboot, validate the OC mapping. Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-11 08:29:54 +0000