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2014-07-04intel/lynxpoint: Make inclusion of Intel ME optionalPaul Menzel
Current build configuration always wants to include an Intel Management Engine (ME) firmware (`me.bin`) on Intel Lynx Point systems. However, we can have a working coreboot without it, as long as the factory delivered ME firmware is kept untouched in the flash ROM. So let the user decide if a ME firmware will be included in the build by introducing the Kconfig option `HAVE_ME_BIN`. The same was done in commit 99fd30e4 (sandybridge: Make inclusion of me.bin optional) [1] for Intel Sandy Bridge (BD82x6x). [1] http://review.coreboot.org/3522 Change-Id: I7c6048fd0f56288769ad90acbfb67b908ac8d824 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6047 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-04intel/lynxpoint: Allow building without IFD (descripter.bin)Paul Menzel
On newer Intel systems, like Intel Lynx Point, the flash ROM is shared between the host processor (BIOS), its Management Engine (ME) and an integrated Ethernet controller (GbE). The layout of the flash ROM (and other information) is kept in the so called Intel Firmware Descriptor (IFD). If we only want to build coreboot to update the BIOS section, all we need is the flash layout. So add the option to specify the flash layout in the mainboard’s Kconfig, and thus, to build without the real IFD. However, with such a build, one has to make sure that the IFD section on the flash ROM will not be written over (nor any other section that has not been included by coreboot). A patch to write selected sections of a flash ROM with IFD has been sent to the flashrom mailing list [2]. The same was done in commit a15cd66b [1] (sandybridge: Make build possible without descriptor.bin) for Intel Sandy Bridge (BD82x6x). [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html [PATCH] Add option to read ROM layout from IFD [2] http://review.coreboot.org/3524 Change-Id: I26a604446cdf37a6bbcee2b14a107b7ccf417d5c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-03AGESA boards: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: Ib76ec433710b3a7c26360329a9403585d6f4fe4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03ACPI: Recover type of wakeup in acpi_is_wakeup()Kyösti Mälkki
Update acpi_slp_type early in ramstage. Change-Id: I30ec2680d28b880171217e896f48606f8691b099 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6142 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA: Call get_bus_conf() just onceKyösti Mälkki
Instead of calling get_bus_conf() three times from write_tables() and executing it once, just make one call before entering write_tables(). Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6133 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA: Add agesawrapper_post_device()Kyösti Mälkki
NOTE: The procedure is moved across a collected timestamp TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted for in an earlier entry in cbmem -t output. Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6132 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA boards: Use acpi_s3_resume_allowed()Kyösti Mälkki
This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the build of romstage also for boards without HAVE_ACPI_RESUME. These symbols got exposed as the use of preprocessor directives was reduced. We expect the linker to do a fair job and optimize away function bodies that are on unreachable execution paths. Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6067 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03AGESA: Clean separation of SPI flashKyösti Mälkki
To be precise, wakeup from S3 does not involve SPI writing, while preparing for it on cold power-ons currently does. For S3DataTypeMtrr storage is changed such that the first 4 bytes is the length of data stored like with the other two S3DataType. Change-Id: Id920650474530d4191075da4ef70daa66c904c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6085 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-07-03AGESA boards: Add prepare_for_resume()Kyösti Mälkki
Use one common implementation for all AGESA platforms. Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6084 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-03AGESA S3: Refactor S3 backup store locations in SPIKyösti Mälkki
Prepare code to locate S3 backup from CBFS as a file. Follow-up will replace remaining use of CONFIG_S3_DATA_POS with cbfs_get_file_content(). Change-Id: I693c41c90e61d1a7c7b10e43c9f264d099c9a400 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6083 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-07-02AMD/agesa: Add functions for AMD PCI IRQ routingDave Frodin
Port the changes that were made in amd/cimx to amd/agesa as were done in: commit c93a75a5ab067f86104028b74d92fc54cb939cd5 Author: Mike Loptien <mike.loptien@se-eng.com> Date: Fri Jun 6 15:16:29 2014 -0600 AMD/CIMx: Add functions for AMD PCI IRQ routing This change also moves the PCI INT functions to southbridge/amd so that they can be used by CIMX and AGESA. The amd/persimmon board is updated for this change. Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637 Reviewed-on: http://review.coreboot.org/6065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-01stdlib: Drop duplicates of min() and max()Kyösti Mälkki
Change-Id: Ib2f6fad735e085d237a0d46e0586e123eef6e0e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6161 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-01ROMCC: Fix collision with token name maxKyösti Mälkki
Even with !defined(__ROMCC__) in the file, romcc chokes on these parameter names after we declare common max() macro in stdlib.h. Change-Id: Id4f2aa61d9c5b19f428452cd475b1b2ed9a70f52 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6165 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-30northbridge/intel/nehalem/raminit.c: Extraneous parentheseEdward O'Callaghan
Equality comparison with extraneous parenthese, spotted by Clang. Change-Id: I8d532392a0365753583ed441958e06d5da784587 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6124 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-30northbridge/amd/{gx2,lx}: Qualify pointer with `volatile`Edward O'Callaghan
There is no guarantee reading a dereferenced null pointer will not be optimised away. Qualify the integer storage type with volatile. Clang enforces this explicitness. Change-Id: I31524141d70632cade0490c820936a3a8b570346 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6148 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-30x86 MTRR: Drop unused return valueKyösti Mälkki
It was never well-defined what value this function should return. Change-Id: If84aff86e0b556591d7ad557842910a2dfcd3b46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6166 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-30Use MTRR definesKyösti Mälkki
Change-Id: I60ae6dcb8c3b280fe74f27f4d61de70cc1ba190b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6123 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-30Makefile.inc: Detect if a working clang binary exists before setEdward O'Callaghan
Let us not assume the 'clang' binary exists and is working just because the user selected it in .config Change-Id: Iad3cbf4a7cda0e1c4d435fbe426b7247233973ea Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6141 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-29Makefile: HOSTCC set too late in clang buildsEdward O'Callaghan
Currently we set HOSTCC=clang a little late meaning some minor bits (utils/kconfig) are built with GCC. Move the assignment up the Makefile. Change-Id: Ic72ad808eba0c0bf508bde34fb9bf0390c0b1d4d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6140 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-29northbridge/amd/gx2/raminit.c Halt func needs noreturn attribEdward O'Callaghan
Missing "__attribute__((noreturn))" on halt function. This sync's the implementation to be the same as that of amd/lx thereby avoiding compiler warnings. Change-Id: Iead16125805eb36ff875fba767cf8d4e5aa86715 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29drivers/pc80/mc146818rtc_early.c: Silence unused func complaintsEdward O'Callaghan
Clang complains these functions are unused since they find their way into the bootblock of ROMCC boards by #including the .c file. These static inlines should probably be moved into a header in reality. Change-Id: I9d82a6befb0ac99afab6265f9d3649e419f2887d Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6122 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-29southbridge/intel/ibexpeak/me.c: Silence warns about unused funcEdward O'Callaghan
Move some __SMM__ functions under the #if preprocessor condition to avoid warnings about unused functions. Change-Id: I7f6fbc6a577032bc4e4635d91e8e94aecb517bd3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6127 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29northbridge/amd: Remove some extraneous parentheses from if-statementsEdward O'Callaghan
Spotted by Clang. Change-Id: I38832da7b93d4ee18b8de3e80dc39513a8910221 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6149 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29cpu/x86/pae/pgtbl.c: Unsigned comparison < 0 always falseEdward O'Callaghan
Comparison of unsigned expression < 0 is always false. Change-Id: Idf4e7846b50f4376a5d33515681efbd773d1caca Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6146 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29AMD boards: Fix comment style and typosKyösti Mälkki
Change-Id: Id630cc46b79a39e1786d42adbc21f3b9c3a051aa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6118 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-29build: remove -ccopts mechanismPatrick Georgi
We now use the slightly more familiar CFLAGS_* and CPPFLAGS_* for the same purpose. Change-Id: Ifd2bd13f67f71fa0a15611a6d11a6a4c7994271b Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5875 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-29include/pc80/mc146818rtc.h: Inconsequential, comment ifdef mazeEdward O'Callaghan
Change-Id: Ie1ec8dbcdbbe0f2b05fdb10b1dca43cfee2a58cb Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6120 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29arch/x86/include/bootblock_common.h: Sanitize header inclusionEdward O'Callaghan
Sanitize the inclusion of mc146818rtc.h in bootblock_common.h Change-Id: I37d9ffd1375aedbf1f3eaa4ddce27e16166ce0b9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6119 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-29utils/cbfstool: No need to pass -g flag twiceEdward O'Callaghan
Spotted by building with Clang. Change-Id: I7ab97278d8bd586a71e453c8cc9d26dd6938c8d2 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-29cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII artEdward O'Callaghan
Embedding comments inside comments is illegal in the C specification, Clang enforces this. Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6154 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-28Don't add .eh_frame sections to SMM imagePatrick Georgi
We don't need exception handlers and they waste space. Change-Id: I98a34d1c9638e8c4168edbfb4b1cddde8a64623f Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6105 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-28armv7: We don't use CPPFLAGS anymorePatrick Georgi
CPPFLAGS is only used as qualified variant (like CPPFLAGS_armv7) now. Change-Id: If8b570ace4ac92d1fdb38ca3f7fef6c79d513a95 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5874 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-27build: Pass correct disassembly flags in Clang buildEdward O'Callaghan
On SVR4-derived platforms, the character `/' is treated as a comment character, which means that it cannot be used in expressions. The `--divide' option turns `/' into a normal character. This seems to be needed with our local build of binutils since we don't yet use the internal assembler/disassembler of the Clang tooling. Change-Id: I344fc8670fd5d994f3b63308a513dd367aefc7f9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5813 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-27lib/Makefile.inc: Stop gcc.c getting into SMM clang buildsEdward O'Callaghan
The libgcc runtime workarounds found in gcc.c are not needed for compiler-rt used by the Clang toolchain. Stop gcc.c from sneaking into Clang builds while processing boards that use SMM code. Change-Id: I51e8d517784721d28b4d951bd0bebc8b52682a8e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6121 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-27src/console/post.c: Sanitize headers from preprocessor abuseEdward O'Callaghan
Continuing on from the rational given in: a173a62 Remove guarding #includes by CONFIG_FOO combinations Change-Id: I524713b21684f6fa99355614a1ab38aee9975790 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6091 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-27include/device/device.h: Header is ROMCC tentativeEdward O'Callaghan
This header is incompatible with ROMCC and its inclusion leads to 'odd' build failures. Change-Id: If31d774385796dcafe2fd48151e424b4c872aec3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6103 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-26amd/persimmon jetway/nf81-t56n-lf: Fix whitespace and alignmentKyösti Mälkki
Change-Id: I76f017b0919e301eeb84e73eff21170bbc921ae2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6113 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26AMD boards: Fix typosKyösti Mälkki
Change-Id: I5df80e6445f390060372be8760c9b5e960e4a6e5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6117 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26AMD boards: Fix typosKyösti Mälkki
Change-Id: If1dc4fd2204a2e4b6f84c75f385b8ff958d2251d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6112 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26AMD boards: Fix typosKyösti Mälkki
Change-Id: I22180c3c2987396717864f04c59560029d088d53 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6111 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26AMD boards: Fix typosKyösti Mälkki
Change-Id: I92f3877b58d9acaa9578337e66107e9cd9f46043 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6110 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26AMD boards: Fix typosKyösti Mälkki
Change-Id: I090e98fbf28595d3917ef84e19bd6d6742f11b94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6108 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26PIRQ tables: Fix typosKyösti Mälkki
Change-Id: I4d8abe3841378e06515e1b3a8f22d78425d08449 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6109 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26bayleybay_fsp: Switch from EHCI controller to XHCIMartin Roth
- Disable the EHCI controller and enable the XHCI controller. SeaBIOS has been tested on the board and boots an OS from a flashdrive at SuperSpeed. This also enables the top USB port on the 2-port stack, which goes through a High Speed Inter-Chip port. The HSIC port is only enabled through the XHCI device. Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6106 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2014-06-25gm45 boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki
Change-Id: Id19d31a2d114bb796b31ad61802d40c8608e4020 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6038 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25nehalem boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki
Change-Id: Ie4df2199e746de58c926f35bc9000752d399aa37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6037 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25i945 boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki
Change-Id: I1bbcba086f841a90544b827ae807a3c351d19d21 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25emulation/qemu: Switch x86 to DYNAMIC_CBMEMKyösti Mälkki
Change-Id: I00055064003c814b86fd1400d50bfd02fdfdf475 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6035 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25sandy/ivy boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki
Like with other more recent boards already using DYNAMIC_CBMEM, the pointer to TOC is no longer stored in GNVS for ACPI. Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6034 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25pc80/mc146818rtc.h: Has X86 specific inlines without guardsEdward O'Callaghan
PC80 header components are winding up in ARM builds with static inline X86 specific code. Change-Id: Ib23e70a34c478dc099b84b59a5234539cc2482e3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6101 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-26 17:39:54 +0000