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2018-10-04sb/amd/pi/hudson: Remove #if 1Jonathan Neuschäfer
Change-Id: I4cf69dc3df2afaa8f33864374ea93548ab7ad810 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04Documentation: Spell "blob" in lowercaseJonathan Neuschäfer
It's not an acronym (outside of database software). Change-Id: I529561e4fc9889be7f9d6bd6d5f9a876e2007671 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04util/abuild/abuild.1: Fix references to CBROOT parameterJonathan Neuschäfer
One occurence of this parameter was changed from LBROOT to CBROOT in f8ee1806ac ("Rename almost all occurences of LinuxBIOS to coreboot."). Change the others, too. Change-Id: Ic0da24c32cd6d2f0577de037b5463c800f455786 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04MAINTAINERS: Update RISC-V entry with SiFive and utilsJonathan Neuschäfer
Change-Id: Idd9e51fe2cb7a8497381f5b7440666cd709166b8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04arch/riscv: Adjust compiler flags for scan-buildJonathan Neuschäfer
Clang doesn't understand -march=riscv64imac and -mcmodel=medany, so don't use them when running the clang static analyzer. On the other hand, __riscv and __riscv_xlen need to be defined in order to select some macros in src/arch/riscv/include/arch/encoding.h. __riscv_flen selects the floating-point paths in src/arch/riscv/misaligned.c. -mabi is moved with -march for consistency. A complete list of preprocessor definitions on RISC-V can be found at https://github.com/riscv/riscv-toolchain-conventions#cc-preprocessor-definitions With this commit, scan-build produces a useful result on RISC-V. Change-Id: Ia2eb8c3c2f7eb5ddd47db24b8e5fcd6eaf6c5589 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-04cpu/intel/car: Fix typoElyes HAOUAS
Change-Id: If71ab647f012a735c6aa6939463414407757ab9a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-10-04mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for FleexIvy Jian
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 2 for DVT. BUG=b:116721822 TEST=Verified it in Fleex EVT board which rework ram id. Change-Id: I0f191c950aa6a70069bffa1f1802386ab263a310 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-04mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQDuncan Laurie
Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04ec/google/chromeec: Define a sync IRQ if neededDuncan Laurie
Some boards are adding a second pin used for synchronization between the EC and AP. This is a direct connection between the EC and the SOC that is intended to provide a lower latency interrupt signal for sensors on the EC. Currently the runtime EC interrupts assert an SCI before eventually resulting in a Notify() on the MKBP device that the sensor driver users. These extra layers add processing time and require additional EC communication to determine the event source. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: I49a11363ce82882e572bcb8923fd114ab6593fea Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04mc_apl1: Set up SPI OPCODE menu before lockingWerner Zeh
In order to enable the OS SPI driver to use the software interface of this controller the OPCODE menu has to be set up properly before locking the controller. This is done on baseboard level so that all variants will get this done as well. Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-10-03mb/google/kahlee: Update careena Audio/TP i2c timingKevin Chiu
After adjustment on Careena Audio: 402.805 kHz -> 396.8 kHz TP: 406.1 kHz -> 399.5 kHz BUG=b:110984023 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ia3eb91ca3772d5f122498e3989ec03838fce06a5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-03google/kahlee: Enable IOMMU deviceMarc Jones
Enable the IOMMU device on all kahlee based mainboards. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I18b9ba1a970c6973226e736d72f82fd53010f31c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/28754 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-03soc/amd/stoneyridge: Add IOMMU supportMarc Jones
Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/28753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-03Documentation/mb/lenovo/t4xx_series: Change "Steps to access the flash IC" ↵Jonathan Neuschäfer
to sub-heading This heading should not be a top-level heading, because it's not at the top of the file. Also remove the trailing colon, because it's unnecessary in a heading. Change-Id: I0685bb8734ad899c29618d24c0497e4fb8c0d01c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-10-03soc/intel/commom/block/i2c: Make I2C controller out of resetSubrata Banik
This patch ensures I2C controllers are out of reset without any assumptions. BUG=b:116191230 BRANCH=none TEST=Dump MMIO offset 0x204 to check if I2C host controller is NOT at reset (by reading Bit 0-1 as 3) Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-02src/soc/intel/broadwell/me.c: Correct HMRFPO misspellingAngel Pons
`HMRFPO` was spelled as `HMRPFO` twice. Change-Id: Ibd04004ac5edcdeee49a6a69fcdd5c73603e92e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-02soc/intel/skylake: Fix spelling mistakeSubrata Banik
Make correct spelling for THERMAL_IRQ macro in irq.h file. Change-Id: I83593822e2abbb07e60fc336b774199fea3b368f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-10-02soc/intel/skylake: Replace white space with tabSubrata Banik
This patch unified line indentation. Change-Id: Ife3396e36a0684490d9ed9b31b4c0a543a3e3d24 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-10-01drivers/intel/wifi: Add DID for Intel WIFI module 8260, 8275Subrata Banik
Change-Id: I38d83370e96cff6822a96da5fa3d9af797ba1dc1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-10-01libpayload/drivers/usb: Fix leaksPatrick Rudolph
Don't leak buffers on device detach. Tested on qemu using: qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \ -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \ -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd Change-Id: Ib2d80dd4590aa0dacdf2da3b614c6505c931d0be Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-01libpayload/drivers/usb: Fix broken retry counterPatrick Rudolph
Exit on first sucessful CONTROL transfer instead of doing GET_DESCRIPTOR_TRIES iterations. Tested on qemu using: qemu-system-x86_64 -bios build/coreboot.rom -M pc -m 2048 -usb \ -device usb-ehci,id=ehci -device usb-mouse -device usb-audio,bus=usb-bus.0 \ -device usb-bt-dongle,bus=usb-bus.0 -device usb-kbd Change-Id: I7c881c08d94636a43223338e46c876b5f3e27d47 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/23688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-01mb/google/octopus: Operate touchpad I2C CLK in specChris Zhou
Need to tune I2C bus 6 clock frequency under the 400K Hz Bug=b:115600671 TEST=flash coreboot to the DUT and measure I2C bus 6 clock frequency whether arrive to 398.07K Hz Change-Id: I5cc1f67f0db0553cb8424f81408ed4686cddb2fb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-01src/Kconfig: Drop a superfluous wordJonathan Neuschäfer
Change-Id: I2d658e57d52f79c77be08599b9e525a46e30f732 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01google/kahlee: Run FCH PTS and WAK methodsMarshall Dawson
The FCH ASL is now capable of controlling the D-states of most AOAC devices, as well as properly reinitializing the xHCI firmware on a resume. Call the FPTS and FWAK methods. BUG=b:77602074 TEST=On Grunt, go to S3 and wake with a USB keyboard Change-Id: I4df8523569dc3dfbd87f79e780c18d39f0d9a37f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28773 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add USB ASL for D0/D3coldMarshall Dawson
Add methods, and call them, for transitioning EHCI and xHCI to D0 or D3cold. Add device objects necessary for waking the system via USB. In order for USB to wake the system, it must be in the D3cold state. Then on resume, its firmware must be reloaded. This code relies heavily on AMD's FchCarrizo.asl (delivered in NDA PI package), and has been modified to fit the coreboot ASL names. In addition, AMD's methodology is to generate a SW SMI for saving/restoring certain settings. This has been ported into U3D0 and U3D3, as the necessary registers are now publicly documented. BUG=b:77602074 Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28772 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ASL helper for AOAC PwrGood ControlMarshall Dawson
Add a method to assist with setting the PwrGood Control register, which will be useful for various devices. BUG=b:77602074 Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01amd/stoneyridge: Add FCH WAK and PTS methodsMarshall Dawson
Add methods that can be used for preparing all controller hub devices for sleep, and that will turn the devices back on. BUG=b:77602074 Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28770 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ASL for D-states on AOAC devicesMarshall Dawson
Duplicate ASL from AMD's FchCarrizo.asl (available in NDA PI package) that can put AOAC devices into D0 or D3cold. The argument numbers coincide with the AOAC register offsets for the various devices. SATA, USB, and SD require additional device configuration. Add a placeholder and mark as todo. BUG=b:77602074 Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28769 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASLMarshall Dawson
Define various AMD_SB_ACPI_MMIO_ADDR registers at 0xfed80000. Define various PCI config space registers. These are duplicated from AMD's FchCarrizo.asl file. BUG=b:77602074 Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28768 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Load AOAC and USB gnvs valuesMarshall Dawson
Indicate the devices that are enabled. This is somewhat rudimentary, but could be improved in a later patch (e.g. get settings from devicetree). Calculate values that may be used for reinitializing the xHCI firmware. Add the EHCI BAR's current base address to gnvs. BUG=b:77602074 Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28767 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Add USB settings to gnvsMarshall Dawson
A later patch will rely on two USB settings from the BIOS. Add these to the global_gnvs_t structure. The first is a data that will be used to locate the xHCI firmware for reloading after a resume. Although the existing calculations will be somewhat simple, keeping this on the coreboot side will help in the event multiple FWs are eventually in the build. The second item is a usable EHCI base address that may be programmed during S3 suspend and resume. At the time the PTS and WAK code runs, the BAR will be clear. BUG=b:77602074 Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-01amd/stoneyridge: Create gnvs entries for AOAC devicesMarshall Dawson
A later patch will leverage AMD's ASL support for handling AOAC devices. This will gather coreboot's device enables from a bitwise field, where each bit corresponds to the register offset used to control each devices. Create an identical structure, and add it to the nvs ASL and global_nvs_t structure. BUG=b:77602074 Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-01drivers/spi/winbond: Fix read protection bitsPatrick Rudolph
Don't care about SRPx and print correct protected range. Change-Id: I051f1459c585a7ed6a4878dc217d11df5ef00d74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-01soc/intel/fsp_broadwell_de: Fix IA32_MC0_* namesElyes HAOUAS
Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and IA32_MC0_CTL is at 0x400. So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at 0x400 by IA32_MC0_CTL. Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-01siemens/mc_apl1: Activate clock spreading for PTN3460Mario Scheithauer
In order to minimize Electromagnetic Interference (EMI) on the LVDS interface driven by PTN3460, clock spreading must be activated for mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal frequency. Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28761 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-30Documentation: Add basic flashing tutorial for LenovoPatrick Rudolph
* Add basic flashing tutorial ** Describe internal and external flashing ** Describe flash supply diode protection ** Gives general advices on flashing ** Describe how to use flashrom --ifd * Describe basic flashing on Lenovo T4xx devices ** Describe how to disassemble and access the flash IC on T4xx ** Describe flash layout on Sandy Bridge and Ivy Bridge series. Change-Id: Ia833e27f4e7d89ee32be9bed21a0c021839facec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-30Documentation: Describe recommonmark's auto_toc_treePatrick Rudolph
Explain recommonmark's auto_toc_tree and give an example to make writing documentation easier. Show an example what happens if the document isn't included in any toctree. Change-Id: I4938d8d292ea890caec6d396b4fa04da65e398f4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-30Documentation: Disable auto_doc_refTom Hiller
According to recommonmark's documentation the enable_auto_doc_ref is deprecated. This is not true, as it's broken with Sphinx 1.6+ commit 12d639873953847de31ec99742b42e50e89ed58c. recommonmark bug report is here: https://github.com/rtfd/recommonmark/issues/73 Instead of using this feature, which doesn't support top level directories in the relative document path anyway, use the TOC tree or inline RST code. Disable auto_doc_ref and document how to reference documents. Change-Id: I9319985b504c4215c33ebbeb9c38317b9efcb283 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-30Documentation: add description for util/pmh7toolEvgeny Zinoviev
Change-Id: Iab5daf101a9ff27aa49b7849bf6bf39362b8db09 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/28368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-30mainboard/opencellular/elgon: Add mainboard supportPhilipp Deppenwiese
Tested on Elgon EVT board and boots into GNU/Linux. TODO: * Add hard reset function for VBOOT. * Add EC code * Add SPI flash write protection Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-30soc/cavium/cn81xx/spi: Add function to return SPI clockPatrick Rudolph
Change-Id: I07c95b9ea14d47da0497470487fa3f162f8012c8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-28amd/stoneyridge: Make gnvs ASL whitespace consistentMarshall Dawson
The globalnvs.asl file had become mixed with tabs and spaces to align columns. Use all tabs to align the comments. BUG=b:BUG=b:77602074 Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-28mb/lenovo/t400: Add 154WX5-TLB2 to display backlight PWM freq listArthur Heymans
Vendor VBT on ThinkPad R500 intends to set a 220MHz backlight PWM frequency which seems to work well. Change-Id: Ic1a12c7e3173468561ed5615319962d0abc6d61b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-28mb/lenovo/t400: Link the gpio.c settingsArthur Heymans
Linking this file instead of including a header makes it possible to easily change gpio settings for a variant. Change-Id: Ifd496510d4868f5901a9dbbf7f1523ccffaf15ab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28628 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28mb/lenovo/t400: Trim down the gpio.h fileArthur Heymans
Some settings like direction are only used if the mode is GPIO. Change-Id: I4efc54dfef3721b528b90d49f490014d9132cdf8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28627 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28vendorcode/amd/pi/00670F00/Lib: Remove folderRichard Spiegel
Now that the last dependency was resolved, remove AmdLib folder. BUG=b:112525011 TEST=Build and boot grunt. Change-Id: Ibd9a20bc358742520138b9b01f76d7fd2fac92ab Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28742 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28soc/amd/stoneyridge/BiosCallOuts: Remove #include <AmdLib.h>Richard Spiegel
In preparation to remove AmdLib, remove reference to AmdLib.h in soc/amd/stoneyridge/BiosCallOuts. BUG=b:112525011 TEST=Buildgrunt. Change-Id: If80eb64fb736ff26ab226a16b583c8b1c29831f4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28741 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Charles Marslett <charles.marslett@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28src/mb/asrock/g41c-gs: Add variant g41m-s3Angel Pons
This board is pretty much like the G41M-GS, but with DDR3 memory instead. The PCB layout is almost identical. What works: - S3/S4 resume - RAM init - Booting to Debian - Display lights up w/ libgfxinit - Both PS/2 work - Ethernet - Graphics card on PEG - USB - SATA ports - NVRAM debug_level - Internal flashing - PCI slots (tested with CT4810 audio card) - fancontrol (Only CPU fan can be regulated) - Audio (Rear ports only) What does not work: - Hell knows what might be wrong What is not tested: - PCIe x1 - IDE - Floppy - Parallel port Change-Id: I66b216af740680c390ea82e4fe07737c20227cc6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-28soc/intel/cannonlake: Fix ACPI FADT table generationDuncan Laurie
The function to fill out the FADT table exits early if the devicetree config option to disable the legacy timer is set. This means it never gets to the later check for s0ix config option and so the flag to indicate that it supports low-power idle in S0 is not set. Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28755 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28mb/intel/coffeelake_rvp: Enable GbE supportLijian Zhao
Enable Gigabit Ethernet network controller on whiskey lake rvp platform, add NVM bin file as well. BUG=N/A TEST=Build and boot up into chromeos on whiskey lake rvp platform, and check eth0 can get IP address assigned, Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27848 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 19:54:28 +0000