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2016-05-10soc/qualcomm/ipq40xx: Update memory map to align to ipq40xxVaradarajan Narayanan
Update the memory to map to align with the internal memory region map of IPQ40XX BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: e33712a729ef9831508c2e9aae81d0b32495b681 Original-Change-Id: Iba1c5281a2fbda4ab96126676b901ba71f6b28e0 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333295 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update DRAM address ranges BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 9150c125cb82f8dccb1347d898106703d85a5192 Original-Change-Id: Ic48d3e3f46a7c13a009a5cbed20984bd253eb85b Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333296 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iea40484751a1c0439ed511319ef09a0254eba757 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14654 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Invoke createxbl.py using `python`David Hendricks
This avoids issues the Makefile can have when running the createxbl.py script directly. BUG=none BRANCH=none TEST="emerge-gale coreboot" works Change-Id: I78b6b0cd4d64c022cbe02fc40202da382e1f1ec7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5351abafcc4bfe5de74d3242a907e86d3aa94bbd Original-Change-Id: I87b8c9991cfc4d5a14903ec565e6a05281b00c82 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338652 Reviewed-on: https://review.coreboot.org/14653 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Add config option for SBL utils pathVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=Compiles... BRANCH=none Original-Commit-Id: bf907395f4abe859489276e793d9662c8594ff9b Original-Change-Id: I132bfe667f9b4fad32ed7b14091c4523020183d0 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333309 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update build script util path BUG=chrome-os-partner:49249 TEST=Able to boot and reach depthcharge BRANCH=none Original-Commit-Id: ffd5fc7a92dae6c5ae11ad7fc85d55dac47b3b3b Original-Change-Id: I7a8011fc9ba2ac25d795d12b61eb9205e414e0c5 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340182 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: If41b5faab7952b1017877a91e4cf281ee4ce99d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14652 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10google/gale: Initial commit for Gale board supportVaradarajan Narayanan
Copy 'storm' files as a template BUG=chrome-os-partner:49249 TEST=None. Initial code. Not sure if it will even compile BRANCH=none Original-Commit-Id: 4bfabf22cb33ac2aacff0ebeed54655664505148 Original-Change-Id: I94e361911b89c5159b99f3d00efbcda94f763e71 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333177 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: google/gale: Remove unwanted config option 2016.02 doesn't seem to like CONSOLE_CBMEM_DUMP_TO_UART BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: 44b91a8f83515936156206f9f273e0e5c62c3f17 Original-Change-Id: I9294ff602a05e4c9573fee3b9b51f9cc5305e192 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333302 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> google/gale: Update ipq806x/storm references Since the files were taken from ipq806x/storm as template. Update those references to reflect ipq40xx/gale. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: fa5962b757dbb6cc9e1e6d1e33e1e09ec6cb4cd2 Original-Change-Id: Ia330367a0547ac4306ef2514dc1305e2d65f80e4 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333292 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> google/gale: Update fill_lb_gpios for new scheme This updates fill_lb_gpios to follow the new scheme introduced in CL:337176. BUG=none BRANCH=none TEST=chromeos.c compiles successfully for gale Original-Commit-Id: 635d7fd71d91552bd7470faeb5637ba1a727f940 Original-Change-Id: I6f98325918b350645b9c19b71125bc12a54953ab Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338651 google/gale: Add '.fmd' file BUG=chrome-os-partner:49249 TEST=None. Initial code. Not sure if it will even compile BRANCH=none Original-Commit-Id: 474de31f7ed0adbe54251ca363e685019091b4e7 Original-Change-Id: I4019b110af676090e8751b315dadc5b601a56178 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333291 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iad8e010371f3b9b92ab26eee4ba35c4f16d3732c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14642 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Update the list of MBNs needed for this SoCVaradarajan Narayanan
BUG=chrome-os-partner:49249 chrome-os-partner:50928 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: a48131897217a6e48927d5aafc855a86551c35ca Original-Change-Id: Ia7bab63e5abfb99ab0c03e0e2879149597b7355f Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333294 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Add Kconfig option for SBL binary path BUG=chrome-os-partner:49249 TEST=Compiles... BRANCH=none Original-Commit-Id: 8f0899e3c69737ec7ba579979dae342673bf3962 Original-Change-Id: If199f755106dc58b55ee0499e05304f0ea117bee Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333307 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> soc/qualcomm/ipq40xx: Add rules to combine vendor binary and CB binaries BUG=chrome-os-partner:49249 TEST=Compiles... BRANCH=none Original-Commit-Id: d4b49d37c5b6f86a3bc360051904175111e1db2b Original-Change-Id: I85fde202213b47d5e7c9af3a8d920da20cf456fa Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333308 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: I91b873894975f0a88babc2e2ecdbe5676ee17c0b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14649 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10soc/qualcomm/ipq40xx: Initial commit for IPQ40xx SoC supportVaradarajan Narayanan
Copy 'ipq806x' files as a template BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: dc6a5937953fe61cd4b5a99ca49f9371c4b712d4 Original-Change-Id: If171fcdd3b0561cb6b7dab5f8434de7ef711ea41 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333178 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update ipq806x/storm references Since the files were taken from ipq806x/storm as template. Update those references to reflect ipq40xx/gale. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: c6c76d184cc92c09e6826fbdc7d7fac59b2cb69b Original-Change-Id: Ieae1bce25291243b4a6034d37a6949978f318997 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333293 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ie5794c48131ae562861074b406106734541880d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-103rdparty/blobs: add more Qualcomm stubsPatrick Georgi
Change-Id: Ie57b0b7844f28671b8d6a8efe9231a47bfb8f805 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14745 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-10siemens/mc_tcu3: Don't try to init unsupported panel typeWerner Zeh
The LCD panel type is read using 4 GPIOs. Of these 16 possible combinations only 5 are supported right now. If the GPIO setting encodes an unsupported panel type, there will be no matching hwinfo.hex in cbfs. Therefore it makes no sense to try to initialize the DisplayPort-2-LVDS converter. Leave the function instead in this case. Change-Id: If8c67a3f5be762758d516c4939dd1de4ff1c8ba5 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/14743 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-05-10AGESA boards: Relocate platform memory configKyösti Mälkki
File buildOpts.c is a can of worms, pull platform memory configuration in to OemCustomize.c. This array should be assigned at runtime instead of linking a modified defaults table. Change-Id: I73d9d3fbc165e6c10472e105576d7c40820eaa6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14528 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-10AGESA boards: Rename files containing OEM configurationKyösti Mälkki
There are other things besides PCIe port configuration that require board specific hooks. Change-Id: I0923651487b9ed5f6f7569ce08e02d993fa5f976 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09mainboard/asus/[kgpe-di6|kcma-d8]: Fix board ROM informationTimothy Pearson
The board information file incorrectly listed an LPC ROM. Fix the information file to show the correct SPI ROM. This patch changes a human-readable file only, and does not alter functionality. Change-Id: Ib5c1789fa636354f2b6c92faf44b45b32d1ec544 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14742 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structureTimothy Pearson
The existing DIMM size calculation for DDR3 was incorrect. Use the recommended calculation from the DDR3 SPD specification. Change-Id: Id6a39e2b38b5d9f483341ebef8f2960ae52bda6c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14739 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09smbios: Add SuperTalent SPD IDTimothy Pearson
Change-Id: I5373be7ab55ac3c4f2e4dd753c6ad8e91712ff7e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14738 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15hTimothy Pearson
While some stubs existed before this patch to handle non-ECC memory initialization, there were a number of ECC detect unaware sections of code. Add ECC support detection to those sections. Change-Id: I56dad8a0f6833b2f42796212afb9777e9cc73d6d Tested-On: ASUS KGPE-D16 Tested-With: 1x Opteron 6262 Tested-With: 1x SuperTalent 4G non-ECC DIMM in slot A2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14737 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09soc/intel/apollolake: Select no stage caching for resumeFurquan Shaikh
Select NO_STAGE_CACHE so that ramstage is not cached for resume. Change-Id: I9ca71686e0f617bb24713ec9ba07b5255c218f66 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09drivers/uart: Use uart_platform_refclk for all UART modelsLee Leahy
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09drivers/uart: Enable override for input clock dividerLee Leahy
Allow the platform to override the input clock divider by adding the uart_input_clock_divider routine. This routine combines the baud-rate oversample divider with any other input clock divider. The default routine returns 16 which is the standard baud-rate oversampling value. A platform may override this default "weak" routine by providing a new routine and selecting UART_OVERRIDE_INPUT_CLOCK_DIVIDER. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Ieb6453b045d84702b8f730988d0fed9f253f63e2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14611 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09soc/apollolake/pmutil: Get PMC base address dynamicallyAlexandru Gagniuc
Instead of using a hardcoded address for PMC device BAR0, read it dynamically. This allows the allocator to move the BAR without needing a fixed resource. Note that we cannot do the same for the ACPI BAR (index 0x20), as it cannot be read back. Change-Id: If43e1ccb693ffb17b78bdd76140a0849493a0010 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com> Reviewed-on: https://review.coreboot.org/14633 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-09soc/intel/quark: Identify the console UARTLee Leahy
Pass the UART identifier to CorebootPayloadPkg Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: I9db1c31c3544d56b66f5a79ac8c3acee41788983 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14610 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09coreboot_tables: Extend serial port descriptionLee Leahy
Extend the serial port description to include the input clock frequency and a payload specific value. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device being used as the console UART. Specify this value as zero when the UART is not on the PCI bus. Otherwise specify the device using bus, device and function along with setting the valid bit. Currently the only payload to consume these new fields is the EDK-II CorebootPayloadPkg. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14609 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09util: ipq40xx: Scripts to combine SBL and Coreboot ELFsVaradarajan Narayanan
The IPQ40xx Primary Boot Loader (PBL, i.e. Boot-ROM) expects an ELF in the boot medium to load and boot. These scripts combine the Secondary Boot Loader (SBL) and Coreboot ELF to an image as expected by the PBL. BUG=chrome-os-partner:49249 TEST=Able to boot and reach depthcharge BRANCH=none Change-Id: I5d02b7f1f58bb23d81a3e19fb9b78f3a999b89f3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 819c7f2a810ca2880718ba14f2451f06eef4d98b Original-Change-Id: I017207b2d4108de150853f421aa7bcfd0e12e9a4 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340181 Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09libpayload: ipq40xx: Introduce timer and uart driverVaradarajan Narayanan
BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: Ibf2c91be93e2567cc1262b6fb84461eef51ab3e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b87157138302b017e64a28417a22421c880c1bcb Original-Change-Id: I16a8324d3c8ef4ee729f4509fda5bfe703b24ce4 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333304 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/14656 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/rk3399: protect the DRAM address for atfCaesar Wang
We need ensure the bl31 base is greater than 4KB since there's the shared mem for coreboot. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot to kernel with atf patch Change-Id: I44cf436b3072f03b93da4a19227dcc540d7513db Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a462f604c284c84bd8c5a0420e75eeae5035b382 Original-Change-Id: I55ec134762bb6bcbc91937ad5763617d7488490b Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342334 Original-Commit-Ready: Vadim Bendebury <vbendeb@google.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: https://review.coreboot.org/14741 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: move vop driver from rk3288 to rockchip commonShunqian Zheng
The rk3288 and rk3399 can use a common driver even that there are some different registers. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot from veyron_jerry and check display Change-Id: I510f68ba00308e47608d6e9921154a5c66ad8858 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1d857a7aa68d831a5007210255b121fed7a9e8de Original-Change-Id: I063e3eebc836debc01c450d8ab9f1524c9a47c56 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/341633 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/rk3288: Shuffle memlayout to make it fitJulius Werner
Another day, another overflowing RK3288 stage. There's almost 2K of space left in verstage/romstage (*gasp*, such waste!), so let's move one of them over to the bootblock. (We now have no whole kilobyte left that I can see...) BRANCH=None BUG=chromium:608439 TEST=Built Jerry Change-Id: Ice51d73ec0d89bcb1c927046be95630f177469c5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb7a101daba4f4f899a9c907b29d908661aa2dae Original-Change-Id: Ib72c0b3718aac38bc97c898a74aa5757e46cef0b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341742 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/14730 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: enable pp1500 and pp3000 rails as soon as possibleVadim Bendebury
The idea is that they stay low unless we know that we booted from SPI flash. As this code runs in SPI flash - it is ok to turn these rails on as soon as possible, and pp3000 rail it is essential for UART to work. Kevin rev1 and Gru designs are going to be using these pins to control these rails. Kevin rev1 had those GPIO pins routed to two chip enable signals, it is save to assert them high. BRANCH=none BUG=chrome-os-partner:51537 TEST=kevin rev0 still boots (which does not prove much) TEST=run coreboot on kevin rev1 to kernel Change-Id: I5f3eb4cf5d6f04a0253574dd8b5c039eab0bae1a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 987042246672e9391087dbd5060785a379dde131 Original-Change-Id: I31bb03334ad9e3aa57db726fb43dec85014a3f05 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/341543 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/14729 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: kevin: use board version specific SD detect GPIO pinVadim Bendebury
This change reflects Kevin schematics differences, Gru will have to be addressed separately. BRANCH=None BUG=None TEST=the code still works fine on Kevin proto 1. Change-Id: Iecae0e82e6bd4d185b49587b6053dcef8ad2162d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e821bbebe902a293b1e78cdd868f6bf3548ddd30 Original-Change-Id: Icd606285aeca1e19189f5e3d24c09b376942708b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340429 Original-Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/14728 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/rk3399: Set all 4 DVFS voltage rails to 1.1V @300kHzVadim Bendebury
Previous code had several problems: * It was only initting 3 of the 4 voltage rails hooked up to PWM regulators. * It was using a PWM frequency that was out of range. Apparently from testing 300kHz is best. * It was initting all rails to .9V. On my Kevin I needed 1.1V to make booting all 6 cores / rebooting reliable. With this fix both booting all 6 cores in the kernel is reliable (if we tell the kernel not to touch the PWM) and the "reboot" command from Linux userspace is also reliable (previously it crashed in coreboot). NOTES: * Setting all rails to the same voltage doesn't make a lot of sense. We should figure out what these should _actually_ be. Presumably the little CPU rail can be lower, at least. ...and we don't use the GPU in the BIOS so we should set that lower. BRANCH=none BUG=chrome-os-partner:51922 TEST=reboot test Change-Id: I44f6394e43d291cccf3795ad73ee5b21bd949766 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ac79a7cfb079d23c9d7c4899fdf18c87d05ed0e Original-Change-Id: I80996adefd8542d53ecce59e5233c553700b309f Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339151 Reviewed-on: https://review.coreboot.org/14727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: select 1.8V as gpio2ab io domainLin Huang
On kevin board, both the gpio2ab's io domain APIO2_VDDPST and APIO2_VDD are 1.8V. So gpio2ab can only output 1.8V. BRANCH=none BUG=chrome-os-partner:52510 TEST=Apply this patch, CPU1_SDIO_PWREN(GPIO2_A2) can output 1.8V Change-Id: Iefe58cf5ad83a8e79916ad177d148c1036283668 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c4afee265f3f31c1defee08cb89ab3e45ff8d1a Original-Change-Id: I0216c8efb7ef9256b878adeeee0a52335bf69f93 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/337194 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/*: refactor edp driverLin Huang
rk3288 and rk3399 use same edp IP, move soc specific setting to soc/display, and move edp driver to common, so rk3399 can reuse this driver. BUG=chrome-os-partner:52460 BRANCH=none TEST= test on jerry and mighty, edp panel can work Change-Id: Ie3f3e8468b2323994af8a002413bf93b3edc8026 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 64bb4b2c7ed373d9730c9aa0b0896a32164fc7ee Original-Change-Id: Ie5c15a81849a02d1c0457e36ed00fbe2d47961fb Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340504 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14725 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: add board nameVadim Bendebury
Gru is the common name of a set of coreboot boards, each of them has the config option BOARD_GOOGLE_GRU enabled. Now we need to add the actual board called Gru to the set. Let's rename the common config option to BOARD_GOOGLE_GRU_COMMON and use BOARD_GOOGLE_GRU for the actual board. BRANCH=none BUG=none TEST=with corresponding depthcharge and configuration space changes it is possible to build the Gru board which boots the kernel using the proper compatibility string of google,gru-rev0 Change-Id: I363d4b690b7549f50ed75d77b56e6a1e1d17b60f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 327ecc0de20ac0b93ec3cd28ef398393d4ea7c42 Original-Change-Id: Ia43278225c2d32d2af37193a77ea792551c9f8d9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340793 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14724 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip/spi: Allow SPI buses > 2Patrick Georgi
If SPI_BASEx is defined (for 2 < x <= 5), allow selecting it. Since the bus number translates into an offset into an array, require that all earlier buses are defined, too. Also assert() that the array is properly sized instead of blindly exceeding its bounds when called with a too big bus number. TEST=initializing bus 5 doesn't trap anymore on kevin BRANCH=none BUG=none Change-Id: I69f8ebe10854976608197a13d223ee8a555a9545 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c4af2a4ad4d6eea551653ca300ea6d04f1280919 Original-Change-Id: I27724d64d822ed0ec824a69ed611140bfbe08f5a Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Reviewed-on: https://chromium-review.googlesource.com/341034 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: Determine Board ID based on the input voltage of ADC1Vadim Bendebury
The Board ID on the Gru family of boards is determined by reading the voltage from a resistor divider, each hardware revision is supposed to have a unique resistor ratio, which allows to distinctly tell between different Board ID. While the long time approach to mapping resistor ratios (and voltages) into Board ID remains under discussion, we know for sure the values for Proto 1 and Proto 2. Let's just use them for now. Since Board ID can be queried multiple times during boot, ideally it should be read once and placed in the coreboot table to be available to all coreboot stages. For now we just cache it so that at least during the same stage the ADC has to run only once. BRANCH=None BUG=chrome-os-partner:51537 TEST=verified that the voltage reading on Proto 1 is as expected, and Board ID 0 is reported. Change-Id: I94bc7fc235dae4155feb6ca35b5ef0ab20c3ec9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bb4064d0af8174b6ae247cdad9378b7f4e5f22ba Original-Change-Id: I105ea97f8862b5707b582904c6f2e3e9406a0f07 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340428 Original-Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: https://review.coreboot.org/14722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/veyron_mickey: Increase RO CBFS size by 512 KbDavid Hendricks
This change increases the size of RO CBFS by 512 Kb to accommodate new images added to the INSERT screen. (This does the same thing as Daisuke's CL:338095, but for Mickey) BUG=chromium:604412 BRANCH=none CQ-DEPEND=CL:339495,CL:339511 TEST=emerge-veyron_mickey chromeos-bootimage Change-Id: Ib58247b2c89e436c6013f3ad59ad1cb80ba14964 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 897499bea5bd4003466ca7ebabff597e87da2e45 Original-Change-Id: I2cee79b2476fcb5bfb91bf9779f1fe11b4361612 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339542 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/14721 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: support saradcLin Huang
This patch add functions to configure saradc clk and get saradc's raw value for each channel. Currently add saradc to ramstage. Please refer to TRM V0.3 Part 2 Chapter 18 for this IP. BRANCH=none BUG=chrome-os-partner:51537 TEST=on kevin board, get the raw value 61 for channel 0, measure the ADC_IN0 as 0.109V, 61.0/1024 = 0.05957 0.109V/1.8V = 0.06056 Change-Id: Ic198b2a964ccf8bb687441f0e2702665402fff6e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc400316de2d75eccad3990a4187bf2dc49a844a Original-Change-Id: I542430ed97bd27f9bfcec89b1d703d9fa390d4e0 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/334177 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable arm trust firmwareLin Huang
BRANCH=none BUG=chrome-os-partner:51537 TEST=kernel is not stuck anymore and can boot into prompt, (testing with others patches) Change-Id: I74bdfa0ce608044a554bb3b06ed17b7157260294 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ca4e7a50c989ae0eff270df4fa160b80a172af31 Original-Change-Id: Id95d5f282ba49981f8e33da029e8710cd4087945 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332561 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14719 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: power up SD cardVadim Bendebury
Make sure SD card is powered up properly. Please refer to TRM V0.3 Part1 Page 324 for sdmmc pinmux. BRANCH=none BUG=chrome-os-partner:51537 TEST=With other patches, boot into chromeos prompt Change-Id: Ib53b05c1fce851ca7cbcc2207fce2dce3b1bfe9a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d37e688a458749e331a50c2ebf2018cba6629823 Original-Change-Id: I9f67c0bc16ddefa5ebe52a10c6d9e54194828a89 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/337192 Reviewed-on: https://review.coreboot.org/14718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: make sure sdram top does not spill into MMIO spaceLin Huang
The base address of MMIO space is different for different Rockchip SOCs. Define them in the appropriate address map files and use the definition in common code. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I615f3cadd6d5d994b7dd1defbd10d02ad5c994da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24f941e960e4a2cfb9fc26415f56e240de3d00d9 Original-Change-Id: Ia48d75e7de546b17636cde7829ee09837b9d7ac9 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/337190 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14717 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add sdram driverLin Huang
Add the sdram driver for rk3399. With this patch we can boot into depthcharge. This patch also include a config file for lpddr3-hynix-4GB that generated bases on its datasheet. Please refer to TRM V0.3 Part1 Chapter 9 for DMC. BRANCH=none BUG=chrome-os-partner:51537 TEST=boot to depthcharge on kevin Change-Id: I2afcaa3b68dbad77a5fe677b835289b675ed2bef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5d777e29942057fb7237eefa34051d1f54b19405 Original-Change-Id: Ifa1fe98a7058869518757d50678a64620610d91d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332562 Reviewed-on: https://review.coreboot.org/14716 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: init the secure settingShunqian Zheng
set sdram, sram and all device to non-secure status, so we can free to do mmu operation in coreboot. bl31 will care about secure control. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I11e02246550630c6dfe4e0cbad01e8cd5b83ef1e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ae2df532856110c4d87eb162fd3687f8de27c77f Original-Change-Id: Ia026cf685a9d7bdf7b0c7181b1b325c54bc4554f Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338947 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14715 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable pwmLin Huang
Reuse the rockchip common pwm driver. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I1a1ab237f891f06affb74817b5cae1a034a9760e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37afce0f94435ffef8bdd74b4251430f11ec22f4 Original-Change-Id: Ia94985f56e424d049fdcc5be86c696577d52a07c Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333255 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add gpio driverVadim Bendebury
Reuse the common gpio driver and implement some stubs in gpio.h. RK3288 has one pmu gpio while RK3399 have two. Please refer to TRM V0.3 Part2 Chapter 11 for GPIO section. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I041865ce269b0ae1f6a07e6c37d53d565a37c5ef Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d416ba0ce6a1ff2cf52f6b83ade601d93b40ffeb Original-Change-Id: I1d213a91ea508997b876441250743671204d7c53 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332560 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14713 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: refactor gpio driverShunqian Zheng
The gpio of rockchip SoCs(rk3288 & rk3399) are the same IP, moving the gpio code of rk3288 to common then can be reused on rk3399. BRANCH=none BUG=chrome-os-partner:51537 TEST=build and boot into chromeos on veyron_jerry Change-Id: I10a4b9d32afe60fd52512f2ad0007e9d2785033b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1c0c4b4b999790b0be7b0eeb70d2a7a86158f779 Original-Change-Id: If13b7760108831d81e8e8c950cdf61724d497b17 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/339846 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14712 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add i2c clock driverhuang lin
This patch add i2c clock driver and reuse the common rockchip i2c driver. The i2c0,4,8 src clock from ppll, while i2c1,2,3,5,6,7 from gpll. Please refer to TRM V0.3 Part1 Page 142 for i2c clock setting. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I91822e483244d71798a1c68f14ba0a84f405a665 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 270118e44d159f6a27812fa234b34fe7ac54cbe4 Original-Change-Id: Iea5f4a93cf173e1278166dcb04e19a4ef6c4af04 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/338948 Reviewed-on: https://review.coreboot.org/14711 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add spi clock driverShunqian Zheng
This patch implements spi clock driver and initialize SPI flash rom for the baseboard gru. There are 6 on-chip SPI controllers inside RK3399. For SPI3, it's source clk from ppll, while the others from gpll. Please refer to CRU session of TRM for detail. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I597ae2cc8ba1bfaefdfbf6116027d009daa8e049 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c6a9b0aedd427727ed4f4a821c5c54fb3a174b9 Original-Change-Id: I68ad859bf4fc5dacaaee5a2cd33418c729cf39b8 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338946 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14710 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09google/gru: enable uart2 if configuredShunqian Zheng
This patch select gpio pins for UART2 which is the default debug port of rk3399. Please refer to TRM V0.3 Part1 Page 325,395 for GRF details. BRANCH=none BUG=chrome-os-partner:51537 TEST=check logs from console manually Change-Id: I91eeadd543e7e895c3972d8dd7a2195c9d78968b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0c51955e18d4ff9cd3208697666af4fa77046e0f Original-Change-Id: I960178628f4020a59d100f2f0b2a6be487892549 Original-Signed-off-by: hunag lin <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/338945 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14709 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: enable mmuLin Huang
This patch initialize MMU and config mmu ranges for rk3399. During the bootblock phase, mark the max dram size supported(4GiB) as device memory because the mmio space start at 0xF8000000, and _sram as secure memory. After ddr setup in romstage, remark whole dram as cached memory except the _dma_coherent range. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I0cd4abb8c30b73d87d8ba6f964edd42bdf4813fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fc22ab0c16d8107c217db1629286d5ff1c4bc5b3 Original-Change-Id: I66bfde396036d7a66b29517937a28f0767635066 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332387 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14708 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: add functions to configure ddrc freqShunqian Zheng
This patch list four frequencies for ddr controller, 200MHz, 300MHz, 666MHz and 800MHz and configure each freq by setting the DPLL dividers. By default, the clk_ddrc is from DPLL and equals to DPLL, so here we only need to set the DPLL clock. BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2 Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/340184 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14707 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: support basic clock driverLin Huang
This patch initialize the PLL clocks and add function to configure cpu freq. Right now, we set the little cpu freq to 600MHz. In coreboot, we currently care about these four PLLs, o. APLL for cpu clk, where A stands for AXI, o. CPLL and GPLL are the generic PLL mainly for peripheral clk, o. PPLL is only PMU clk. For the peripheral clocks, there are thress clocks named as, aclk_perihp, aclk_perilp0, hclk_perilp1, where the 'h' and 'l' letters refer to High and Low speed. As the diagram below, the aclk_perihp always be the parent of more higher speed peripheral devices like pcie, and hclk_perilp1 for spi, i2c, aclk_perilp0 for crypto. These three clocks can choose parent from GPLL or CPLL freely, in this patch, they are all sourced from GPLL. GPLL(594M)/CPLL(384M) APLL(600M for little core) | | `-- aclk_perihp `-- clk_core(600M == APLL) | | | | `-- periph_aclk(148.5M) `-- atclk_core(300M) | `-- periph_hclk(148.5M) `-- aclkm_core(300M) | `-- periph_pclk(37.125M) `-- pclk_dbg_core(100M) | `-- hclk_perilp1 | | | `-- periph_hclk(99M) PPLL(594M) | `-- periph_pclk(49.5M) | | `-- pmu_pclk(99M) `-- aclk_perilp0 | `-- periph_aclk(99M) `-- periph_hclk(99M) `-- periph_pclk(49.5M) BRANCH=none BUG=chrome-os-partner:51537 TEST=emerge-kevin coreboot Change-Id: I1c46ff17e6b466529244afb41d7fd4abbcfd3da4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9f0d31177336a3450577950426f9cc9d56e2254c Original-Change-Id: I4ad00df3e406bd0a7576287d6e62b8993a8c2d02 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332386 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/14706 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09rockchip: rk3399: use static pointers to regs as they compile to faster codeVadim Bendebury
Quoting an earlier review comment, using static structures pointers in the include file "should allow the compiler to optimize accesses better than defining it in a separate compilation unit (by being able to constant fold stuff like &rk3399_pmusgrf->field into a single address, rather than loading the symbol, loading an offset constant and adding)". Any decent compiler linker system nowadays would consolidate this definition in any case. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied Kevin successfully boots Linux kernel. Change-Id: Ibb576c7691a30f2f429651fcca133bd72710c13b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89b6f22e37f733667156f15afb8c27d8a9f07512 Original-Change-Id: Ice8d6d766a91e7f4fce553378a23b9ca593d12dd Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/339869 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14705 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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