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2017-09-02cpu/x86/smm: Fix explicit 'addr32' usage in clang buildsEdward O'Callaghan
The addr32 prefix is required by binutils, because even when given an explicit address which is greater than 64KiB, it will throw a warning about truncation, and stupidly emit the opcode with a 16-bit addressing mode and the wrong address. However, in the case of LLVM, this doesn't happen, and is happy to just use 32-bit addressing whenever it may require it. This means that LLVM never really needs an explicit addr32 prefix to use 32-bit addressing in 16-bit mode. Change-Id: Ia160d3f7da6653ea24c8229dc26f265e5f15aabb Also-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-02soc/intel/cannonlake: Use common mca_configure() APIPratik Prajapati
Use mca_configure() API from cpulib to configure Intel Machine Check Architecture (MCA) Change-Id: Ib4943a7f7929775bd5e9945462e530ef68a398b8 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-02soc/intel/skylake: Use common mca_configure() APIPratik Prajapati
Use mca_configure() API from cpulib to configure Intel Machine Check Architecture (MCA) Change-Id: Ia96cb82fff3def46dbecb09dee94de86f179abe6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-02intel/common/cpulib: Add API to configure MCAPratik Prajapati
Add mca_configure() API to configure Intel Machine Check Architecture (MCA). Change-Id: I5e88c7527ce350824e48892caa978b2b78f1de20 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-02util/lint/checkpatch: Untaint variables from env & command lineMartin Roth
Jenkins is giving warnings due tainted variables from the environment and command line: Insecure $ENV{PATH} while running setgid at util/lint/checkpatch.pl line 907, <$conststructs> line 39. Insecure dependency in piped open while running setgid at util/lint/checkpatch.pl line 907, <$conststructs> line 39. This should fix those warnings. Change-Id: I6a09915d13547bf9a86c011d44cbcd39c46f3fec Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-02nb/intel/pineview: Enable dram remappingArthur Heymans
Without this remapping code enabled, the system fails to boot properly if the amount of ram inserted is larger than 4G minus the mmio space (hardcoded to 1G here). Change-Id: I02e7ceed0cd9db7eb7182481b6989f80cef31ee5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-01soc/intel/cannonlake: Define Max PCIE Root PortsPratik Prajapati
This patch defines Max PCIE Root Ports and fixes bellow Coverity scan defect, *** CID 1380036: Control flow issues (NO_EFFECT) /src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params() 79 >>> CID 1380036: Control flow issues (NO_EFFECT) >>> "i" is converted to an unsigned type because it's compared to an unsigned constant. 80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { 81 if (config->PcieRpEnable[i]) 82 mask |= (1 << i); Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: add *spi.c files to makeNick Vaccaro
Adds spi.c and gspi.c to verstage. Change-Id: I363d9aafa989c5a7a0b36ad9edf1c70a75604d28 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: add gpio files to makeNick Vaccaro
Adds gpio.c to romstage and ramstage. Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS. Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01nb/intel/i440bx/debug.c: Bugfix and cleanupKeith Hui
Fix dump_pci_device() broken by commit 65b72ab5 (Drop print_ implementation from non-romcc boards) in 2015 (!) where only one in 16 bytes were being dumped. Also remove the #if made redundant by commit aef8542 (Compile debug.c only if CONFIG_DEBUG_RAM_SETUP) as this whole file is only compiled in that case. Also clean up headers that were included twice. Change-Id: I60e272b29417039feb15540e49d7300f86e5ed21 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-01intel/i440bx: Move LATE_CBMEM_INIT under mainboardKyösti Mälkki
Some of these will move to EARLY_CBMEM_INIT. Change-Id: Ia969e30ad7097860180bd047eaf81859a42a747c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Keith Hui <buurin@gmail.com>
2017-09-01buildgcc: Integrate nds32 update from Andes TechnologyStefan Reinauer
This patch has been provided by Mentor Chih-Chyang Chang on behalf of Andes Technology. It fixes using the coreboot toolchain to compile the Chrome EC code base on the ITE8320 embedded controller. The new patch incorporates a fix for the issue previously fixed by patches/gcc-6.3.0_nds32.patch, so that patch can be removed. patches/gcc-6.3.0_riscv.patch needs to be slightly adjusted to still apply cleanly (configure scripts only). Change-Id: I0033888360f13ba951b692b3242aab6697ca61b3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-09-01soc/intel/canonlake: Enable LPSS UART in 32bit PCI modeLijian Zhao
Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode. To maintian compatibilty with previous generation of SOC, select 32 bit mode as default. Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01lippert/toucan-af: Switch away from AGESA_LEGACYKyösti Mälkki
NOTE: Some code was currently left behind that may be required for certain type of board reboots. A followup patch will address this. Change-Id: I8fb89fb82c3a3608bb84b29319eb793605538996 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01lippert/frontrunner-af: Switch away from AGESA_LEGACYKyösti Mälkki
NOTE: Some code was currently left behind that may be required for certain type of board reboots. A followup patch will address this. Change-Id: I3c1258b4e4dcf6fd04f57f5ab59cb1572a7d1fa3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/cannonlake: Perform dram top calculation based on HW registersSubrata Banik
This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot cannonlake RVP successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. 6. Enable C6 DRAM with PRMRR size 0MB and boot to OS. Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/apollolake: Use SMM library to get tseg region informationSubrata Banik
This patch uses smm common library function to get tseg base address and size. Hence removing definitions of smm_region() from soc directory. BRANCH=none BUG=b:63974384 TEST=Build and boot reef successfully. Change-Id: I091ca90cf576c0da35cf3fe010f8c22a18ef82d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/skylake: Use SA library to get smm region informationSubrata Banik
This patch uses system agent common library to know tseg region start and size. Unable to remove smm_region() function from soc code as SMM common library is not yet available for skylake use. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: If98b65805753db2c30d6fea29e401a17cef39799 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-31google/gru: Support Nefario rev0Philip Chen
Do not assert GPIO1_B3 otherwise BT would be disabled on Nefario. Also, remove DVS support for CENTERLOGIC. BUG=b:64702054, b:63537905 TEST=build coreboot Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/21176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-31lenovo/g505s: Switch away from AGESA_LEGACY_WRAPPERKyösti Mälkki
Change-Id: Ia65f9ecb62767424744e399a43e4728666fd28b3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-31lenovo/g505s: Enable XHCI device in devicetreeKyösti Mälkki
Enabling XHCI is additionally controlled with Kconfig option HUDSON_XHCI_ENABLE. Even when it is enabled, it EHCI debug works on the USB port next to the DVD drive door. Change-Id: I83738da6015f58ecd0819c553d333a176365dc78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-31AGESA: Remove separate f15rlKyösti Mälkki
Change-Id: I18c62ad034249c5ad14e5d5e708b4f0d4bcbf400 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-31lenovo/g505s: Switch from f15rl to f15tnKyösti Mälkki
Support code for Trinity and Richland is identical now. I have also come across a unit with Trinity model CPU, whose CPUID was not listed in f15rl while f15tn already had support for f15rl. Change-Id: Ia869429b75a9b308b4d4a84f16914ca629b1b1b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-31cpu/x86 asm: Just use the correct op suffixEdward O'Callaghan
LLVM AS doesn't support as much GNU junk extensions, data16/32 is almost never needed in truth if we just use the correct op suffix. So do that here, fixes clang/llvm builds with the integrated-as toggled on. Change-Id: I6095d03d0289b418a49a10f135de5eb0e117cae0 Also-by: Damien Zammit <damien@zamaudio.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/21218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-31AGESA f15 vendorcode: Remove unused sourcesKyösti Mälkki
Change-Id: Id1ed36e7e76d25cdc9e86254b108deaca0f8b423 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f15 vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: I1b7d7c017a4dfd93c5befbc0d5858278eacc6c89 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f16kb vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: Id3d9a365469f7d73788cad4095ec3495fc9baf3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f15tn vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: I2a6e53e5555a1b1e19c45a196b21f8505e275a76 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f14 vendorcode: Remove unused sourcesKyösti Mälkki
Change-Id: Ie4a735b156ded934fac0c9248fbb9042bf9be781 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f14 vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: I6dbcd23b0ea03b1b965d43346ae1cf7cf1971eb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f12 vendorcode: Remove unused sourcesKyösti Mälkki
Change-Id: Ia22c96ee19babb3fc64d57966ea923eb5ec4b48f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-31AGESA f12 vendorcode: Split to Makefile.inc filesKyösti Mälkki
Change-Id: I8438dc468e59174bd6f88c0c02b2fbf60587dbfd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-30soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLESubrata Banik
This patch to avoid build bot hang issue due to no active default value for UART_FOR_CONSOLE kconfig option. Change-Id: I70ca5dc6c4bde6a119ad59d8c58955c96c042198 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21287 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30mainboard/google/soraka: Add stop gpio control to touchscreen deviceFurquan Shaikh
BUG=b:64987428 TEST=Verified that touchscreen works on boot-up and after suspend/resume. No power leakage via stop gpio in suspended state. Change-Id: Ia260eb444081dbe1646c90e82c2725661e7306bc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-08-30acpigen: Add stop gpio control to power resourceFurquan Shaikh
There is at least one I2C device (being used by Soraka) that has 3 controls -- enable, reset and stop. If the stop gpio is not put into the right state when turning off the device in suspend mode, then it causes leakage. Thus, we need control in power resource to be able to stop the device when entering suspend state. BUG=b:64987428 TEST=Verified on soraka that touchscreen stop is correctly configured on suspend. Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21249 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-30mainboard/google/soraka: Remove Atmel TouchscreenFurquan Shaikh
We no longer use this touchscreen device, so get rid of it. BUG=b:64987428 Change-Id: I67af787d231317a80998fb483eed5674de19aeb4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30google/cyan: update SPD functionsMatt DeVillier
Update cyan's SPD-related functions to more closely mirror those of other Braswell boards, in order to simplify the upcoming baseboard/variant setup for Braswell ChromeOS boards. TEST: boot google/cyan, observe SPD correctly identified in cbmem log, RAM-related data correct in SMBIOS tables. Change-Id: Iafe99ec0795764f645e0a91f5b321be5b4c6fd88 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-30drivers/i2c/ck505: Add generic driver to configure clockgenArthur Heymans
Replaces the ics/954309 driver with a more generic version to accommodate clockgens with a different amount of registers. It also features a mask to only touch certain bits of the clockgen. TODO: set appropriate mask for X60/T60 since the datasheets for their clockgens can be found. Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-08-30soc/intel/common: Add functions into common SMM librarySubrata Banik
This patch to add helper function to get SMM region start and size based on systemagent common library. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: If10af4a3f6a5bd22db5a03bcd3033a01b1cce0b4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30soc/intel/common: Add functions into common system agent librarySubrata Banik
This patch to add helper function to get tseg memory base and size for HW based memory layout design. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: I4c8b79f047e3dc6b2deb17fdb745f004004526b6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30soc/intel/cannonlake: Add PrmrrSize and C6DRAM configSubrata Banik
This patch ensures coreboot can set PRMRR size and C6DRAM enable FSP-M UPDs. Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30mb/google/eve: rt5514: Add 16ms delay on dmic initDuncan Laurie
Add a 16ms delay to DMIC init by the kernel driver in order to prevent an audible 'pop' noise when starting to record. BUG=b:63413023 TEST=manual testing to ensure this device property is present in SSDT: Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") Package () { Package () { "realtek,dmic-init-delay", 0x10 } } }) Change-Id: If9160ce6992153ba49719029de336595bbf4ae72 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/21271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30drivers/i2c/generic: Support additional device propertiesDuncan Laurie
Add support for providing additional free form device properties via devicetree in order to make this driver suitable for kernel drivers that need additional board-specific device properties. This currently allows adding up to 10 additional properties to a device. BUG=b:63413023 TEST=manual testing to ensure that newly added properties are in SSDT Change-Id: I2b8ceb208f4aba01053746547def6d07c8f8f3a2 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/21270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30acpi_device: Provide a new function to add a list of propertiesDuncan Laurie
Provide a new function that will allow adding arbitrary properties to devicetree entries without needing a custom driver for the device. This will allow the 'generic i2c' driver to support kernel drivers that need additional device properties exposed and have those board specific properties set with values from devicetree. BUG=b:63413023 TEST=not used yet, compiles cleanly Change-Id: Id272256639a8525406635e168a3db5ab1ba4df6b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/21269 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30sb/intel/*: add option to lockdown chipset on normal boot pathBill XIE
On platforms with a PCH, some registers within host bridge should be locked down on each normal boot path (done by either coreboot or payload) and S3 resume (always done by coreboot). A function to perform such locking is implemented in src/northbridge/ intel/*/finalize.c, and is designed as the handler of an #SMI triggered with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only triggered during s3 resume, and not on normal boot path. This problem has beed discussed in https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html . This time, an option "INTEL_CHIPSET_LOCKDOWN" within src/southbridge/ intel/common/Kconfig is added to control the actual locking, which depends on several compatibility flags, including "HAVE_INTEL_CHIPSET_LOCKDOWN". In this commit, "ibexpeak", "bd82x6x", "fsp_bd82x6x", and "lynxpoint" have the flag "HAVE_INTEL_CHIPSET_LOCKDOWN" selected. The change is only well tested on Sandy Bridge, my Lenovo x230. Change-Id: I43d4142291c8737b29738c41e8c484328b297b55 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/21129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-08-30ec/google: Use feature flag layout that matches the EC host commandPatrick Georgi
The EC side of the feature bits in ACPI EC space isn't stable yet, and we're now going for matching them up with the EC host command of the same purpose. Change-Id: I9c1f0e5390e840ea0c32315a3da8eea6f3e12f54 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30AGESA: Drop Kconfig CPU_AMD_SOCKET_AM3R2Kyösti Mälkki
Never selected in our tree. Change-Id: I5065903ebf74d281ecccaf53e0cc9fa24317e1cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-30AGESA f15 vendorcode: Remove AM3r2 refcodeKyösti Mälkki
We never had a board in the tree that implements this. If you are interested in implementing such board, note that also f12 and f14 had copies of the same refcode. As part of the sourcetree cleanup it was not studied which was the most up-to-date one for AM3r2. Change-Id: Ic7dd065c0df08c22af6f3a2dcfc7ff47d6283a46 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-30AGESA f14 vendorcode: Keep only Ontario refcodeKyösti Mälkki
The only subtree we build is /ON. Change-Id: I8cb11211a2a5ab7d8ae6296b601ee09146a9c9f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-30AGESA f12 vendorcode: Keep only Liano refcodeKyösti Mälkki
The only subtree we build is /LN. Change-Id: I035932a4be41fa0451a3f3c7be33442afeeb5571 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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