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2019-04-11Documentation: Allow the use of CSVPatrick Rudolph
Allow the use of CSV files if properly referenced from markdown. Sphinx will parse the file and create a human readable table, allowing easy integration of autogenerated files. Change-Id: I6fa13acf67ff1c6c9e3985054405c5446808da03 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-11Documentation: Add coreboot architecturePatrick Rudolph
Describe the coreboot stages, given a short introduction what is done and add a chart for coreboot's vs EDK II bootflow as well as the source for the SVG. TODO: Describe stages in detail in a separate commit. Change-Id: I98cb61b1d0d29ac9d03f5ef3644d51a8e14bad74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-10mb/ocp/monolake: Add board.fmdAndrea Barberio
Change-Id: I6095c3b30990b530c5bc4e2c808879252680e1d7 Signed-off-by: Andrea Barberio <barberio@fb.com> Signed-off-by: David Hendricks <dhendrix@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-10Doc/mb/asrock/h110m: update info about PEGMaxim Polyakov
- Now there is no need to additionally configure the FSP before building; - PEG works with high link speed 8 GT/s (Gen 3); - external GPU supported, but dynamic switching between iGPU and PEG is not yet supported. Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31949 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-10libpayload: Deduplicate strtol and strtoullJulius Werner
Our strtol() and strtoull() function contain almost exactly the same code. This is a) bad in general and b) may cause the code to get out of sync, such as it recently happened with CB:32029. This patch changes strtol() to be based on strtoull() so that the main parsing code exists only once, and also adds a strtoll() to round off the library. Also fix the bounds imposed by strtoul() to be based on the actual length of a 'long', not hardcoded to 32-bits (which is not equivalent on all architectures). Change-Id: I919c65a773cecdb11739c3f22dd0d182ed50c07f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-10libpayload: limits.h: Provide reliable definitions for all XXX_MAX/MINJulius Werner
Our current limits.h only provides (U)INT_MAX constants. This patch adds most others expected by POSIX. Since some of these may be different depending on architecture (e.g. 'long' is 32-bit on x86 and 64-bit on arm64), provide a definition that will automatically figure out the right value for the data model the compiler is using (as long as it's using two's complement for signed integers, which I think we can assume these days). Change-Id: I1124a41279abd4f53d208270e392e590ca8eaada Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-10libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archsJulius Werner
New compilers are a little more stringent about defining the same prototype more than once, so some of our CONFIG_LP_DEBUG_MALLOC wrappers don't quite work the way they are written anymore. Also, several of the printf()s weren't written 64-bit safe. And let's add some double-evaluation safety while I'm here anyway... and I have no idea why this ever depended on CONFIG_LP_USB, that just seems like a typo. Change-Id: Ib54ebc3cfba99f372690365b78c7ceb372c0bd45 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/14921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-09libpayload: Fix potential NULL pointer dereferenceFrancois Toguo
Found-by: Klockwork BUG=NONE TEST=Boot to OS on GLK Sparky Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com> Change-Id: I9d4636f0429de829e746909492c2f543026a02ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/32083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-09nb/intel/sandybridge: Set uninitialized run lengthJacob Garber
If the entire array is zero, then the length of the longest zero run is the length of the array itself. Found-by: Coverity Scan, CID 1229715 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Id23292087b14182448d70117915fb044e9c579f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-09google/kukui: Configure AP_IN_SLEEP_L correctlyYou-Cheng Syu
This pin should be set to its alternative function SRCLKENA0 instead of GPIO, so that SPM (a power management component of MT8183) can control it. BUG=b:113367227 BRANCH=none TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0. 2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then run 'powerinfo' in EC console and see power state in S3. 3. Wait until AP resume. 4. Run 'powerinfo' in EC console and see power state back to S0. Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09mb/google/hatch: Support 16MiB fmapPhilip Chen
Add a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flash ROM chips. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-09arch/x86/smbios: Reference type 7Patrick Rudolph
Fill in the handle to cache entries of type 7 in the type 4 structure. Tested on Intel Sandy Bridge (Lenovo T520). All 3 caches are referenced. Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09arch/x86/smbios: Add type 7Patrick Rudolph
The SMBIOS spec requires type 7 to be present. Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the "Deterministic Cache Parameters" as available on Intel and AMD. As CPUID only provides partial information on caches, some fields are set to unknown. The following fields are supported: * Cache Level * Cache Size * Cache Type * Cache Ways of Associativity Tested on Intel Sandy Bridge (Lenovo T520). All 4 caches are displayed in dmidecode and show the correct information. Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09arch/x86/cpu: Add functions to determine CPU vendorPatrick Rudolph
Add two functions to determine if CPU is made by a specific vendor. Use Kconfig symbols to allow link time optimizations. Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Julien Viard de Galbert <coreboot-review-ju@vdg.name> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-09mb/google/hatch: Add ACPI support for BT reset functionalityTim Wawrzynczak
Expose the Bluetooth BT_DISABLE_L signal in Hatch's devicetree, on both USB2 port 5 and 10. BUG=b:123293169 BRANCH=none TEST=compiles, verified kernel is able to find the reset-gpio Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32216 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09src: Fix remaining #include <timer.h>Nico Huber
Follow-up to add76f91d5 (src: Use #include <timer.h> when appropriate). Change-Id: I7813daa0b73039ec76d33a16ce3ae0ce6cc7f2cc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-09util/docker: Update coreboot-sdk Dockerfile for new debian imageMartin Roth
libssl1.0-dev is no longer available: - Update to libssl-dev - Add libcrypto++-dev to provide additional crypto libraries not available in libssl-dev. Change-Id: Ie10e14ebf7ae849301302008ee6ffeec1f40ccab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-08mb/facebook/watson: Make turbo mode configurable (disabled by default)David Hendricks
Change-Id: Ief1eaab960c8fdab5bd5041b1a4f0c6ba1dd833f Signed-off-by: David Hendricks <dhendrix@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32222 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08Docs/kconfig: Update to use CONFIG()Nico Huber
Change-Id: Ica7b601d1c9c3bcf39b8b805d48e969f8a944927 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-08nb/amd/pi/agesawrapper: Drop stale comment about IS_ENABLED()Nico Huber
We decided to not care about compile-time errors. So drop the comment, the code was updated already. Change-Id: Ib115fa6e2c48bfde7f67c327d42b3fe0e7af8c1f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-08commonlib/cbfs: Check for presence of CONFIG() macroNico Huber
Check for CONFIG not IS_ENABLED, as we use the former now. Change-Id: I7e1b67bc0894ca6f0149039054449656b58bcdd3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-08soc/amd/stoney: Don't use IS_ENABLED() for a constantNico Huber
IS_ENABLED() was supposed for Kconfig options. Change-Id: Ia40d64856cd89586133e54ff6e02c35d6b647059 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32225 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()Nico Huber
Another run of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I3243197ab852a3fbc3eb2e2e782966a350b78af2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-08libpayload/drivers/timer: Use 64 bits to prevent overflowJacob Garber
Cast cpu_khz to a 64 bit integer to prevent possible integer overflow (the multiplication is currently done using 32 bit math). Similar to 61dac13 (libpayload: timer: cast cpu_khz to make sure 64bit math is used). Found-by: Coverity Scan, CID 1261177 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Iadb0abb7c7cc078f31a6d88d971f5d1b8ac62a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-08nb/intel/pineview: Correct lsbpos(0) and msbpos(0)Jacob Garber
lsbpos and msbpos have incorrect behaviour when given 0. lsbpos(0) returns 8, and msbpos(0) hangs. The latter is because the check i >= 0 is always true for an unsigned integer, causing it to loop indefinitely (this was flagged by Coverity). 0 doesn't have a lsb or msb position, so we change both functions to return -1 in this case to indicate an error. The code already guards against calling these functions with 0, but we make this more explicit to prevent errors in the future. Found-by: Coverity Scan, CID 1347356, 1347386 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ic5be50846cc545dcd48593e5ed3fd6068a6104cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/32054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-08soc/intel/baytrail: Correct array bounds checkJacob Garber
If `gms == ARRAY_SIZE(gms_size_map)`, then we will have an out of bounds read. Fix the check to exclude this case. This was partially fixed in 04f68c1 (baytrail: fix range check). Found-by: Coverity Scan, CID 1229677 (OVERRUN) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I8c8cd59df49beea066b46cde3cf00237816aff33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-08nb/amd/pi, mb/amd/bettong: Fix null pointer checksJacob Garber
The dev pointers were being dereferenced before the null check. Move the checks so they are done earlier. Found-by: Coverity Scan, CID 1241851 (REVERSE_INULL) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ie578787c3c26a1f3acb4567c135486667e88a888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-08soc/skl: Update SkipExtGfxScan in UPD from devtreeMaxim Polyakov
The SkipExtGfxScan option is defined in the device tree, but doesn`t update the value in the UPD. It uses the default value - 0. This means that the FSP will scan all external graphics devices, in spite of the configuration in devicetree.cb for a specific board. Patch updates SkipExtGfxScan options in UPD from devicetree.cb. This change affects all boards with skl/kbl processor. Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-08siemens/mc_apl5: Remove reduced clock rate for I2C0Mario Scheithauer
There is no device on I2C0 which requires a lower clock rate. Change-Id: Iaf01be5ea4839c54eb2f0ba95bca272970c24bdb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-08src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMIMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia296a680217a38136c063cae6ed619df0c497795 Reviewed-on: https://review.coreboot.org/c/coreboot/+/30753 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08{src,util}: Correct typo in comment and debug stringFrans Hendriks
Correct typo in comment and debug string. BUG=N/A TEST=build Change-Id: I0362bb8d7c883e7fcbc6a2fc2f9918251f0d8d6e Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29321 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08mb/mainboard/google/sarien/variants: Set correct tcc_offset valueSumeet Pawnikar
Set new tcc_offset value to 10 degree C. This configures the Thermal Control Circuit (TCC) activation value to 90 degree C. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action when CPU temperature goes above 90 degree C. Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-08mb/google/sarien: Add support for melfas touch panelEric Lai
Add a support melfas touch panel with i2c address:0x34. BUG=b:122019253 TEST=tested with new melfas touch panel and worked Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I27f5c47517d093c819cbbbcdafd85d74145887e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32169 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08src/soc/intel/cannonlake: Remove ITSS IPC restoreAamir Bohra
Remove ITSS IPC restore for cannonlake, as it does not take effect since the ITSS PCR registers are locked post FSP-S. Change-Id: Ie39e0d43644cb7b03b6c3432f0965f1d76d1bc37 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-07vc/amd/agesa/f14: Add missing break statementJacob Garber
We do not want to ASSERT(FALSE). Found-by: Coverity Scan, CID 1241850 (MISSING_BREAK) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ia08bb519cdb5ef5d2a79898706c7fac7e58adf3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-07sb/intel/{common,i82801dx}: Improve TCO debug codeJacob Garber
Report unhandled TCO bits (previously dead code). This finishes the work done in 3e3b858 (sb/intel/ibexpeak: Update debug code to match other chips). Found-by: Coverity Scan, CID 1229598 (DEADCODE) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I65df8f3363c62b364e096368a36ba5e9e8894c13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32179 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-07device/pci: Rewrite PCI MMCONF with symbol referenceKyösti Mälkki
The effect of pointer aliasing on writes is that any data on CPU registers that has been resolved from (non-const and non-volatile) memory objects has to be discarded and resolved. In other words, the compiler assumes that a pointer that does not have an absolute value at build-time, and is of type 'void *' or 'char *', may write over any memory object. Using a unique datatype for MMIO writes makes the pointer to _not_ qualify for pointer aliasing with any other objects in memory. This avoid constantly resolving the PCI MMCONF address, which is a derived value from a 'struct device *'. Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-06mb/amd/bettong/mainboard: Drop unused include <agesawrapper.h>Elyes HAOUAS
Change-Id: I020c1b9558f6aec47b048fa575c64c619b8c592a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32013 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06src: Use #include <timer.h> when appropriateElyes HAOUAS
Also, extra-lines added or removed and local includes moved down. Change-Id: I5e739233f3742fd68d537f671642bb04886e3009 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32009 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06Doc/mb/asrock/h110m: Fix the linksMaxim Polyakov
Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-06mb/asrock/h110m: Add PEG Gen3 supportMaxim Polyakov
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16 slot. All parameters for FSP are set during initialization in romstage. Now there is no need to additionally configure the FSP before building the ROM image. Tested on Intel Core i5-6600 processor with the following devices: - LP11000e Fibre Channel HBA (Gen2 x8); - PEX8734 PCIe Fabric/Switch (Gen3 x16); - NVIDIA GeForce GTX 1060 GPU (Gen3 x16). GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2 (4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used as primary device for display output. Dynamic switching is not yet supported. Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload. Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31948 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06soc/intel/skylake: Set FSP options for PEG portMaxim Polyakov
FSP options list (for each PEG port): - PegXEnable, - PegXMaxLinkWidth, - PegXMaxLinkSpeed, - PegXPowerDownUnusedLanes, - PegXGen3EqPh2Enable, - PegXGen3EqPh3Method. Add PegMaxLinkWidth to chip.h. This option overrides the number of active lines from the devicetree.cb for each enabled PEG port (for example for boards that use x4 instead of x16 lines in PEG0). If the PegMaxLinkWidth is not defined, the port uses the maximum possible number of lines. To enable or disable the corresponding PEG root port you need to add to the devicetree.cb: device pci 01.0 on end # enable PEG0 root port device pci 01.1 off end # do not configure PEG1 If PEG port is not defined in the devicetree, it will be disabled in FSP. It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU). Change-Id: I23708f7060edf08739adf61fe61a419329907563 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32045 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-06mb/asrock/h110m: Set PEG as primary GFX deviceMaxim Polyakov
If an external graphics card is inserted in the PEG, it will be used as the primary display device (as in the AMI BIOS) Change-Id: Iea846179fc309c2b98093de37c05ceb332081f4f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-06{mb,soc/intel/skylake}: remove unused InternalGfxMaxim Polyakov
The InternalGfx option in devicetree.cb is not used to enable iGPU. The patch removes this option from chip.h and mb/*/devicetree.cb files for all boards with skl/kbl processor. Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-06soc/intel/skylake: Update GFX devtree optionsMaxim Polyakov
This patch includes the following changes: 1. Sets FSP options in romstage_fsp20.c to select primary GPU. List of options: - InternalGfx, - PrimaryDisplay. 2. iGPU will be initialized if the corresponding PCI device is defined in the device tree as: device pci 02.0 on end In this case, it is not necessary to set the InternalGfx option to enable this device 3. Primary_iGFX is used as the default value for all skl/kbl boards (since the PrimaryDisplay option isn`t defined in the devicetree.cb) Change-Id: Ie3f9362676105e41c69139a094dbb9e8b865689f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-05libpayload: Align main() data typesPatrick Georgi
One of many steps to compile with -Wconversion, as unsigned int and int aren't the same thing. BUG=b:111443775 BRANCH=none TEST=make junit.xml shows fewer warnings with -Wconversion enabled Change-Id: I9673ca70da32a1e5117b27fa89167e03379af9c1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-05drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failureFrans Hendriks
RTC time contains invalid values on system without RTC battery. Handle 'invalid' the same way as 'cmos_invalid'. This will reset CMOS date when calling function enables 'invalid'. BUG=N/A TEST=Portwell PQ-M107 booting Linux Embedded Change-Id: I5eae57d00f328400a8b03c28b7ecdbbc71522206 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29329 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04Make common macros double-evaluation safeJulius Werner
I just got hit by a double-evaluation bug again, it's time to attempt to fix this once more. Unfortunately there are several issues that don't make this easy: - bitfield variables don't support typeof() - local macro variables that shadow others trigger -Werror=shadow - sign warnings with integer literal and unsigned var in typeof-MIN() - ({ statement expressions }) can not be used outside functions - romcc doesn't support any of the fancy GCC/clang extensions This patch tries to address all of them as far as possible with macro magic. We don't have the technology to solve the bitfield and non-function context issues yet (__builtin_choose_expr() still throws a "no statement expression outside a function" error if it's only in the branch that's not chosen, unfortunately), so we'll have to provide alternative macros for use in those cases (and we'll avoid making __ALIGN_MASK() double-evaluation safe for now, since it would be annoying to do that there and having an alignment mask with side effects seems very unlikely). romcc can continue using unsafe versions since we're hopefully not writing a lot of new code for it. Sign warnings can be avoided in literal/variable comparisons by always using the type of the variable there. Shadowing is avoided by picking very explicit local variable names and using a special __COUNTER__ solution for MIN() and MAX() (the only ones of these you're likely to nest). Also add DIV_ROUND_UP() to libpayload since it's a generally quite useful thing to have. Change-Id: Iea35156c9aa9f6f2c7b8f00991418b746f44315d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-04mb/google/hatch: Move I2C/SPI options to override treeFurquan Shaikh
This change moves the I2C/SPI devices and configs which do not apply to all variants to override tree. Currently, there are just two variants. However, as we prepare to add more variants, these devices need to be moved out of the base devicetree. BUG=b:129728235 TEST=Verified that I2C/SPI devices are present in static.c for hatch and hatch_whl. Change-Id: I9426f6bf5f8514de5f1889e22e57105749fd92de Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32138 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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