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2019-05-29soc/intel/common: Check bios_size and window_size after MIN operationJohn Zhao
Clang Static Analyzer version 8.0.0 detects that log2_ceil(bios_size) and log2_ceil(window_size) are garbage or undefined if the value of bios_size and window_size is zero. Check bios_size and window_size after MIN operation to prevent error. TEST=Built and boot up to kernel. Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-29soc/intel/common: Set GSPI clock value to prevent division by zeroJohn Zhao
Clang Static Analyzer version 8.0.0 detects the division by zero if gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to prevent the division by zero in DIV_ROUND_UP operation. Then the value of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value. TEST=Built and boot up to kernel. Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-29util/autoport: Add info about rank 1 mirroringEvgeny Zinoviev
inteltool can't detect whether address mapping is normal or mirrored, which in turn may be cause RAM initialization to fail when using spd.bin generated by inteltool. Mention this in readme as it may help someone. Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87 Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-29drivers/intel/fsp2_0: Dont' use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: Ic50b16916261abb8c63b8fe571819af5c830ff8d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29soc/intel/common/pmc: Don't use CAR_GLOBALArthur Heymans
All platforms using this code use NO_CAR_GLOBAL_MIGRATION. Change-Id: I426dee60521045db4711cd253432c65223a64b93 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29soc/intel/common/cse: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: If952ad8129e1fa6e45858cb77ec99c9fec55c4a6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29soc/intel/common/cse: Declare g_cse staticallyArthur Heymans
Change-Id: I91b6ce3b52d987e2fc0f79e550fda2891502bfe8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29drivers/emulation/qemu_debugcon: Don't use CAR_GLOBALArthur Heymans
This platform uses NO_CAR_GLOBAL_MIGRATION. Change-Id: Idc9434e5a1a8bc5ed76a9f80c9a7cfba2fd474c0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29soc/intel/common/gspi: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I5dfbc718fd82f0511b0049383e4e93c6f15ee932 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32999 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29soc/intel/quark: Don't use CAR_GLOBALArthur Heymans
This soc has NO_CAR_GLOBAL_MIGRATION and does not require CAR_GLOBAL and car_get/set_x. Change-Id: I4e2c1c5766e3bcdd4763b42fb925074f7ccd7002 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32998 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29intel/quark/storage_test.h: Drop external variable declarationArthur Heymans
These are only used where they are initially declared. Change-Id: I0a81a945b771b6c29a170c479b9e72c98e8f3c5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-29soc/intel/braswell: Don't use CAR_GLOBALArthur Heymans
Now that this soc supports NO_CAR_GLOBAL_MIGRATION CAR_GLOBAL and car_get/set_x are not needed anymore. Change-Id: Ia7fa97135a4b376ac0bd8b30093a77614cc2cf55 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29Clean up unused arch/early_variables.h headerArthur Heymans
Change-Id: Ib863e23863ba6d7504b6c4d32de2f1fea4e57fec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29soc/intel/apollolake: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I0f393385aa94f18c2e05af3b5a54999575323d18 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-29intel/sandybridge: Make timC training more robust.Tobias Diedrich
When using native raminit with https://review.coreboot.org/#/c/22683/ I've found that timC training usually fails unless the ram is overspecced (i.e. DDR3L-1600 rated for 1.35V works most of the time with native raminit as DDR3-1333 @1.5V). Looking at the training data I've found that during timC training it is reading register values in the 0-4000 range and checking for runs of 0, but with the failing training the values don't go all the way down to 0. The solution for me has been to do a thresholing pre-pass, after which both the DDR3-1333 @1.5V and the DDR3L-1600 @1.35V work fine for me. Tested: - Intel NUC DCP847SKE - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V), boots fine with native raminit @1.5V - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V), boots fine with native raminit @1.35V - Casual use with these settings - Tested on Lenovo T520 with Crucial HyperX DDR3-1833. - Memtest86+ stable. Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/22776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-29mb/gigabyte/ga-b75m-d3{h,v}: Switch to variant setupAlex James
The Gigabyte GA-B75M-D3H/D3V mainboard trees share a lot of duplicate code, and can serve as a base for porting other Gigabyte 7 series motherboards. Switch the Gigabyte GA-B75M-D3H/D3V mainboard trees to a variant setup, defining ga-b75m-d3v as a variant of ga-b75m-d3h. Signed-off-by: Alex James <theracermaster@gmail.com> Change-Id: Ia175207a2568aefe1aa9bd8d4d990de6a26f1657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-29Documentation: Warn about ME cleaner on Sandy BridgePatrick Rudolph
Document known issues with 'disabled' ME. Change-Id: I364f3ed49341523c781eb2f3b41e866f33632a7e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32889 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29mb/google/sarien: Send post code to the ECEric Lai
Use the mainboard post code hook to inform the wilco EC driver of the every stage. BUG=b:124401932,b:133466714,b:133600566 BRANCH=sarien TEST=Remove DIMM module, confirm diagnostic LED pattern for memory failure (2 amber, 4 white). Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de Reviewed-on: https://review.coreboot.org/c/coreboot/+/33047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29arch/x86: Do not add properties to null DP packagesJacob Garber
It doesn't make sense to add a property to a non-existent Device Property package. However, some of these functions will proceed anyway and allocate a new Device Property package, add the property to that, and then immediately leak the new package. This changes all the acpi_dp_add_* functions to ignore a null package. Change-Id: I664dcdbaa6b1b8a3aeb9a0126d622e2ffb736efd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 135745{6,7}, 138029{2-6} Reviewed-on: https://review.coreboot.org/c/coreboot/+/32971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29mb/google/poppy/variants/nami: Disable FPMCU for non-fingerprint variantsIvy Jian
Even fingerprint device probe failed on non-fingerpint boards,the CRFP driver still register the device that cause the GPE#1 as wake source every time. Override devicetree for non-fingerpirnt variants to avoid unexpected wake event(GPE#1). BUG=b:129650040 BRANCH=firmware-nami-10775.108.B TEST=Boots to OS and check no GPE#1 wake event from eventlog when S0ix exit. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I6fa96e04a34e296889414b96a8c604fc61b8a236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33017 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29nb/intel/nehalem: Call smm_region_start() functionArthur Heymans
This also removes the unnecessary mask. TEST: X201 Boots again. Change-Id: Ia637bd01cd7dc1aecd1a87a739d5243c70419553 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-29drivers/intel/fsp2_0: Fix typo mistakeSubrata Banik
Change-Id: I90f595d7d789429c8717261c6edb6c756f6c0e1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-05-28util/xcompile/xcompile: apply -march to clang as well as gccAlan Green
For x64 and x86_32 configurations, apply the -march flag to both GCC and Clang flags. This solves the problem of Clang-compiled coreboot failing due to Clang emitting SSE instructions for code that is executed while SSE is not enabled. This patch takes functionality targeted for GCC configurations and moves it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order that it applies to both GCC and Clang. This is an alternate patch to CB:32887. Signed-off-by: Alan Green <avg@google.com> Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-28soc/intel/cannonlake: Dump ME status info before notify EndOfFirmwareBora Guvendik
Dumping ME status displays wrong information if we disable Heci1 because it is called after fsp notifies EndOfFirmware and disables Heci1. This patch moves the ME status dump before fsp notify EndOfFirmware. TEST=Boot to OS, check ME dump information Change-Id: Ifd8b18a41c502c4ecfb84698a7669028394589fd Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-05-28mb/google/sarien: Modify SSD power sequenceEric Lai
Due to we turn off SSD power in S5. CB:32952 Based on M2 spec we have to turn on SSD power before RST assert. BUG=b:133389422 TEST=verify warm boot and cold boot are boot successfully. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5b78bab4be675bbb8795361bcfa5af52cb54bb1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/33029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-28mb/google/sarien: Fix SSD power leakage in S5Eric Lai
Turn off SSD power in S5. BUG=b:133389422 TEST=measure H13 is low in S5 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-28src/arch/x86: Add automatic type41 entry creationChristian Walter
SMBIOS Type41 Entries will be automatically created. Type 41 entries define attributes of the onboard devices. Change-Id: Idcb3532a5c05666d6613af4f303df85f4f1f6e97 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32910 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-28src/cpu/x86/lapic/lapic.c: Add missing newlineChristian Walter
Added missing new line to Info Output. Change-Id: Ic4cd63f231de918fad7cd34724651bf8eb1c8e62 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-28src/include/device/pci_ids.h: Add Kabylake C236 DeviceChristian Walter
Change-Id: Ib11981543575311a32896df385d44cf30aa9387f Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32964 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-28mb/google/sarien: Modify arcada touchscreen reset delayCasper Chang
Modify reset delay to 20ms of touchscreen to address i2c hid driver rebind failed issue after auto update of touchscreen firmware BUG=b:132211627 TEST=Touchscreen works after auto update and no re-bind driver failed issue Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: If17afbd160a2c97beb69d0cb50e4a7dc654775f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Crews <ncrews@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-27sb/intel/common/smi.c: Remove unused functionsArthur Heymans
Since all targets using sb/intel/common and cpu/intel/smm/gen1 are now using PARALLEL_MP, some code is not used anymore. Change-Id: Ibdc2bb0f1412366b945813efbc1b6451d27f376f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30019 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-27cpu/intel/model_2065x: Put stage cache in TSEGArthur Heymans
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-27cpu/intel/model_2065x: Use parallel MP initArthur Heymans
TESTED on Thinkpad X201 with a i7 CPU M620 CPU (hyperthread dual core). Boots ~28ms faster. Change-Id: I56b352f9d76ee58f5c82cd431a4e0fa206f848a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-27sb/intel/ibexpeak: Use common Intel SMM codeArthur Heymans
TODO in followup patch: Some not mainboard specific things should be moved out of mainboard_smi_apmc. Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-27src/drivers/intel/fsp1_0: Move PLATFORM_USES_FSP1_0Arthur Heymans
drivers/intel/fsp1_0/Kconfig is a better location than cpu/x86/Kconfig. Change-Id: Ic1c86c26a66c33760484bb6a86e9763c148a7c96 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-27drivers/intel/fsp1.1: Remove unused functionArthur Heymans
This function is unused since POSTCAR_STAGE is used. (be291e8 soc/intel/fsp1.1: Implement postcar stage) Change-Id: Ia9ff5236295a0e1c4f7634d27cf0ae1d87029678 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-27drivers/intel/fsp1.1: Remove stale comment on bootflowArthur Heymans
This list is incorrect and not up to date. The FSP1.1 romstage bootflow is unnecessarily clumsy and instead of trying to update this comment effort is better spend making the bootflow more streamlined. Change-Id: If1e4c462acd0748f072f33e6397a7b43f3bfc834 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-27libpayload: Reset PS/2 keyboardPaul Menzel
Loading a libpayload based payload like coreinfo or FILO from SeaBIOS or GRUB pressing keys does not give the expected results. For example, pressing F1 gives the character 24 translated to scan code 6a. ESC for example 43 (111) in coreinfo loaded from SeaBIOS on QEMU Q35. The problem is not reproducible using the payload directly, that means without SeaBIOS or GRUB. The problem seems to be, that those have already initialized the PS/2 controller and AT keyboard. Comparing it with coreboot’s PS/2 keyboard code, the keyboard needs to be reset. That seems to fix the issue, when the keyboard was initialized before. TEST=Build coreboot for QEMU Q35 with SeaBIOS, and coreinfo as secondary payload. Run qemu-system-i386 -M q35 -L /dev/shm -bios build/coreboot.rom -serial stdio press 3 to select the coreinfo payload, and verify that the keys F1 and F2 are working. Same with coreinfo loaded from GRUB on the ASRock E350M1. Change-Id: I2732292ac316d4bc0029ecb5c95fa7d1e7d68947 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-25nb/intel/pineview: Use MTRR as a proxy for proper resetArthur Heymans
On reset this platform can sometimes hang. This also fixes pineview mainboards not building due to the symbol 'check_mtrr' lacking. Change-Id: I61fe77113004ea664522bda549240a33e3742a98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-25superio/fintek/f71863fg: Remove variable set but not usedElyes HAOUAS
Change-Id: I993055d237b2bd607822485d34d5508c74a7744c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-25nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
This adds a file i82801gx/bootblock_gcc.c since other targets that don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled bootblock.c. Tested on Foxconn D41S. Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-25Documentation: Add HP EliteBook 8760wIru Cai
Also add the HP EliteBook document from wiki. Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30950 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-25mb/lenovo: Unify thermal threshold handlingPeter Lemenkov
Unify thermal handling across Lenovo boards (except g505, which is different). Namely, do the following: * Move thermal levels from acpi_tables to thermal.h (and create if necessary). * Don't use board-specific ifdef guards. * Set thermal levels using dedicated acpi_update_thermal_table function as almost all Lenovo boards do. * Update list of authors in comments. Merge all author's entries. * Minor whitespace and formatting. This makes diff -ruw between the Lenovo boards smaller. Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29659 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-25AGESA binaryPI: Add AGESA entry timestampsKyösti Mälkki
The call to timestamp_rescale_table() had to be moved before TS_AGESA_INIT_{POST/RESUME}_DONE to have that timestamp appear without rescaling. Change-Id: I71e09d3bc4c8657979d447b90fb6ac7cae959479 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-25AGESA binaryPI: Redo entrypoints namelistKyösti Mälkki
Stop assuming the list is complete with no gaps, and use a lookup-table to match AGESA_STRUCT_NAME types of the entrypoints we use with names. Change-Id: Ibef4690d8aa76ff5b47c879f5ceb9d8fc4c4c4cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-25AGESA: Move debug helper to eventlog fileKyösti Mälkki
Change-Id: I2d74f934936e250886526b9c8482f500628a1158 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31513 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-25AGESA f12 f14 vendorcode: Clean up extra CFLAGSKyösti Mälkki
Extra variable is no longer required here. Change-Id: I2a6839ee0349e3019de3b2a91f9e7bb1c435603d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-05-25AGESA: Move heap_status_name() implementationKyösti Mälkki
Place it within class libagesa to avoid including AGESA internal header heapManager.h in coreboot proper build CPPFLAGS. Change-Id: Iae86d6631d7a6ba6ea2588a53b292b435dfd7861 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-24ec/google/wilco: Fix radio control commandDuncan Laurie
This command is working as written, but it is not actually correct as to what the format of the command should be. Fix this and add define the other radios. There is no change in the command send to the EC. Change-Id: Ia551b08561b673d27bec2f900d97b746699b30c4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-05-24nb/amd/amdmct/mct/mctdqs_d.c: Remove variable set but not usedElyes HAOUAS
Change-Id: I45f32ea1ebf59a20d475dfad2d9d0980dec6918b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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