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2018-12-24mb/asus/p5qpl-am: Add mainboardArthur Heymans
This mainboard has the BSEL straps hooked up to the SuperIO similar to the ASUS P5GC-MX and might therefore require a restart. Tested: - FSB 800, 1067 and 1333MHz CPUs - USB - Ethernet - Serial - 2 DIMM slots - SATA - Libgfxinit (VGA) TESTED with SeaBIOS (sercon disabled) and Linux 4.19. Change-Id: Id845289081751ff8900e366592745f16d96f07c0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-12-24driver/spi/eon.c: Add EN25F80Arthur Heymans
TESTED on ASUS P5QPL-AM (writes MRC_CACHE) Change-Id: I5aebe4703a033a0f0226f405d8933b12f3af136f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30249 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-24arch/x86/wakeup.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I5ada2cd4c27eb34b453210fb86848f20569b8e83 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-24arch/arm/memmove.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I614dd37ba9b0899b37bf60a23a64de2683f509f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-24x86/smm/smmhandler.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I7a10ddf79cf457b5dde21714b13890fc9510e7ce Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-24car/non-evict/exit_car.S: Use tabs instead of white spacesElyes HAOUAS
Change-Id: I53e33c54fe3ff7b6276a5bbf7defd2db33a60f0f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-24Documentation/nb/intel: Add Haswell documentationTristan Corrick
At the moment, this just gives some details on the MRC. Change-Id: I84e8ca2543b2e19b84a24f7d7032a4aedb6e9272 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-24drivers/aspeed/ast: Select `MAINBOARD_HAS_NATIVE_VGA_INIT`Tristan Corrick
Any board that uses the AST driver will have support for native graphics init. So, select the option in the driver instead of every board. Change-Id: I2bf42c168d1ffdda11857854889b74953abd7e40 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-24sb/amd/cimx/sb800/ramtop: Fix coding style issuesPaul Menzel
Let GNU indent 2.2.11 fix the coding style issue with `indent -linux …`. Change-Id: Ia2d48906bbeb5ec2f3bea6a93fd2a06aa76b29d9 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/c/19458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-12-24soc/intel/fsp_broadwell_de/acpi: Fix wrong table checksumPatrick Rudolph
Fix the following warning shown in dmesg: "ACPI BIOS Warning (bug): Incorrect checksum in table [FACP]" The table checksum was wrong as it was calculated twice and with the second time the checksum field wasn't set to zero. Change-Id: I375354bf3e95ebdac3b0dad43659d72c6ab3175a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-24Revert "mb/google/octopus/variants/fleex: Update Charger throttling settings"Sumeet Pawnikar
This reverts commit 969ed357f823659a6861a2ca38f3ad9d7b58f949 Reason for revert: According to partner issue b:112448519 comment#80, it impacts skin temperature specifications. Change-Id: I7603c3816f34adebc1f67eff6fad214557544022 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-12-24util/cbfstool/cbfstool.c: Fix typoFrans Hendriks
Fix typo of 'top-aligned' BUG=N/A TEST=Intel CherryHill CRB Change-Id: I6dc2f150d8ec245070257384b406a570498400b2 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/30337 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-23mb/google/hatch: Enable IGD (Integrated GFX Device)Maulik V Vaghela
This patch ensures following 2 features 1. Enable IGD controller in devicetree.cb 2. Pass required FSP UPD to perform internal graphics initialization Change-Id: I607199590d793a70e1e20bb3241fc34467aa829d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-23mb/google/hatch: Add memory init setup for hatchAamir Bohra
This implementation adds below support: 1. Add support to read memory strap. 2. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config 3. Include SPD configuration BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc -bmplk" emerge-hatch coreboot Change-Id: I9bda08bd0b9f91ebb96b39291e15473492a6bf19 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30248 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22mb/google/hatch: Enable Elan TrackpadShelley Chen
BUG=b:120914069 BRANCH=None TEST=USE="-intel_mrc" emerge-hatch coreboot Change-Id: I91db5745d1db16ab4b2fbb7f8c415bd7c1eb29e9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/30227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-12-22mb/google/hatch: Fixes to initial hatch mainboard checkinShelley Chen
Incorporating some feedback to initial hatch mainboard checking (CL:30169) that came in after the CL merged. Updated the chromeos.fmd with the following, * SI_ALL = 3MB * SI_BIOS = 16MB BUG=b:20914069 BRANCH=None TEST=./util/abuild/abuild -p none -t google/hatch -x -a -v Change-Id: I4e311c68873f10f71314e44d3a714639a06dbee8 Signed-off-by: Shelley Chen <shchen@google.com> Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/30296 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22cbmem: Always use EARLY_CBMEM_INITKyösti Mälkki
Wipe out all remains of EARLY/LATE_CBMEM_INIT. Change-Id: Ice75ec0434bef60fa9493037f48833e38044d6e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-22arch/x86 cbmem: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Remove all cases in code where we tested for EARLY_CBMEM_INIT or LATE_CBMEM_INIT being set. This also removes all references to LATE_CBMEM_INIT in comments. Change-Id: I4e47fb5c8a947d268f4840cfb9c0d3596fb9ab39 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/26827 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22soc/intel/fsp_broadwell_de: Select RELOCATABLE_RAMSTAGEArthur Heymans
Tested on wedge100s. Change-Id: I0dcbce230c151cecbbbeec581964cd5f44fbe046 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29911 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-22emulation/qemu-{i440fx,q35}: Don't migrate globalsArthur Heymans
Migration of globals is not needed as there is no real CAR that gets torn down. Change-Id: Id24642b49fab811e59291747eda8632cd49d83d0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-22Revert "mb/google/octopus: Add custom SAR values for Bobba"Justin TerAvest
This reverts commit a914152fa6072c443ccd18de22412b47a228e754. Reason for revert: According to the partner on this project, custom values like this are no longer necessary. Change-Id: I393eb4997f58abe0f77161999474994f06741519 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/c/30347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-12-21mb/google/sarien: Disable pcie interface for wwanLijian Zhao
WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the usgae of Sarien choose to only use USB interface but not over pci express, so totally disable pci express root port 12. BUG=b:1246720 TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10 cyles can still device can be listed under lsusb. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d Reviewed-on: https://review.coreboot.org/c/30350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2018-12-21mb/intel/coffeelake_rvp: Update default configurationWonkyu Kim
Report correct board information for Whiskeylake RVP to OS. Use short board name like other RVP as it's used for firmware version check in auto test. Change-Id: I3f7c95f136e39b978a335cc7855cac819043db7c Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-on: https://review.coreboot.org/c/30318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-21mb/google/poppy/variants/atlas: Remove duplicate entry of dptf_enableSumeet Pawnikar
Remove duplicate entry of dptf_enable. BRANCH=None BUG=None TEST=None Change-Id: I3ddd6a702180624d31c5c58c71acdce8f627c925 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21car/non-evict/cache_as_ram.S: Use tabs instead of spacesArthur Heymans
Change-Id: Icc5fc9ca4aadf02bd9e63b4abc02131b6c2a79da Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A512M16TB-062EJ SPDFrank Wu
Add SPD file for micron_dimm_MT40A512M16TB-062EJ (ram id: 12) BUG=b:121217853 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I45e6a7a183556fb085f5442cd6bb429d79ef4235 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A256M16LY-075F SPDIvy Jian
Add SPD file for sdp micron_dimm_MT40A256M16LY-075F (ram id: 11) BUG=b:120884302 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Icf731bfefd550e9b94b6404bc870d4d76451deb1 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21chromeos: Provide watchdog support in verstageYou-Cheng Syu
Some boards may want to initialize watchdog in verstage instead of bootblock or ramstage, so we need to add watchdog support in verstage. BRANCH=none BUG=b:120588396 TEST=build successfully Change-Id: I13ab84f54d576a0e8c723070b5d9aadd9d63f87c Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/30329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-12-21mediatek/mt8183: Reduce compiled code size of SPI related code.You-Cheng Syu
Refactor function mtk_spi_set_gpio_pinmux to reduce compiled code size. This change can save us about 552 bytes (before compression). Idea from Julius's comment in https://review.coreboot.org/c/coreboot/+/27498/4 BRANCH=none BUG=b:120588396 TEST=manually boot into kernel Change-Id: I93bc88c535b6a2ff94e85f247cf2d51f60b9b29c Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/30328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-12-213rdparty/libgfxinit: Update submodule pointerArthur Heymans
Updates to current master. This includes: - A fix for textmode scaling on G45 - Refactor things to rely less on inline proving - Increased width of modeline fields to 32 bits Change-Id: Iab2915b747f6e4fa4e78eb28fea29bb3a9b3b687 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/30311 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21cpu/amd/geode_lx: Drop supportArthur Heymans
These chips are still using LATE_CBMEM which was agreed upon to be removed after release 4.7. It is now more than 1 year later and they still linger around. The work and review to bring this code up to date can happen on the 4.9 branch and then squashed together and merged back into mainline when done. Change-Id: I11290a5e92397b9b7e7e5a19b029278e728671a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-21mb/pcengines/alixxx: Drop boardsArthur Heymans
These boards are still using LATE_CBMEM which was agreed upon to be removed after release 4.7. It is now more than 1 year later and they still linger around. The work and review to bring those boards up to date can happen on the 4.9 branch and then squashed and merged back into mainline when done. Change-Id: Iede79ef50681f769a47ce3d66b335dae92aef56b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-21util/release: Don't assume the source is in a directory called corebootPatrick Georgi
Change-Id: I384ff2f01b38916851522411d0c25c49793fe480 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-12-21util/release: Use "gpg", not "gpg2" for creating signaturesPatrick Georgi
It's the common name. Change-Id: Iafa793b961847b2c98282fd035ea96ddf6109012 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21util/release/genrelnotes: Don't assume we're on origin/masterPatrick Georgi
A release may be done from an older commit. It's also not a problem as commits are stored in the reflog (unlike local changes that the script guards properly). Change-Id: I26f1c16c1cdfc9e77e28528b3327ce30c5b82b19 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21util/release: Test for rename(1) in genrelnotesPatrick Georgi
It's a separate package on debian, so it may not be installed with perl. Change-Id: Id82661e1d7e6a025f5b207e3bd61669abc32d328 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21util/release: Also keep 3rdparty/fsp in the blobs tarballPatrick Georgi
Change-Id: I089519f685377ae02155817bb042f83d79d1af6c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/30339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-12-21mb/google/hatch: Enable H1 TPM support over SPI interfaceAamir Bohra
Add code support to enable H1 TPM interfaced to SOC on GSPI0. The TPM interrupt is mapped to GPP_C21. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: Ib63a0b473f632d91745102ebd01993e8d65b9552 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30210 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21mb/google/hatch: Clean up gpio definitions in hatch variantAamir Bohra
This implementation cleans up gpio configuration functions and limit definition to baseboard only for now, until variant specfic overides are needed. BUG=b:120914069 TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot Change-Id: I563f6b97812b32d6e3d99e3df512dc112da78aea Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30291 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-20soc/intel/broadwell: implement RMRR ACPI tableMatt DeVillier
Modeled after Skylake implementation; uses duplicated intel common SA functions to get RMRR addresses Test: build/boot purism/librem13v1, observe IOMMU fully functional with intel_iommu=on kernel parameter Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-12-20cpu/intel/common: decouple IA32_FEATURE_CONTROL lock from set_vmx()Matt DeVillier
Newer CPUs/SoCs need to configure other features via the IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the msr is already locked. Create separate functions for setting the vmx flag and lock bit, and rename existing function to indicate that the lock bit will be set in addition to vmx flag (per Kconfig). This will allow Skylake/Kabylake (and others?) to use the common VMX code without breaking SGX, while ensuring no change in functionality to existing platforms which current set both together. Test: build/boot each affected platform, ensure no change in functionality Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/30229 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-20soc/amd/stoneyridge: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6d6dce29591f134f64983387c3b268019d52a602 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-20soc/intel: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ic29891d78514db3b7eed48414a14e4ff579436c0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30004 Reviewed-by: David Guckian Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-20Revert "mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD"Jenny TC
This reverts commit 999b916015ea0558e3821bdb51501b43a60b5ed6. The DMIC doesn't have an ACPI id. The patch which enables ACPI device with id DMIC may create conflict in the feature. Also the ACPI id "DMIC" doesn't comply with ACPI naming conventions. The issue for which the patch was introduced, is already addressed in kernel DMIC driver and the patches are upstreamed in to the Linux kernel. Change-Id: I42cb076700dcb5906599471bebfcd5b265b17644 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/c/30151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-12-20mb/intel/kblrvp: Change HDA verb table selection logicPraveen hodagatta pranesh
All the kaby lake variants uses HDA verb table except RVP8, hence unselect SOC_INTEL_COMMON_BLOCK_HDA_VERB for RVP8 and enable for other variants by default. BUG=None TEST= Tested on KBL RVP11 and verified the audio functionality. Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Change-Id: I64d18ab62cfc08b5560dbcf1b77e975eb68c8d30 Reviewed-on: https://review.coreboot.org/c/30267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
2018-12-20util/xcompile/xcompile: Enable x86_64 supportPatrick Rudolph
Similar to i686 on x86_32, compile for nocona on x86_64. Nocona is the first Pentium 4 CPU that has long mode support. Required for 64bit support. Change-Id: Ied28f98f89610a748be8d66cf35814e9112a4407 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/29877 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-20Documentation/mb/intel/kblrvp11: Fix table formattingJonathan Neuschäfer
Without this patch, Sphinx 1.7.9 prints the following warning, and doesn't emit the table as HTML: /.../Documentation/mainboard/intel/kblrvp11.md:1: WARNING: Malformed table. +------------------+---------------------------------------------------+ | CPU | Kaby lake H (i7-7820EQ) | +------------------+---------------------------------------------------+ | PCH | Skylake PCH-H (called SPT-H) | +------------------+---------------------------------------------------+ | Coprocessor | Intel ME | +------------------+---------------------------------------------------+ Change-Id: I17920398126d57eb8815c45e4a0d4b100f46004a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-19zoombini: remove support for deprecated zoombini boardBob Moragues
Change-Id: Iab2737940f07afb4f5a29ff50e6cb2a22027c51b Signed-off-by: Bob Moragues <moragues@chromium.org> Reviewed-on: https://review.coreboot.org/c/30094 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-19util/crossgcc/buildgcc: Remove quotation marks around hashesJonathan Neuschäfer
They were not originally printed, and serve no good purpose, so let's remove them again. Change-Id: I4e00477f2e143f93fd27ba6a083977a667a3eb48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/28829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-19amd/stoneyridge: Clear SMI_EVENT_STATUS when entering S3/S5Edward Hill
disable_all_smi_status() was not clearing SMI_EVENT_STATUS. This caused us to complain in the eventlog (ELOG_SLEEP_PENDING_GPE0_WAKE) and then wake early from sleep when waiting for a cr50 reset to turn on a cr50 update. BUG=b:121203745 TEST=Careena remains in S5 until cr50 reset after cr50 update, and ELOG_SLEEP_PENDING_GPE0_WAKE is no longer seen in eventlog. Change-Id: I2eec014109249d5c3574c4dbdec5569e2a0bfc8e Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/30304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 11:02:21 +0000