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2014-11-12tegra124: Port a PWM clocking change to big.Gabe Black
The generic tegra124 code will use one of the PWMs to drive the backlight of the display, but the PWM clock was enabled only for nyan. This change enables it for big as well. BUG=none TEST=Built for Big BRANCH=None Original-Change-Id: I5171da7c41f4b4db931563ada3e8e4ebf74ec3d9 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/186767 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 687f3771fb3e6b340a818fa7594b3ac0630fdeaf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ifd14a22a98e7fe273ec28c460b928b8a83c84b66 Reviewed-on: http://review.coreboot.org/7404 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Add pwm_controller registersAndrew Chew
Add some defines and structs that describe what the PWM registers look like. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan Original-Change-Id: Ie10589e4cbf5292e543d205ac8a1c6b09a0f76d0 Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185771 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit fbbd2a5e148c1142aee100dbcde17c865b06b2bd) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: If4dc40c1dcdf1723e05923e2fea42ccc47766699 Reviewed-on: http://review.coreboot.org/7401 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Enable PWM clock, and set up PWM1 pinAndrew Chew
Configure pin H1 for PWM1, and enable the PWM clock. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan Original-Change-Id: I2f91ebd4666bd227686c08cedf3c1aa7abbe8215 Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185770 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 069636d9299f64dd64466d45d2297593b37df4f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic41515842fb883f44f228c77b4cd266e16124d99 Reviewed-on: http://review.coreboot.org/7400 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Fix PWM pinmux functionsAndrew Chew
It seems that someone just stuck the PM3 function for all of the potential PWM pins. Fix this to be more specific to the particular PWM (of which there are four). BUG=none TEST=emerge-nyan chromeos-coreboot-nyan Original-Change-Id: Ic61a7321fbe28953b22007a1d0b522c3ca8714ad Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185739 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit f19f897fe11a582cc240d98de88c5e2d4dc4e364) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie10173413a5f00e06f5b1803fd93d6cb322cee3d Reviewed-on: http://review.coreboot.org/7399 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12tegra124: Add PWM base addressAndrew Chew
The Tegra PWM base address was missing, so add it. BUG=none TEST=emerge-nyan chromeos-coreboot-nyan Original-Change-Id: Iebf687c6644290e05ee72794cde697658ab6d7cb Original-Signed-off-by: Andrew Chew <achew@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185738 Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit b62843f6cfbf870451f658e6df1a3b48256fa4e1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibb8578a130d5995345592caa610c57c1d7f28573 Reviewed-on: http://review.coreboot.org/7398 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12src/lib/Makefile.inc: Allow rmodules to link under ClangEdward O'Callaghan
rmodules were getting linked with libgcc and not libcompiler-rt. Unfortunately this is pretty ugly however we do this else where in the build system so its consistently ugly. The build system will later need a unification pass between compilers once we are tree stable on Clang. Change-Id: I380f7386de2c5adfa9036311323ad9f703b6e712 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7440 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-12src/lib/rmodule.ld: DISCARD (.note|.note.*) sectionsEdward O'Callaghan
We have no need for these sections winding up in the build leading to possible overlaps, such as in the case of Clang builds. Discard sections from inclusion into the resulting binary. Change-Id: Ie807e5809594dcc6e94660a64e359e3b2ca1a0f6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7439 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-12tegra124: nyan: Keep in memory structures below 4GB.Gabe Black
We'd been putting some data structures like the framebuffer and the cbmem at the end of memory, but that may not actually be addressable as identity mapped memory. This change clamps the addresses those structures are placed at so they stay below 4GB. BUG=None TEST=Booted on nyan. Went into recovery mode and verified that there was a recovery screen. Forced memory size to be 4GB and verified that the recovery screen still shows up. BRANCH=None Original-Change-Id: I9e6b28212c113107d4f480b3dd846dd2349b3a91 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185571 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 63ea1274a838dc739d302d7551f1db42034c5bd0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I970c1285270cb648bc67fa114d44c0841eab1615 Reviewed-on: http://review.coreboot.org/7397 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-12nyan: Use asm volatile instead of plain asm so it doesn't get optimized out.Gabe Black
If an asm blob isn't marked as volatile, gcc is free to throw it out if it doesn't think it produces any values that are actually used. To prevent that from happening, add volatile to some asm blobs in the nyan romstage code. BUG=None TEST=Booted on nyan rev1. BRANCH=None Original-Change-Id: I819e068e738e94ea749fcb72bba2eee080e1dfb1 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185610 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 76c09581d6ca4dc6c2f9048f599822939f439d11) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0b32197abf0ddc5f454f9c2415a65d98c60ca48b Reviewed-on: http://review.coreboot.org/7396 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-11blobs: Update to IPQ blob commitMarc Jones
Update the 3rdparty repo to the IPQ binary commit This got updated in error by commit:39bbc8cb97e2de2423cc31bee014ef56884d9f3c Original-Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: http://review.coreboot.org/7354 Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> (cherry picked from commit cfa06c746023fbb79169260012539253811525aa) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibfa243d057f9a2d27e9e02e3e8d4fc6e1da61df0 Reviewed-on: http://review.coreboot.org/7437 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-11AMD Kabini: Update SMU firmware from 0.4 to 0.9Zheng Bao
Version 0.9 contains a fix for a security issue. A more detailed changelog is not available. Change-Id: I1a66c9da900f89ba9b4c13f3457582278d3793e2 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/7293 Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz> Tested-by: build bot (Jenkins)
2014-11-11asus/f2a85-m: Disable SD controllerTobias Diedrich
The hudson handling alluded to in the original comment was implemented in commit ea90963666af1ba49d524c46c9d3257f9438e6c4, use it to disable the SD controller so it doesn't show up in lspci. Change-Id: Ib2ba79a11af06c6765dcad4070232a8a7c6d2751 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/7383 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-11-11mainboard/asus/f2a85-m: Correct APIC routing for Bus 0, Dev 21Tobias Diedrich
The "Bus 0, Dev 21 PCIE Bridge" entry doesn't match the DSDT from my BIOS. It looks like this entry was erroneously copied from the entry for "Bus 0, Dev 20" without rotating the IRQ numbers. The other entries match my ASUS BIOS and the usual rotation pattern. Change-Id: I7401c3daaf0da78ba631791947e5a6bb045fc075 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/7384 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-11-11asus/f2a85-m/devicetree.cb: Correctly align optionTobias Diedrich
Correctly align option (whitespace off-by-one). Change-Id: I606861c5a9f748a17965b75c6d9a8e0f5e4262ce Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/7382 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-11-11drivers/intel/gma/intel_dp.c: Fix printf type-specifierEdward O'Callaghan
'%02hx' is unsigned short, where as the argument is typed as uint8_t and so '%02hhx' is actually correct here. Found-by: Clang Change-Id: I40c48dcecf12845f4708e511236184908e90fb56 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7428 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-11cpu/x86/smm/Makefile.inc: Fix up linkage rulesEdward O'Callaghan
Broken linkage rule for Clang builds on one side of a branch. Hence refactor out common rules from branch. Change-Id: I00e5a2f5f9af1b7882a453caebb378ef74d2d51e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7425 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-11lib/malloc.c: Remove pre-proc guard around includeEdward O'Callaghan
Guards around #includes only hide deeper issues. Change-Id: I0a356360eb3919910a980966213a2c53e99e77eb Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7424 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-11-10arm: Redesign, clarify and clean up cache related codeJulius Werner
This patch changes several cache-related pieces to be cleaner, faster or more correct. The largest point is removing the old arm_invalidate_caches() function and surrounding bootblock code to initialize SCTLR and replace it with an all-assembly function that takes care of cache and SCTLR initialization to bring the system to a known state. It runs without stack and before coreboot makes any write accesses to be as compatible as possible with whatever state the system was left in by preceeding code. This also finally fixes the dreaded icache bug that wasted hundreds of milliseconds during boot. Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183890 (cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97) nyan_big: apply cache-related changes from nyan This applies the same changes from 07a3592 that were applied to nyan. Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c Reviewed-on: https://chromium-review.googlesource.com/184551 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea) Squashed the followup patch for nyan_big into the original patch. Change-Id: Id14aef7846355ea2da496e55da227b635aca409e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> (cherry picked from commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-10AGESA f14: Add "const" modifiersEdward O'Callaghan
Apply commit 283ba78415 to f14 (literally, plus one adaptation). Change-Id: Ieea47470e5852ec8a46596ce23a2d18444618624 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7361 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09abuild: pass compiler configuration options to tool building stepPatrick Georgi
This is required to run abuild parallely with clang without the canonical coreboot toolchain installed. Change-Id: Iea56d3f552d50ab6e762afa134091b0d8e38792c Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7369 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-11-09inteltool: add more hardware IDs and PCIEXBAR/PXPEPBAR read supportFelix Held
Add IDs of some SNB and Haswell chips; use more descriptive names. Add PCIEXBAR and PXPEPBAR read support for SNB/IVB/Haswell. Change-Id: I16753bf90061fc2065b813b1c2169e7b7bcc89e8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/7360 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Mathias Krause <minipli@googlemail.com>
2014-11-09libpayload: serial: Move the depthcharge serial drivers into libpayload.Gabe Black
These drivers need to be ready right away and never really fit into the depthcharge driver model anyway. CQ-DEPEND=CL:194063 BUG=None TEST=Built and booted on nyan and peach_pit. Built for nyan_big, nyan_blaze, and daisy. BRANCH=None Original-Change-Id: I9570dee53c57d42ef4cd956f66a878ce39a2dc20 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/194057 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 26e18f680c93fc990a3d1057c164f19859634a9f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia2233e2bd821d8de8d2d57a9423aeb74be7efd93 Reviewed-on: http://review.coreboot.org/7224 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-09sch: Move to implicit length patchingVladimir Serbinenko
Change-Id: I057e7d30fa3c661e83db09e27278ce9f0bec69d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7330 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09car globals: add "used" attributePatrick Georgi
Otherwise clang feels free to optimize away that variable (somewhat) and revive it in a different form inside .bss. They probably have the language lawyery excuse for why that's perfectly legal, so let's play it safe. (relevant URL, sorry ron: http://llvm.org/bugs/show_bug.cgi?id=9520) Change-Id: I603312ceea7207088dd29453cc8fb8f48c31af21 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/7357 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09i945: consolidate sb & nb early initsVladimir Serbinenko
Change-Id: I00c2c725de5b982a5e4f584b77b09017a5bc0a72 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7062 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-09i945: Consolidate common GNVS initVladimir Serbinenko
Change-Id: Idc3522807b17e56bdaf8f04b4bd68c6ed9777363 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7110 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09Kconfig: Hide DYNAMIC_CBMEM.Vladimir Serbinenko
Only one setting actually works (exact value depends on board). So no need to show it. Change-Id: I2a85719264bbac07791ef6a9279590ba768c309e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7359 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-09lenovo/wacom: Move to implicit length patchingVladimir Serbinenko
Change-Id: Ica8a54ab215d09a2d2de93f316e3831ae4bfe5f5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7331 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09i82801ix: Move to implicit length patchingVladimir Serbinenko
Change-Id: I4027bc8c017901781ae56c7d3bd751bac50719f2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7329 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09i82801gx: Move to implicit length patchingVladimir Serbinenko
Change-Id: Idba0f33d231084d02392e23026f567c30f77b316 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7328 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-09haswell: Move to implicit length patchingVladimir Serbinenko
Change-Id: I662ba2a08f9a176a84b8318c8004aa5db7239567 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7327 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09ibexpeak, bd82x6x: Move to implicit length patchingVladimir Serbinenko
Change-Id: I43eef7f97398d7c4c3f8d9790920fa4402019dd7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7326 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-09Provide ability to integrate with QComm SBLsVadim Bendebury
Ipq8064 SBLs initialize the hardware to prepare it to run an arbitrary user provided bootloader. The only bootloader requirements imposed by the SBLs are that it is concatenated with the SBL chunks in the bootprm AND it uses MBN encapsulation (mostly to specify the size and load address). This patch adds configuration options to specify the location of the SBL blobs and to require MBN encapsulation of the bootblock. BRANCH=none BUG=chrome-os-partner:27784 TEST=manual - the below demonstrates added encapsulation, no code run attempts have been made yet: $ FEATURES=noclean emerge-storm coreboot $ cd /build/storm/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999 $ \od -t x4 build/cbfs/fallback/bootblock.bin | head -3 0000000 00000005 00000003 00000000 2a010000 0000020 00000be0 00000be0 2a010be0 00000000 0000040 2a010be0 00000000 e32bf0df e59f0030 Original-Change-Id: Iae30ad08059e2b35c434ac25a410ac2017752957 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193511 (cherry picked from commit bf16ea915c723ab124d817e3b0d950282e3cf1c1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I53c71d382ec1d826f530d7afb545f64ec4eaf96b Reviewed-on: http://review.coreboot.org/7261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09arm: Thumb ALL the things!Julius Werner
This patch switches every last part of Coreboot on ARM over to Thumb mode: libpayload, the internal libgcc, and assorted assembly files. In combination with the respective depthcharge patch, this will switch to Thumb mode right after the entry point of the bootblock and not switch back to ARM until the final assembly stub that jumps to the kernel. The required changes to make this work include some new headers and Makefile flags to handle assembly files (using the unified syntax and the same helper macros as Linux), modifying our custom-written libgcc code for 64-bit division to support Thumb (removing some stale old files that were never really used for clarity), and flipping the general CFLAGS to Thumb (some more cleanup there as well while I'm at it). BUG=None TEST=Snow and Nyan still boot. Original-Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/182212 Original-Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a) Conflicts: payloads/libpayload/include/arm/arch/asm.h src/arch/arm/Makefile.inc src/arch/arm/armv7/Makefile.inc *** There is an issue with what to do with ramstage-S-ccopts, and *** will need to be covered in additional ARM cleanup patches. Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/6930 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-09build: Add ccopts back into the buildMarc Jones
The ccopts mechanism is needed for passing ARM assembler flags to GCC. There are many gotchas in adding ASFLAGS. As things have moved around, the revert doesn't remove cleanly, so this reverts and cleans up the ccopts. This reverts commit 25b56c3af514faa8a730d56fe14cae4960ac83aa. Change-Id: I44c025535258e6afb05a814123c10c24775a88e8 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7352 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-08acpigen: Add new function acpigen_pop_lenVladimir Serbinenko
acpigen_patch_len doesn't really need its argument: length always includes everything from length bytes to current pointer and never bytes before it. Hence just infer all the info implicitly. Argument is wrong in several places through the codebase but ACPI parsing is lax enough to swallow incorrect SSDT. After this function is used throughout the codebase, these issues will be fixed. Change-Id: I9fa536a614c5595146a7a1cd71f2676d8a8d9c2f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7325 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-08fsp_rangeley: Switch to per-device ACPIVladimir Serbinenko
Change-Id: Ic8b2204a6d08d63ac7f05836bf1424f1ca6ee50e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7046 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2014-11-08ibexpeak: Move to common FADTVladimir Serbinenko
Change-Id: Ibb4dcc4356876f6385e79c10d8296fb680937827 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7201 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-08bd82x6x: Move to common FADT.Vladimir Serbinenko
Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7200 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-08intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'Edward O'Callaghan
Change-Id: I1cf87b3c73d8bf8846e5870b19b089f85c299567 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-08device/dram/ddr3.c: Fix sizeof on array func param overflowEdward O'Callaghan
The sizeof on array function parameter will return size of 'u8 *' instead of 'spd_raw_data' (aka 'u8 [256]' leading to an overflow. Found-by: Clang Change-Id: I78e113a640b2953c853eb43bd6874e4694260b1f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7353 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-11-08blobs: Update to IPQ blob commitMarc Jones
Update the 3rdparty repo to the IPQ binary commit Change-Id: I50fd7254eaf97ac44fb046e39ff1a81d2baad16f Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7354 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-07mainboard: Trivial - Make AGESA board include consistentEdward O'Callaghan
Change-Id: If6cb99469f56fff8f88b294b625f0a5205ec540b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7238 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-07drivers/ioapic: DEVICE_NOOP some stub function callbacksEdward O'Callaghan
Just when you thought you found them all.. Reduces loc and makes NOP's explicit. Change-Id: I416e0468b7f2f462c940daae695d67fb409aa4c6 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7350 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-07drivers/net/ne2k.c: Collect headers and defines to top of fileEdward O'Callaghan
Change-Id: I2ffb0dd9fe400132f6d430f115f962b5f8578efa Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7292 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-07cpu/intel/fsp_model_406dx: Invaild include pathEdward O'Callaghan
Found-by: Clang Change-Id: Iac54755caadc3ffbe8a09d40aed8500c2359e829 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7349 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-06northbridge: DEVICE_NOOP some stub function callbacksEdward O'Callaghan
Reduces loc and makes NOP's explicit. Change-Id: I8a117b150b8b421c7a18b48a2ac36d15679f20b0 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7344 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-06inteltool: Fix message in case of multiple LPC controllersMathias Krause
If we find multiple LPC controllers, we want to tell the user that we'll ignore all but the first. However, we use 'dev' in the message (the current device found) instead of 'sb' (the one we want to use). Fix the message by using 'sb' and break the loop right away in this case. It's sufficient to tell the user once which LPC controller we'll use. Change-Id: Ibd27e40525fabe8c63b112691ad49fd994c70a48 Signed-off-by: Mathias Krause <minipli@googlemail.com> Reviewed-on: http://review.coreboot.org/7342 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-06inteltool: Add support for Sandy Bridge desktop processorsFelix Held
Change-Id: I5e68b89c30d5550e4bce5c3e4c7b0689c38756bc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/7337 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
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