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AgeCommit message (Expand)Author
2016-07-28intel/common: Add ASL code for DPTFShaunak Saha
2016-07-28Documentation: Capitalize RAM, ROM and ACPIElyes HAOUAS
2016-07-28intel/common/opregion.c: only write 16 bytes to 16 byte fieldMartin Roth
2016-07-28arch/riscv: Refactor bootblock.SJonathan Neuschäfer
2016-07-28arch/riscv: Only initialize virtual memory if it's availableJonathan Neuschäfer
2016-07-28arch/riscv: Remove spinlock code from atomic.hJonathan Neuschäfer
2016-07-28intel/fsp1_1: Add C entry support to locate FSP Temp RAM InitSubrata Banik
2016-07-28skylake/devicetree: Add LPC EC decode rangeSubrata Banik
2016-07-28skylake/mainboard: Define mainboard hook in bootblockSubrata Banik
2016-07-28soc/intel/skylake: Add C entry bootblock supportSubrata Banik
2016-07-28soc/intel/skylake: Do cache as ram and prepare for C entrySubrata Banik
2016-07-28util: Correct typo in MSR_EBC_SOFT_POWERONElyes HAOUAS
2016-07-28util/msrtool: update register for Pentium4_laterElyes HAOUAS
2016-07-28msrtool/README: Remove trailing spacesElyes HAOUAS
2016-07-28soc/intel/skylake: Use init_vbnv_cmos from vboot vbnvFurquan Shaikh
2016-07-28soc/intel/broadwell: Use init_vbnv_cmos from vboot vbnvFurquan Shaikh
2016-07-28chromeos/gnvs: Clean up use of vboot handoffFurquan Shaikh
2016-07-28chromeos: Clean up elog handlingFurquan Shaikh
2016-07-28google/urara: Provide dummy implementations of rec/dev functionsFurquan Shaikh
2016-07-28qualcomm/gale: Add required files to enable elog in ramstageFurquan Shaikh
2016-07-28qualcomm/storm: Add required files to enable elog in ramstageFurquan Shaikh
2016-07-28i2c/ww_ring: Add ww_ring files to ramstageFurquan Shaikh
2016-07-28google/chromeos: Use vboot bootmode functions for elog add boot reasonFurquan Shaikh
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
2016-07-28vboot: Separate vboot from chromeosFurquan Shaikh
2016-07-27drivers/intel/fsp2_0: Update MRC cache with dead version in recoveryFurquan Shaikh
2016-07-27soc/intel/common: Store MRC data in next available slot in the cacheFurquan Shaikh
2016-07-27mainboard/google/slippy: remove unobtainable mainboardAaron Durbin
2016-07-27mainboard/google/bolt: remove unobtainable mainboardAaron Durbin
2016-07-27soc/intel/apollolake: Disable monitor mwaitBora Guvendik
2016-07-27Rename VB_SOURCE to VBOOT_SOURCE for increased clarityPaul Kocialkowski
2016-07-27chromeec: Use CHROMEEC_SOURCE with fallback instead of hardcoding pathPaul Kocialkowski
2016-07-27arch/x86: Add bootblock and postcar support for SOC MTRR accessLee Leahy
2016-07-27cpu/x86: Support CPUs without rdmsr/wrmsr instructionsLee Leahy
2016-07-27nb/intel/x4x: Fix CAS latency detection and max memory detectionDamien Zammit
2016-07-27device: include devicetree in bootblock stageAaron Durbin
2016-07-27soc/nvidia/tegra124: remove cache_policiy optionAaron Durbin
2016-07-26drivers/intel/fsp2_0/header_util: Convert UPD headersLee Leahy
2016-07-26google/oak: dsi: set mipi pin driving control onMartin Roth
2016-07-26meditek/mt8173: dsi: set mipi pin driving control onJitao Shi
2016-07-26arch/x86: Generate a map file for the postcar stageLee Leahy
2016-07-26arch/x86: Organize ramstage to match other stagesLee Leahy
2016-07-26arch/x86: Move romstage files into romstage sectionLee Leahy
2016-07-26arch/x86: Move postcar stage commands into placeLee Leahy
2016-07-26drivers/elog: put back 4KiB limitAaron Durbin
2016-07-26intel car: Use MTRR WRPROT type for XIP cacheKyösti Mälkki
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
2016-07-26lib: Don't require ULZMA compression for postcarLee Leahy
2016-07-26drivers/intel/fsp2_0: Enable XIP romstage with loaded FSP-MLee Leahy
2016-07-26src/lib: Enable display of cbmem during romstage and postcarLee Leahy