summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2016-12-06cpu/x86/msr.h: Drop excessive includesKyösti Mälkki
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17735 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06cpu/cpu.h: Drop excessive includesKyösti Mälkki
Change-Id: Ifeef04b68760522ce7f230a51f5df354e6da6607 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17734 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Declare cpu_phys_address_size() for all archKyösti Mälkki
Resource allocator and 64-bit PCI BARs will need it and PCI use is not really restricted to x86. Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17733 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06CPU: Move SMM prototypes under x86Kyösti Mälkki
Change-Id: Iefbc17dcfcf312338d94b2c2945c7fac3b23bff6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17732 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-06PCI ops: Remove pci_mmio_xx() in ramstageKyösti Mälkki
MMCONF operations are already the default so these would never be used. Change-Id: I671f3d2847742e400bc4ecfccc088e3b79d43070 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17691 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Rename pcie_xx() to pci_mmio_xx()Kyösti Mälkki
Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17530 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Define read-modify-write routines globallyKyösti Mälkki
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17690 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17689 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06PCI ops: Remove conflicting duplicate declarationsKyösti Mälkki
The code originates from times before __SIMPLE_DEVICE__ was introduced. To keep behaviour unchanged, use explicit PCI IO operations here. Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17720 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel PCI ops: Remove explicit PCI MMCONF accessKyösti Mälkki
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17529 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06mb/lowrisc/nexys4ddr: Read RAM information from the config stringJonathan Neuschäfer
Change-Id: I9147eca0b536b6267d58f6e8baa37b6950b35160 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17710 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06mb/lowrisc/nexys4ddr: Initialize CBMEM in romstageJonathan Neuschäfer
Change-Id: Ic1706ae8ab3cbef8f445d70cb78fa9d3301d87be Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17707 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06soc/lowrisc: Place CBMEM at top of autodetected RAMJonathan Neuschäfer
Change-Id: I9f169db330d1792128db7a6308ed3afbe5803c03 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17708 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06soc/marvell/mvmap2315: Fix integer arithmeticJonathan Neuschäfer
Replace logical with bitwise AND operator. Change-Id: I712fab61fbbc833fc2b2575948a875e2f07fd5de Reported-by: Coverity (CID 1362808) Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06riscv: Stub out sbi_(un)mask_interruptJonathan Neuschäfer
Linux needs these SBI calls, but so far it seems to work when they don't do anything. Change-Id: I2cd0bb3ab91e89805fed84ec87e4a48ce70c3a46 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17593 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06soc/ucb/riscv: Place CBMEM at top of autodetected RAMJonathan Neuschäfer
Change-Id: Ida016aec11ccdb8da8d2ae1d30ddca16b069be11 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17595 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06arch/riscv/mcall.c: Return the correct memory base and sizeJonathan Neuschäfer
Change-Id: Ibf471787ccb4f5393b0af737a9f7fc47b853a41a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17594 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-06mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missingWerner Zeh
Do not abort the initialization of PTN3460 if HW-ID could not be retrieved and just assume that the HW-ID does not match 7.9.2.0. In this case PTN3460 will be setup to a working condition even if this field is missing. This makes this driver more robust with faulty blocks. Change-Id: I301fb165a7924768e44182d92be820294beb0280 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/17671 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-12-06vendorcode/siemens: Ensure a given info block is available for a fieldWerner Zeh
While searching for a field in all blocks ensure that the checked block is available and can be used. In this way a field can be retrieved from every block and not just the first one. Change-Id: Idbd7656ab0664763cb065f5e817193ad1d9e0871 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/17670 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2016-12-06AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already setKyösti Mälkki
It gets selected from CPU_AMD_MODEL10XXX. Change-Id: Iffab43edc1152b07ba2af6273d4b5eb94afe33ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17692 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel/fsp_sandybridge: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Untested. Change-Id: I61ab1e5279c995f933971332673aa4ca0150e80c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17544 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06intel/fsp_rangeley: Switch to MMCONF_SUPPORT_DEFAULTKyösti Mälkki
Boards with this chipset do not have any reference of MMCONF_BASE_ADDRESS being written to chipset registers. Either board support is already broken or FSP takes care of this early and Kconfig lacks the notice that this parameter must match with the chosen FSP binary. CPU bootblock associated with this chipset uses exclusive PCI IO access already. Untested. Change-Id: I07d20d81266ff6aaa6384d20a806d52fd4568e08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17547 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06spi_flash: Make a deep copy of spi_slave structureFurquan Shaikh
Commit 36b81af (spi: Pass pointer to spi_slave structure in spi_setup_slave) changes the way spi_setup_slave handles the spi_slave structure. Instead of expecting spi controller drivers to maintain spi_slave structure in CAR_GLOBAL/data section, caller is expected to manage the spi_slave structure. This requires that spi_flash drivers maintain spi_slave structure and flash probe function needs to make a copy of the passed in spi_slave structure. This change fixes the regression on Lenovo X230 and other mainboards. Change-Id: I0ad971eecaf3bfe301e9f95badc043193cc27cab Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17728 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Iru Cai <mytbk920423@gmail.com>
2016-12-05mainboard & southbridge: Clear files that are just headersMartin Roth
These headers & comments indicating a lack of functionality don't help anything. We discourage copyrights and licenses on empty files, so just clear these. Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17657 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-05Add/Combine Haswell Chromebooks using variant board schemeMatt DeVillier
Combine existing boards google/falco and google/peppy with new ChromeOS devices leon and wolf, using their common reference board (slippy) as a base. Chromium sources used: firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...] firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode] firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...] Additionally, some minor cleanup/changes were made: - I2C devices set to use ACPI (vs PCI) mode - I2C device ACPI entries adjusted as per above - I2C devices set to use level (vs edge) interrupt triggering - XHCI finalization enabled in devicetree - HDA verb entries use simplified macro entry format Existing google/falco and google/peppy boards will be removed in a subsequent commit. Variant setup modeled after google/beltino Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17621 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-05Remove boards google/falco and google/peppyMatt DeVillier
No need for these boards to exist separately once included as variants under google/slippy Change-Id: I52a476ceaadf50487d6fe21e796d7844f946d8b3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17622 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-05rockchip/rk3399: display: Update edp initialization retryMartin Roth
Follow on patch to clean up the previous retry code. Previous patches: coreboot commit 079b5c65 (rockchip/rk3399: display: Retry edp initialization if it fails) cros commit 28c57a6e (rockchip/rk3399: display: retry edp initialization if edp initial fail) - Reduce the jumping around via goto statements - Break the retry code out into a separate function that also prints the error messages. BRANCH=gru BUG=chrome-os-partner:60150 TEST=Rebuild Kevin and Gru Change-Id: I3b6cf572073e4dcac83da09621bafde179af2613 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17642 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-12-05nb/intel/sandybridge/raminit: Split raminit.cPatrick Rudolph
Split raminit.c into smaller parts. Move all functions that will be used by chip-specific code into raminit_common.c. The chip-specific changes includes new configuration values for IvyBridge and 100Mhz reference clock support, including new frequencies. No functionality is changed. Tested on Lenovo T420. Change-Id: If7bb5949f4b771430f3dba1b754ad241a7e8426b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/17604 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-05spi: Define and use spi_ctrlr structureFurquan Shaikh
1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17684 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Pass pointer to spi_slave structure in spi_setup_slaveFurquan Shaikh
For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17683 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-05spi: Fix parameter types for spi functionsFurquan Shaikh
1. Use size_t instead of unsigned int for bytes_out and bytes_in. 2. Use const attribute for spi_slave structure passed into xfer, claim bus and release bus functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ie70b3520b51c42d750f907892545510c6058f85a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17682 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-04spi_flash: Move spi flash opcodes to spi_flash.hFurquan Shaikh
BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I3b6656923bb312de470da43a23f66f350e1cebc7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17680 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-04cbfstool: Fix off-by-one error in checking hash_typeFurquan Shaikh
Change-Id: Iaf208705d0cd450288af721d53053b2d3407a336 Found-by: Coverity Scan #1325836 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17698 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-03mainboard/intel/kblrvp: Enabling Kaby Lake RVP7Barnali Sarkar
Add support for Kaby Lake RVP7 board * Add RVP7 board support in Kconfig * Override default descriptor and ME binary paths in Kconfig since those binaries will differ for RVP3 and RVP7 * Add RVP7 board name in board_info.txt and Kconfig.name * Add devicetree.cb for RVP7 in the variants path * Add gpio.h for RVP7 in variants/include/variant path * Made board specific code for retrieving spd, i.e., in RVP7 there is non-soldered DIMMs, so SPD is read through smbus, unlike RVP3 where memory DIMMs are soldered down with board. Hence for RVP3, the spd binaries will be fixed and can be kept as binary file in cbfs. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP7 Change-Id: I6f3d17d857bad1b5cf39f0bc900c760fee72da48 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17637 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-03nb/i945/raminit.h: Fix fsb_frequency's commentElyes HAOUAS
Change-Id: Ie1c28b73bd2d34070173838d341cc6b8f65f50ef Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/17686 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-03nb/x4x: Fix sticky scratchpad register offsetArthur Heymans
Change-Id: I9b952e32dc661f5c1fa96b037b415693d8777b04 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17685 Tested-by: build bot (Jenkins) Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-12-03rockchip/rk3399: Fix typoPatrick Georgi
TRAINING, not TARINING. BUG=none BRANCH=none TEST=still builds Change-Id: I8b7ffd0f0544a58865865a8b09d9c153db9c2674 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1ea846ce1ffd654d7d34c2a1d43b0fddbd4ae32 Original-Change-Id: I4940279ed7217cc20fe29c8b3603d1853acbfc5e Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/411801 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/17677 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-02soc/intel/common: Add suppport for Extended VBTAbhay Kumar
With addition of new features in VBT its size got increased more than 6k and was unable to pass using mailbox 4 hence pass using mailbox 3 to kernel. BRANCH=none BUG=chrome-os-partner:60026 TEST=firmware screen and Chrome OS screen should come up. Change-Id: I359cf9bc402881161c9623cada689496716e04a5 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/17585 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02google/pyro: set i2c bus timings by rise/fall timesKevin Chiu
Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot Change-Id: I68be9b96dc731eb0084ee5e15921866818637e73 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02mainboard/google/reef: Add all DMIC endpointsSathyanarayana Nujella
Independent of Board DMIC configuration, add all DMIC points i.e. add DMIC-1ch, DMIC-2ch, DMIC-4ch endpoints. This allows flexibility to userspace to open capture devices as needed. This is a temporary fix; once upper layers support choosing particular channels from 4-ch PCM stream, we will limit exposing only DMIC-4ch endpoint. BUG=chrome-os-partner:60444 BRANCH=none TEST=Verify All DMIC blobs are included Change-Id: I9729a3570c0668f3da4e7986291ebad6fe1de47a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17660 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02soc/intel/apollolake: Drop privilege level to IA_UNTRUSTEDAndrey Petrov
As per guidelines CPU security level should be dropped before OS start, so that certain MSRs are locked out. Drop privilege levels on all logical CPUs. BUG=chrome-os-partner:60454 TEST=iotools rdmsr x 0x120, make sure bit 6 is set, rdmsr x 0x121 results in io error. Change-Id: I67540f6da16f58b822db9160d00b7a5e235188db Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17665 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-12-02soc/intel/apollolake: Enable ACPI PM timer emulation on all CPUsAndrey Petrov
Currently we enable ACPI PM timer emulation only on BSP. So the timer doesn't work on other cores and that breaks OSes that use it. Also, microcode uses this information to figure out ACPI IO base, and that is used for other features. This patch enables ACPI timer emulation on all the logical CPUs. BUG=chrome-os-partner:60011 TEST=iotools rdmsr x 0x121, x={0..3}, make sure it is set Change-Id: I0d6cb8761c1c25d3a2fcf59a49c1eda9e4ccc70c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17663 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-01PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI accessKyösti Mälkki
Some PCI-e capability registers are located starting from 0x100, these are not accessible using the conventional PCI IO config operations at 0xcf8/0xcfc, unless PCI_CFG_EXT_IO was selected. Thus any feature that calls pciexp_find_extended_cap() depends on either MMCONF_SUPPORT_DEFAULT or PCI_CFG_EXT_IO being enabled on the platform. In theory there can be system without MMCONF_SUPPORT, but with complete PCI Express configuration space available using PCI_CFG_EXT_IO. Do not use explicit PCI MMCONF operations here, but rely on the default PCI access method to be able to access all of the configuration space. While at it, convert to IS_ENABLED() everywhere in the source and organize Kconfig file better. Change-Id: Ica6e16d2fb2adc532e644c4b2c47806490235715 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01PCIEXP_ASPM: Unify code with other PCI-e tuningKyösti Mälkki
Error reporting can be enabled together with ASPM, there is no other use for function return value. Change-Id: I58081fac0df5205a5aea65d735d34b375c2af9cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17654 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01mainboard/google/reef: allow variants to modify nhlt oem revisionAaron Durbin
In order to mirror the full flexibility of the NHLT library that allows a caller to set the OEM revision field in the ACPI header modify the variant callback to override the value. Change-Id: I16e539b350a50e3c163be1439c8637b82e53a759 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17651 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-12-01lib/nhlt: add support for setting the oem_revisionAaron Durbin
In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17650 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01arch/x86: cache postcar in stage cacheAaron Durbin
Stash and reload postcar stage in the stage cache for increased S3 resume speed. It's impact is small (2 ms or so), but there's no need to go to the boot media on resume to reload something that was already loaded. This aligns with the same paths we take on ramstage as well. Change-Id: I4313794826120853163c7366e81346858747ed0a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17649 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01lib: put romstage_handoff implementation in own compilation unitAaron Durbin
Instead of putting all the functions inline just put the current implementation into a C file. That way all the implementation innards are not exposed. Lastly, fix up the fallout of compilation units not including the headers they actually use. Change-Id: I01fd25d158c0d5016405b73a4d4df3721c281b04 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17648 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01romstage_handoff: add helper to determine resume statusAaron Durbin
Instead of having callers query the romstage handoff resume status by inspecting the object themselves add romstage_handoff_is_resume() so that the same information can be queried easily. Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17647 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-05 03:05:48 +0000