Age | Commit message (Collapse) | Author |
|
Skylake soc code sets the length of the PCIe configuration space to 64
MB while the specification allows up to 256 MB. Linux reports "acpi
PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bos 00-3f] only
partially covers this bridge".
Remove "select PCIEX_LENGTH_64MB" from Kconfig so the default 256MB will
be used and the size can be reduced on the mainboard level when required.
BUG=N/A
TEST=tested on facebook monolith
Tested is by booting Linux 4.15 and analyzing the coreboot and Linux
dmesg to make sure the memory range is reported correctly and doesn't
create an overlap.
Change-Id: I8a06b9fba5ad561d8595292a73136091ab532faa
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37704
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The _PRS for the LNK* items don't contain irq 11. So this is not
supposed to be used.
Add irq 11 to the list as there is no reason not to allow this.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I634d0ea8506a5e93359c652f74131231f5c13b02
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37690
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The ANX7625 is an ultra-low power 4K Mobile HD Transmitter designed for
portable devices. It converts MIPI DSI/DPI to DisplayPort 1.3 4K.
BRANCH=none
BUG=b:140132295
TEST=emerge-jacuzzi coreboot
Change-Id: I02ef29798b0257632e0750f09a4390b3d0226367
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Renze Nicolai tested it on hardware: boots into Linux without problems.
Change-Id: I17e09c366ae0c9c99d5c65dd1f00672697a7c709
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37737
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Remove baseboard gpio.c and rely on variant override.
Change-Id: I4657b1aa2c81a990b750e163e948b8495d8b97c7
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37512
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add support for automatic extraction of the Second Logical Boot
Partition from the supplied IFWI binary.
Change-Id: Ia2a9ca233bddb8e9fb4e980f0ae5e6fcf3fc757c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37681
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The ApolloLake SoC allows two Logical Boot Partitions. This patch
introduces a '-s' optional parameter to select the second Logical
Boot Partition.
Change-Id: If32ec11fc7291d52b821bf95c1e186690d06ba11
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37660
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The base address of the 16 MB flash range was reported as 0xFFF00000
this causes the range to extend above the 4GB boundary.
Change the base to 0xFF000000 as is the case with e.g. Skylake.
BUG=N/A
TEST=build
Change-Id: Ia8de01769ced00c5ae13f255760401933230b88c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not
enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized),
which indicates the TEVT method is empty.
The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses
this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT.
The TEVT method will be removed from the ASL code when the EC does not support TEVT.
BUG=N/A
TEST=Tested on facebook monolith.
Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
Mainboards exist with a 4+1 MiB flash chip combination.
Change-Id: I214553a2c70e1a4a0e4d972fee5e524b609bb1e0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The AST2500 is similar to the AST2400, but it also supports ESPI mode.
In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable.
Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add VBTs for all rambi variants, extracted from VGA BIOS
from stock firmware images using intelvbttool.
Test: boot several rambi variants using MrChromebox edk2/master
branch with Baytrail GOP driver and extracted VBTs.
Change-Id: I401ae5accd852fc5211092a5944fc85871b642ae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add VBTs for jecht variants, extracted from VGA BIOS
from stock firmware images using intelvbttool, zero-padded
to 0x11ff bytes to make the Intel BMP editor happy.
Use a common VBT for all except tidus, since it differs
from the others.
Change-Id: I570bdb749ef7d49f41539074220bb16c9c100342
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This impacts boards:
hatch (&variants) and drallion.
Some variants like Puff can have up to 12 cores. coreboot should take
the min() where MAX_CPU is the upper bound.
Further to that, boards themseleves shouldn't be setting the MAX_CPUS,
the chipset should be and so do that.
BRANCH=none
BUG=b:146255011
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I284d027886f662ebb8414ea92540916ed19bc797
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
|
|
Switching was done by moving a SIO configuration and
a clocks setup from 'romstage.c' to 'bootblock.c'
TEST=Boots into Ubuntu Linux 16.04.6 without a problem.
Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: Idbc1b37a8c98fe7fa24d8632e6a55c046e2d2869
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
-1 shouldn't be assigned to an unsigned variable, so use an otherwise
unused constant here. Since 7 is the highest virtual LDN number, using
0xffff as PNP_SKIP_FUNCTION marker has no unwanted side effects.
Change-Id: I5e31e7ef9dad5fedfd5552963c298336c533a5e9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Now RCOMP_TARGET_PARAMS is defined and used once in the definition of
the RcompTarget structure. All other structures in these functions use a
fixed value.
Replace RCOMP_TARGET_PARAMS with fixed value.
BUG=N/A
TEST=build
Change-Id: Ibe7c72c65975354433e9a0c613bda715eb782412
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37658
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The FSP-M/S/T headers added are generated as per FSP v1433.
Change-Id: Iacb44204c3f7220a20ab3edc2163c97188014bbf
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37559
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I66d48206a4c1c31802e85c08ab935f81f10aadbc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
Change-Id: Ie7a8af46a59c36b0dd62f227a6b53918c8fde7b8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37742
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I38a721c359ab7761c5a3ea79da0c159fd7f58970
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37711
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To support showing CBMEM logs on recovery screen, add a function
cbmem_console_snapshot() to copy the CBMEM console to an allocated
buffer. Non-printable characters are automatically replaced with '?' to
ensure the returned string is printable.
BRANCH=none
BUG=b:146105976
TEST=emerge-nami libpayload
Change-Id: Ie324055f5fd8276f1d833fc9d04f60a792dbb9f6
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Change-Id: Ica1c9f0c92886a081ab69612174a8d1d467b0713
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Add VBTs for beltino variants, extracted from VGA BIOS
from stock firmware images using intelvbttool, zero-padded
to 0x11ff bytes to make the Intel BMP editor happy. Use
a common VBT for all except monroe, since it differs as
it has a built-in display (being a Chromebase vs Chromebox).
Change-Id: I82afb20a5648695c2cd568384a26839ab28be3da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Update VBT using file extracted from VGA BIOS from stock
firmware image using intelvbttool, zero-padded to 0x11ff
bytes to make the Intel BMP editor happy.
Change-Id: I9f53e80305ec8de78a3d5c930224b394b5c8618a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37732
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add VBTs for all auron variants, extracted from VGA BIOS
from stock firmware images using intelvbttool, zero-padded
to 0x11ff bytes to make the Intel BMP editor happy.
Test: boot several auron variants with libgfxinit and Tianocore
payload, ensure both internal and external displays as well as
HDMI audio function properly under Linux (4.x/5.x).
Change-Id: Ibc4eabfa5d02b4c08755cf52835b5df8c1291fea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
If the compiler fails to inline all the FORCE_INLINE functions, it will
complain.
Change-Id: I7b8349c9a3d53c47ac189f02b296600abac8a0cf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37734
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Commit 77ad581ce [chromeec: PS2K node can't be under SIO node]
moved the PS2K ACPI device from under the SIO device to under
the LPCB, and while this fixed the keyboard under Windows for
Skylake devices, it was insufficient for Baytrail and Braswell
devices (and likely Apollo Lake/Gemini Lake too).
Moving the PS2K device under PCI0 allows the PS2K to be functional
under Windows for all Chrome-EC platforms.
Test: build/boot various Chrome-EC devices from IVB, HSW, BDW,
BYT, SKL, BSW, and KBL platforms, verify keyboard functional
under both Linux (4.x and 5.x) and Windows 10.
Change-Id: If773eea69dc46030b6db9d64c3855be49951d4c0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37542
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We had to role the `fsp` submodule back for a minute due to a regression
with the Coffee Lake binary. Intel silently mixed FSP 2.1 features into
the Coffee Lake FSP which is supposed to be FSP 2.0. With the stack and
heap usage partitioned for FSP using coreboot's stack (config FSP_USES_
CB_STACK), it works again.
To make this even messier: We already selected this Kconfig option for
Whiskey Lake, which is supposed to use the very same FSP binary. So with
either submodule pointer, something was always broken :-/
Change-Id: Id2aa17aaa2c843dcc7e0fb28779d1e5948da83c9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mimoja <coreboot@mimoja.de>
|
|
Also, don't define the default as this results in spurious lines in the
.config.
TEST: Build all boards with where config.h differed with
BUILD_TIMELESS=1 and remained the same
Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ide336fb900360c446bffcc5ca31bf51e7746cae1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Support configuring the qup dfsr registers.
Tested: validated DFSR clock configuration and M/N/D values.
Change-Id: I146ac7c2197606965265f2a770769312af76041e
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Change-Id: I662420e6e05a6489950c583dfd37df5826153214
Signed-off-by: Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: RONAK KANABAR <ronak199323@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
|
|
Make it part of the release process to note not only what config flags /
code properties etc will be deprecated, but to also spell out which
boards would be affected at the time of the release.
Change-Id: I0ef1404e75182ea4bacae31edb0a843e7a359545
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37702
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add an fmd file with a layout that allows configuring the system for
measured boot without enabling verified boot.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37673
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
cbfstool doesn't support % tag yet while this was in the fmd.
Revert the fmd changes that use the % tag.
BUG=N/A
TEST=build
Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
Update signal names and GPIO configuration.
Remove unused GPE_EC_WAKE and EC_XXX_GPI defines.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Iae5edb8418894a669ed49c2d78672d8957010f3c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
|
|
Update PMC shadow register base address for Jasperlake
Correct PCH detection logic based on PCH ids and return correct base
address based on PCH detected since our code supports both tgl and jsl.
Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
|
|
Remove the sarien_cml and arcada_cml subdirectories from the
drallion/variants directory.
BUG=b:140068267
TEST=./build_packages --board=drallion
Confirm that drallion still builds successfully.
BRANCH=none
Change-Id: I9648965ca222d4d68bf73738716ad1c93739b03f
Signed-off-by: Mike Wiitala <mwiitala@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
|
|
As per the 4.11 release requirement, C_ENVIRONMENT_BOOTBLOCK=y
is a mandatory feature, which most AGESA and binaryPI boards lack.
Disable such platforms from the build for the time being.
The Kconfig symbol has been flipped, ROMCC_BOOTBLOCK=n is the
same mandated feature as C_ENVIRONMENT_BOOTBLOCK=y.
If a platform does not reach ROMCC_BOOTBLOCK=n within a
reasonable timeframe both the mainboard and the respective
unused platform support code will get removed.
Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Indent continuation lines of an if test farther than its "true"
expression to be executed.
Change-Id: I3dfa4049761095dcbb6797f1533d6a513e3b503c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37727
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ib27c518fb5ce99e17be25b974ff5adc8c6b3f3a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37570
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ie9918e5114bb880e37680a85eab2bd224b0b082c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
BRANCH=none
BUG=b:146172098
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
This reverts commit 01787608670adec26fcea48173e18395e51c790e.
AMD: Dropping the _HID of PCI root bus doesn't work well and people
started to notice the breakage.
Intel: These platforms have a devicetree switch to choose between PCI
and ACPI modes. In the former case we need _ADR, but in the latter _HID
as the PCI devices are hidden.
The conflicting use of _ADR and _HID still needs to be fixed before
we can bump our IASL version.
Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reverts commit 547de69de73629c051e9b5312f6369744ec6ce8f.
Merged out of order before CB:36317. The conflicting use of
_ADR and _HID needs to be properly addressed before we can
bump the IASL version.
Change-Id: Iacbc9877a8ff2324eba4789d65df8545b8a25413
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37713
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
These platforms now use a GCC compiled bootblock.
Change-Id: I9a0139f497fe84860664195ed6584f90daecec16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
The split of bootblock initialisation to cpu, northbridge and
southbridge is not specific to intel at all, create new header
<arch/bootblock.h> as AMD will want some of these too.
Change-Id: I702cc6bad4afee4f61acf58b9155608b28eb417e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|