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2019-05-14mb/{lenovo/x201,packardbell/ms2290}: Remove superfluous TS initArthur Heymans
Timestamps are initialized in cpu/intel/car/romstage.c. Change-Id: Ia2b762667be17aa5b482cd585dd6f6198cf50d9e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32758 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-14Remove unnecessary ENV_RAMSTAGE guardSubrata Banik
TEST=Able to build coreboot for CML. Change-Id: Ic0f473e04ffc1de50dee871af52eacf0b328b376 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32764 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13Reland "Makefile.inc: Enable -Wtype-limits""Julius Werner
This reverts commit 99e836c843e6a8536348d5cc9581b5a17512a263. This relands commit c4ab50cdde4bfd01ec7509012b105c88bcf4c953. The issues with -Wtype-limits in the vboot submodule have been resolved now, so we can enable this flag again. Change-Id: I32e8cc88e69072e7ee66cf443b578a9a8ea0ebe2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2019-05-13crossgcc: Upgrade acpica to version 20190509Elyes HAOUAS
Changes: https://acpica.org/node/170 Change-Id: I6779a20005ffc0d4781bb60de3ba48759ef67d40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-133rdparty: Uprev vboot submodule to upstream masterJulius Werner
This patch uprevs the vboot submodule to the new upstream HEAD commit dac763c782 Make vboot -Wtype-limits compliant Change-Id: I363e218e019b25483bc4c06315ca4e0e34599daf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-13i82801gx/bootblock: Use macro instead of magic numberElyes HAOUAS
Change-Id: I2556c150f53d9580bc3b70ab49b3a2c8477c18ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13soc/intel/{cannonlake,icelake}: Drop unused cbmem.c fileElyes HAOUAS
Change-Id: Ib9444f7797289c9b8250cfb16eb1c12dff867ec3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-13{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macroElyes HAOUAS
Use BIOS_CNTL defined macro instead of magic number. Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13nb/intel/sandybridge: Move boot_count_increment()Patrick Rudolph
Move boot_count_increment() to romstage.c, drop preprocessor code and only increase counter once on regular boot. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32067 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13nb/intel/sandybridge: Migrate MRC settings to devicetreePatrick Rudolph
* Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree. This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure. The followup commit will migrate to devicetree.cb. Tested on Lenovo T520, boots MRC path with the new devicetree settings. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Reviewed-on: https://review.coreboot.org/c/coreboot/+/32069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13mb/samsung/lumpy: Move onboard SPD to second channelPatrick Rudolph
Move the onboard SPD to second channel as native raminit does and workaround mrc expecations in northbridge code. Required to move pei data to devicetree and to use the same code for mrc and native raminit. Tested on Lenovo T520: Other fields then spd_data[0] are ignored. Change-Id: If1910e82a4bd178c2a6c2991c91e09782122888e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13nb/intel/sandybridge: Update pei_data commentsPatrick Rudolph
Update outdated comments. Change-Id: I100f71345281a1dc52e99d2395f528d60a9a1f58 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13src/ec/lenovo/h8/acpi: Serialize Control MethodElyes HAOUAS
IASL reports warning 'Control Method should be made Serialized'. Change-Id: I034f2c00e912e8f9ef87b9918de1db06fade38b9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13mb/lenovo/s230u: Rewrite trigger inversion ACPI codeMartin Roth
The GPIO invert registers are already defined in the PCH code, so just use the 8-bit versions of the registers instead of creating a new GPIO field for the single bits. This allows us to get rid of the Field(GPIO...) code that's causing problems with IASL version 20190509. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Iac5dfb71b3a2b5a25c05a403cf5f403c7acecaaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-05-13mb/t400/acpi: Update ATPR buffer to fit all entriesElyes HAOUAS
Error spotted using acpica version 20190509 (Change-Id: I6779a20). Change-Id: Ic9cf16a7494667f6dab156c697fb8f8e9966051e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-13libpayload/drivers/i8042: Add fallthrough commentJacob Garber
Ctrl-delete does nothing, so it falls through to the default case. Add a comment to make this explicit. Found-by: Coverity Scan #1260878 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I4a6f51cb04696b6ebcb554c5667a5bbea58622c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13util/inteltool: Use appropriate channel for printing timingsJacob Garber
At least one channel must be present, so print an error if there is not. However, we cannot always assume it will be the first channel, so make the appropriate selection when printing the timings. Found-by: Coverity Scan #1370{584,585,588,589,590-596,600} Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13soc/intel: Geminilake Refresh feature request supportJohn Zhao
Add 0x706a8 for GLK Refresh CPU stepping ID. BUG=b:132414963 BRANCH=None TEST=Image built successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I4641d9bd4c82211e7200f617cae9043b0f2f38d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-13mainboard: remove "recovery" gpio, selectively add "presence" gpio.Matt Delco
The gpio table is only used by depthcharge, and depthcharge rarely has a need for the "recovery" gpio. On a few boards it does use the gpio as a signal for confirming physical presence, so on that boards we'll advertise the board as "presence". All these strings probably should have been #defines to help avoid typos (e.g., the "ec_in_rw" in stout seems questionable since everybody else uses "EC in RW"). Cq-Depend: chromium:1580454 BUG=b:129471321 BRANCH=None TEST=Local compile and flash (with corresponding changes to depthcharge) to 2 systems, one with a "presence" gpio and another without. Confirmed that both systems could enter dev mode. Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-13libpayload: classify all keyboardsMatt Delco
Depthcharge uses the keyboard type to help determine whether it can trust the keyboard for security-sensitive confirmations. Currently it trusts anything except usb, but now there's a need to distrust ec-based ps/2 keyboards that are associated with untrusted ECs. To help facilitate this, coreboot needs to report more details about non-usb keyboards, so this change replaces the current instances of unknown with enum values that distinguish uart and gpio from ec-based keyboards. BUG=b:129471321 BRANCH=None TEST=Local compile and flash to systems with trusted and non-trusted ECs. Confirmed that security confirmation can't be performed via keyboard on a system with an untrusted EC but can still be performed on a system with a trusted EC. Change-Id: Iee6295dafadf7cb3da98b62f43b0e184b2b69b1e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-13mb/google/sarien: config ISH_GP6 with NF2Jett Rink
A12 is not current set for ISH_GP6 so the ISH_LID_CL#_TAB signal is not making it to the ISH properly. Enable the second native function instead of the first. BRANCH=none BUG=b:131785573 TEST=gpioget on ISH now shows the correct gpio level Change-Id: Ib3a654ae659037263aa9aa29d45b42ca67b7955b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32738 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13lib/hexdump: Drop redundant isprint() implementationNico Huber
Change-Id: I23e2d89274553cbc75e42f0420a1a84d4cec4340 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-13util/kconfig: Use snprintf to avoid buffer overflowJacob Garber
'name' and 'env' are supposed to be file system paths, but could overflow the buffer if configured incorrectly. Let's avoid that entirely. Found-by: Coverity Scan #1362515 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I1aef36819d49ebcbde1c51995dc0961c85e74150 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13soc/intel/braswell: Remove unused include <timestamp.h>Elyes HAOUAS
Change-Id: Ied645a583f78bc47c8358240acd639132fd499db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-05-13mainboard: Remove unused include <timestamp.h>Elyes HAOUAS
Change-Id: Id05fc39c0c0d0560e34e55f793060d29df82d026 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-05-13soc/intel/braswell: Add tsc_freq.c and pmutil.c in verstageFrans Hendriks
Systems with C_EVIRONMENT_BOOTBLOCK and VBOOT enabled requires functions tsc_freq_mhz(), vbnv_cmos_failed() and vboot_platform_is_resuming() in verstage. Add tsc_freq.c and pmutil.c to verstage. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 + Building Google Banon Change-Id: Ia509eda6bf415aaa63be71013249493aa472289d Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13util/intelvbttool: Add error checking for memory allocationJacob Garber
It is possible that 'malloc_fo_sub' and 'remalloc_fo' can fail, so add appropriate error checks for those cases. This incidentally fixes a possible memory leak when 'malloc_fo_sub' succeeds but 'remalloc_fo' does not. Found-by: Coverity Scan #1396050 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13util/intelvbttool: Free file object on error pathJacob Garber
Prevents a memory leak. Found-by: Coverity Scan #1396047 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13util/ifdtool: Add find_fd null checkJacob Garber
As the previous comment indicated, this null check is currently superfluous, but adding it in makes Coverity happy, and future-proofs the code in case someone changes the internals of 'find_fcba' later and forgets/doesn't know to update this error check. Found-by: Coverity Scan #1395066 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13lapic/lapic_cpu_init: Add cpu_add_map_entry() to store default_apic_idSubrata Banik
This patch ensures start_cpu() function to store default_apic_id using common cpu_add_map_entry() function to make cpu_index() implementation generic. BRANCH=none BUG=b:79562868 Change-Id: Iac4d6e9e6e6f9ba644335b4b70da8689c405f638 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13src/arch/x86: Use core apic id to get cpu_index()Subrata Banik
This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not be true in case of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retrieving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpus_default_apic_id[] variable to return correct cpu_index(). BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26346 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-12mb/asrock/h81m-hds: Drop now obsolete libgfxinit overrideNico Huber
CPU type is detected at runtime now. Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
We keep the support, though. Just now that `libgfxinit` is fixed, we don't need the distinction anymore. Causally, we also don't need CPU_INTEL_MODEL_306AX any more. TEST=Played tint on kontron/ktqm77. Score 606 Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-123rdparty/libgfxinit: Update for runtime CPU detectionNico Huber
Beside one tiny fix for framebuffer scaling, this contains a major refactoring of libgfxinit's configuration infrastructure. With this, we are finally able to detect CPUs at runtime and only have to confi- gure a CPU/GPU generation. Change-Id: Iccf4557453878536f527e4a1902439a1961ab701 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32736 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-123rdparty/libhwbase: Update to current masterNico Huber
Beside some refactorings that don't affect coreboot, this contains bd0ed91 (Makefile: Revise support for generated sources) that fixes an issue with upcoming libgfxinit configuration changes. Change-Id: Ib47aeff8f6426ae27ddbc235a954e3bd60029072 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32735 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-12mb/lenovo/*: Add MAINBOARD_FAMILYPatrick Rudolph
The Kconfig MAINBOARD_FAMILY sets the family field of SMBIOS entry 1. Match what vendor firmware does and use the same value as in the version field. Required for fwupd which uses the family field to generate a GUID. Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-12boot_device: Constify argumentPatrick Rudolph
Add const qualifier to first argument. Change-Id: I6655e04401b6a7aa5cafb717ff6f46b80b96646e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-12lib/timestamp: Make timestamp_sync_cache_to_cbmem() in postcarSubrata Banik
This patch ensures to have correct timestamp value in postcar. Change-Id: I3ba3a54c20dfcdaf5b87818cc5da9a812f5f2edf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-12Kconfig: Create RAMPAYLOAD kconfigSubrata Banik
This patch enables coreboot flow to skip ramstage as individual stage to load payload. Instead it is expected to load payload from postcar stage. Change-Id: I839f2d34a93b69ca6bf3de6594e2ad9f66ee7135 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2019-05-12arch/cpu: Rename mp_get_apic_id() and add_cpu_map_entry() functionSubrata Banik
This patch renames mp_get_apic_id() to cpu_get_apic_id() and add_cpu_map_entry() to cpu_add_map_entry() in order access it outside CONFIG_PARALLEL_MP kconfig scope. Also make below changes - Make cpu_add_map_entry() function available externally to call it from mp_init.c and lapic_cpu_init.c. BRANCH=none BUG=b:79562868 Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-11soc/intel/cnl: Enable VT-dJohn Zhao
Enable VT-d through fsp upd VtdDisable. Update remapping structure types in numerical order as all remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2019-05-11Define ENV_PAYLOAD_LOADERRonald G. Minnich
We've been assuming that ENV_RAMSTAGE is always the payload loader. In order to test out different models, we need a way to mark the "stage we are in" as the payload loader. Define a new rule, ENV_PAYLOAD_LOADER. For now, it is set to ENV_RAMSTAGE. It is not used yet pending approval of this approach. Change-Id: I7d4aa71bad92987374d57ff350b9b0178ee7c12b Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10vboot: Turn vboot_logic_executed() into a static inlineJulius Werner
This patch moves vboot_logic_executed() (and its dependencies) into a header and turns it into a static inline function. The function is used to guard larger amounts of code in several places, so this should allow us to save some more space through compile-time elimination (and also makes it easier to avoid undefined reference issues in some cases). Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-05-10assert.h: Undefine ASSERT macro in case vendorcode headers set itJulius Werner
Some edk2 vendorcode headers define an ASSERT macro. They're guarded with an #ifndef ASSERT, but if coreboot's assert.h gets included after that header, we still have a problem. Add code to assert.h to undefine any rogue definitions that may have already been set by vendorcode headers. This is ugly and should only be a stopgap... it would be nice if someone maintaining those vendorcode parts could eventually replace it with a better solution. One option would be to use a "guard header" for every vendorcode header we want to pull into normal coreboot code which would chain-include the vendorcode header and then undefine anything that clashes with coreboot again. Change-Id: Ibf8dc8b2365821e401ce69705df20aa7540aefb2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-10vboot: Make vboot_logic_executed() a bit more preciseJulius Werner
This patch adds another check to vboot_logic_executed() to make sure we only do a runtime check for verstage_should_load() if CONFIG_VBOOT_RETURN_FROM_VERSTAGE is enabled. That's the only case where the stage that's loading the verstage can execute after verification has run (because the verstage will return to it when it's done). In the other case, the stage that loads verstage really just loads it and will never do anything again after hand-off, so it's guaranteed to always execute before verification. This change may allow extra dead-code elimination in some cases. Change-Id: I7019b6f7b0acfbf0a8173914b53364751b08f2cf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-05-10soc/amd/stoneyridge: Add IO access functions for PMxMarshall Dawson
Replace locations in the source that explicitely use the CD6/CD7 index/data pair with utility function calls. Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-10mb/google/sarien: Fix s5 touchscreen power leakageLijian Zhao
Leakage power is observed from TOUCH_SCREEN_PD# (GPP_E7 which is connected to RESET pin of Wacom controller) during S5. To avoid leakage power, GPP_E7 needs to be turned off before S5 entry. BUG=b:129899315 TEST=Measure leakage power in S5 from both Arcada and Sarien Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c Reviewed-on: https://review.coreboot.org/c/coreboot/+/32367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-05-10sb/bd82x6x: Don't rewrite over BCTRLElyes HAOUAS
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). Some lines obove that code line, the "write" on BCTRL is already done. Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32700 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-10sb/i82801gx: Don't rewrite over BCTRLElyes HAOUAS
PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). BCTRL registry for D30:F0 is defined at offset 0x3e for i82801gx (see ICH7 Family Datasheet page 355). The write on that register is already done some lines above. So remove wrong register name and the wrong code line. Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-10mb/google/nami: Add VBT blobs and include them in cbfsArthur Heymans
Add vbt files for nami variants and select Kconfig option to utilize them. The default vbt is automatically added by the Kconfig selection and so does not need to be specified in the makefile with the others. Test: boot vayne and akali nami variants, verify display functional and correct vbt loaded. Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-02 17:36:29 +0000