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2013-06-04Asus M4A785T-M: Add CMOS defaults.Denis 'GNUtoo' Carikli
After removing power and the CMOS Battery, putting it back and booting coreboot we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Enable baud_rate = 115200 hw_scrubber = Enable interleave_chip_selects = Enable max_mem_clock = 400Mhz multi_core = Enable power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0xc slow_cpu = off nmi = Enable iommu = Enable nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide. nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3324 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04PC Engines ALIX.1C: Add CMOS defaults.Denis 'GNUtoo' Carikli
After Booting the BIOS, flashing coreboot and booting coreboot with that patch we have: # ./nvramtool -a boot_option = Fallback last_boot = Fallback ECC_memory = Disable baud_rate = 115200 power_on_after_fail = Disable debug_level = Spew boot_first = HDD boot_second = Fallback_Floppy boot_third = Fallback_Network boot_index = 0xf boot_countdown = 0x7f nvramtool: Warning: Coreboot CMOS checksum is bad. Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3323 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04pci_ids.h: Add PCI IDs for VIA VX900 chipsetAlexandru Gagniuc
Change-Id: I4a75326fef0a10a6290cdd4b1b93d9af8e3ab23d Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3268 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-04superiotool: Add dump facility for HWM of W83627DHG-PNico Huber
Change-Id: I9355996a8cf1b7cb91cc415ec04f5108a1cc42a5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3358 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04superiotool: Add dump facility for ITE IT8516 + I/O 0x20e/fNico Huber
Change-Id: Iaea08b7eb5aac9ff1e0756f1400a82641bb45b14 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3359 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04libpayload: Whitelist Mobile Panther Point AHCI controllerNico Huber
Add the Mobile Panther Point (PPT) AHCI controller (DEVID 0x1e03) to the list of tested controllers. Also comment the only other listed controller (Mobile ICH9). The PPT AHCI controller was tested with a QM77 chipset on a Kontron KTQM77 board. Change-Id: Ia396761411f4f9289af11ec8e1b144512b2fc126 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3361 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04fix tinycursesPatrick Georgi
Change-Id: I9e7bde7b2c90b8b34c6aa8e90a16cd29dc108fe9 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/3360 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04coreboot: Add generic early SMBus APIAlexandru Gagniuc
Early SMBUS code with similar functionality is duplicated for all southbridges. Add a generic SMBus API (function declarations) designed to unify the early SMBus structure. This patch only adds the API. It does not implement any hardware-specific bits. Change-Id: I0861b7a3f098115182ae6de9f016dd671c500bad Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/143 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04DDR3: Add utilities for creating MRS commandsAlexandru Gagniuc
MRS commands are used to tell the DRAM chip what timing and what termination and drive strength to use, along with other parameters. The MRS commands are defined by the DDR3 specification [1]. This makes MRS commands hardware-independent. MRS command creation is duplicated in various shapes and forms in any chipset that does DDR3. This is an effort to create a generic MRS API that can be used with any chipset. This is used in the VX900 branch. [1] www.jedec.org/sites/default/files/docs/JESD79-3E.pdf Change-Id: Ia8bb593e3e28a5923a866042327243d798c3b793 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3354 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04VIA Nano: Add microcode updates filesAlexandru Gagniuc
While we had support for updating microcode on the VIA Nano CPUs for a while now, we never included the actual microcode. Unlike, Intel and AMD CPUs, VIA microcode is not available for download, and was extracted from the vendor BIOS. It was not included in coreboot since we never had explicit permission to do so. I have just received confirmation from VIA that we can distribute the microcode. Change-Id: I4c15b090cd2713cfe5dc6b50db777ff89dbc0f19 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3357 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-06-04AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"Christian Gmeiner
Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: convert spd_read_byte() to non-static versionChristian Gmeiner
Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3369 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: move #include "northbridge/amd/lx/raminit.h"Christian Gmeiner
Move the include before static inline int spd_read_byte(). Change-Id: I4cac4b1f55368041b067422d95c09208e15d0f2d Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3368 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: rename get_systop() to get_top_of_ram()Christian Gmeiner
Change-Id: I6126d575b8289f76b38858304836e3037200bcdb Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3367 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: include northbridge.h in raminit.cChristian Gmeiner
Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3365 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-staticChristian Gmeiner
Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3364 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: add some missing includesChristian Gmeiner
This commit fixes problems if we build raminit.c for romstage. Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3363 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Northbridge LX: make sdram_* function prototypes non-staticChristian Gmeiner
In order to get rid of the bad #include "northbridge/amd/lx/raminit.c" line we need to do some prepartion steps. This commit is one of them. Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3362 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04AMD Fam 15tn: Use all memory on systems with more than 4 GBSiyuan Wang
Take a Parmer board with 4G memory as an example. Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'. Parmer uses 512M as video memory when it has 4G. 3327540+512*1024 = 3851828(kB), so some memory is lost. When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is 0x00000001. But in e820 table or coreboot table, the last item is 6: 0000000100000000 - 0000000118000000 = 1 RAM This is not correct, it should be 6: 0000000100000000 - 000000011f000000 = 1 RAM This patch changes the memory layout when TOM2 is set. Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3366 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04crossgcc/buildgcc: Remove unneeded 'break' statementsDavid Hubbard
Bash case statements are terminated with ';;'. Unlike C, bash case statements will not continue to the next case. No 'break' is needed. Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036 Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Reviewed-on: http://review.coreboot.org/3330 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-03dram: Add utilities for decoding DDR3 SPDsAlexandru Gagniuc
Add convenience utilities for decoding DDR3 SPDs and printing the information to the console. These have proven invaluable when writing the VX900 memory initialization. These are used in the VX900 branch Information printed has the following format: > SPD Data for DIMM 51 > Revision: 10 > Type : b > Key : 2 > Banks : 8 > Capacity: 1 Gb > Supported voltages: 1.5V > SDRAM width : 8 > Bus extension : 0 bits > Bus width : 64 > Optional features : DLL-Off_mode RZQ/7 RZQ/6 > Thermal features : ASR ext_temp_range > Thermal sensor : no > Standard SDRAM : no > Row addr bits : 13 > Column addr bits : 10 > Number of ranks : 1 > DIMM Capacity : 1024 MB > CAS latencies : 6 7 8 9 > tCKmin : 1.500 ns > tAAmin : 13.125 ns > tWRmin : 15.000 ns > tRCDmin : 13.125 ns > tRRDmin : 6.000 ns > tRPmin : 13.125 ns > tRASmin : 36.000 ns > tRCmin : 49.125 ns > tRFCmin : 110.000 ns > tWTRmin : 7.500 ns > tRTPmin : 7.500 ns > tFAWmin : 30.000 ns Change-Id: I30725a75caf74ac637db0a143344562bd9910466 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3267 Tested-by: build bot (Jenkins)
2013-06-03spd.h: Add all known SPD_MEMORY_TYPE definitions.Alexandru Gagniuc
This file was missing some definitions, so add them. Also turn the defines into an enum. The reason for doing this is that functions can now explicitly take an spd_memory_type as a parameter: > int do_something_with_dram(enum spd_memory_type type, ...) Which is a lot more explicit and readable than: > int do_something_with_dram(u8 type, ...) These are used in the VX900 branch. Change-Id: Ic7871e82c2523a94eac8e07979a8e34e0b459b46 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3266 Tested-by: build bot (Jenkins)
2013-06-03util/cbmem: Fix format string in cbmem.cNico Huber
Use PRIx64 to print a u64 instead of "llx". Fixes the following error: cbmem.c: In function 'parse_cbtable': cbmem.c:135:2: error: format '%llx' expects argument of type 'long long unsigned int', but argument 2 has type 'u64' [-Werror=format=] Change-Id: Ibc2bf8597cb86db5b2e71fba77ec837a08c5e3d4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/3301 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-03include/cpu/amd: Align `CPU_ID_EXT_FEATURES_MSR` with other definesPaul Menzel
Probably due to different (character) widths for a tab, sometimes only one tab was used for aligning the define `CPU_ID_EXT_FEATURES_MSR`. For the “correct” alignment, that means where a tab is eight characters, two tabs are necessary. Change it accordingly. Change-Id: I450a7796dc00b934b5a6bab8642db04a27f69f4b Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3263 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03Asus F2A85-M: Fix the _CRS PCI0 bus infoRudolf Marek
On Asus F2A85-M, the Linux kernel complains that the _CRS method does not specify the number of PCI busses. [FIRMWARE BUG]: ACPI: no secondary bus range in _CRS Just put there 256. This should be part of re-factoring of the whole ACPI stuff. The same change was already done for the AMD Brazos (SB800) boards, based on commit »Persimmon DSDT: Add secondary bus range to PCI0« (4733c647) [1]. [1] http://review.coreboot.org/2592 Change-Id: I06f90ec353df9198a20b2165741ea0fe94071266 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/3320 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-06-03AMD Geode CS5536: downgrade BIOS_ERRChristian Gmeiner
There is no need to use everywhere BIOS_ERR. Change-Id: If33d72919109244a7c3bd96674a4e386c8d1a19e Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3307 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03console: add support for QEMU's debugconGerd Hoffmann
Add support for sending debug output to an I/O port. It can be used together with QEMU's isa-debugcon driver to log the coreboot output to a file. The port is configurable and defaults to 0x402 which has established as the de facto standard. For example, SeaBIOS+OVMF [1] use that one too. [1] http://www.linux-kvm.org/page/OVMF Open Virtual Machine Firmware Change-Id: I0803f7fc70030242f80003e25c9449c37d71975e Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3331 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03haswell: allow for disabled hyperthreadingAaron Durbin
There were assumptions being made in the haswell MP and SMM code which assumed the APIC id space was 1:1 w.r.t. cpu number. When hyperthreading is disabled the APIC ids of the logical processors are all even. That means the APIC id space is sparse. Handle this situation. Change-Id: Ibe79ab156c0a171208a77db8a252aa5b73205d6c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3353 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03haswell: fix overflow handling TOUUDAaron Durbin
It's possible that the TOUUD can be set to less than 4GiB. When that is the case the size_k variable is an extremely large value. Instead ensure TOUUD is greater than 4GiB before adding said resources. Change-Id: I456633d6210824e60665281538300fd15656b86d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3352 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-03Intel Lynx Point: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3182 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-03Intel BD82x6x: LPC: Unify I/O APIC setupPaul Menzel
Remove local copies of reading and writing I/O APIC registers by using already available functions. This change is similar to commit db4f875a412e6c41f48a86a79b72465f6cd81635 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Reviewed-on: http://review.coreboot.org/300 and commit e614353194c712a40aa8444a530b2062876eabe3 Author: Kyösti Mälkki <kyosti.malkki@gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Reviewed-on: http://review.coreboot.org/2532 and uses `io_apic_read()` and `io_apic_write()` too. Define `ACPI_EN` in the header file `pch.h`. As commented by Aaron Durbin, a separate `pch_enable_acpi()` is not needed: “The existing code path *in this file* is about enabling the io apic.” [1]. [1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3183 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-06-03northbridge/amd/amdmct: Use `static const` instead of `const static`Paul Menzel
From ISO C99 standard: »The placement of a storage-class specifier other than at the beginning of the declaration specifiers in a declaration is an obsolescent feature.« Found at <http://www.approxion.com/?p=41>. The following command was used to make the change. $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/' As asked by Bruce Griffith, the changes in `src/vendorcode` were reverted as that is what AMD prefers. The same change was done already for AMD Persimmon in the following commit. commit 824e192809e021b3cdee947a44b3a18d276bdb35 Author: Jens Rottmann <JRottmann@LiPPERTembedded.de> Date: Wed Feb 20 21:24:20 2013 +0100 Persimmon: platform_cfg.h: Declare codec arrays as `static const` Reviewed-on: http://review.coreboot.org/2474 Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3197 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03am335x: Clean up/fix some settings in the am335x Kconfig.Gabe Black
Some settings in the am335x Kconfig weren't actually used for anything, some where place holders, and some where left over from another CPU. The memory addresses are in the internal RAM in the SOC as described in the reference manual. The stack is put where the internal ROM had its stack, and the bootblock is put at the bottom of that region as the manual suggests. The ROM stage offset is set to 10K which is a bit bigger than the ~7.5K the bootblock currently takes up. Change-Id: I1a117d789a791d7e3db1118823f8216b3361433c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3327 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-06-02Provide sane Kconfig default for cmos.default.Denis 'GNUtoo' Carikli
Without that fix we have with CONFIG_USE_OPTION_TABLE: OPTION cmos_layout.bin build/util/nvramtool/nvramtool -y /home/gnutoo/x86/coreboot-alix/src/mainboard/pcengines/alix1c/cmos.layout -L build/cmos_layout.bin make: *** No rule to make target `nvramtool', needed by `build/coreboot.pre1'. Stop. rm build/util/sconfig/sconfig.tab.c build/cbfs/fallback/bootblock.elf build/util/sconfig/lex.yy.c That log was captured with make V=1 but the error also appear with make. Tested on the PC Engines ALIX.1C with the following commit (Change-Id: Ia87b090) [1]: PC Engines ALIX.1C: Add CMOS defaults. [1] http://review.coreboot.org/#/c/3323/ Change-Id: I548005a58f430ed7b6da5249a24bbdcae440a1e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3223 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-05-31Lenovo ThinkPad X60: cleanup Native VGA init.Denis 'GNUtoo' Carikli
Change-Id: Iaefa23a6257fd0295357465eb03ccadbef0f70da Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: http://review.coreboot.org/3272 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-31AMD Trinity boards: Add reserved memory area for SPI base address in ACPISteven Sherk
- SPI controller base address gets overwritten by SD controller under Linux. - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't get automatically reserved. Solution is to add it as a reserved memory area in ACPI. - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this platform was made as part of: http://review.coreboot.org/#/c/3167/3 - Once approved a follow-on patch for other southbridges using a non-standard BAR for the spi controller. Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: http://review.coreboot.org/3270 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-31AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard'Siyuan Wang
This issue can be reproduced in Linux by the following steps: 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. In this patch, I add AcpiGpe0Blk using MMIO access and write 1 on bit 11. I have tested on Parmer. Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1 Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com> Reviewed-on: http://review.coreboot.org/3347 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-30AMD Llano, Brazos boards: Use `sizeof(var)` to get its sizePaul Menzel
Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Rudolf Marek’s patch »ASUS F2A85-M: Correct and clean up PCIe config« [1] contains the same change and is ported over. In the commit message Rudolf makes the following comment. »Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR?« Testing on the ASRock E350M1, no regressions were noticed. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I123031b3819a10c9c85577fdca96c70d9c992e87 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3248 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-30AMD Trinity boards: Use `sizeof(var)` to get its sizeRudolf Marek
Change `sizeof(type) * n`, where n is the number of array elements, to `sizeof(variable)` to directly get the size of the variable (struct, array). Determining the size by counting array elements is error prone and unnecessary. Not sure why the copy is needed instead of direct reference. Maybe it has something to do with CAR? These changes are based on Rudolf’s original patch »ASUS F2A85-M: Correct and clean up PCIe config« [1], where it was just done for the ASUS board. [1] http://review.coreboot.org/#/c/3194/ Change-Id: I4aa4c6cde5a27b7f335a71afc21d1603f2ae814b Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3247 Tested-by: build bot (Jenkins) Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-05-29qemu: remove vga hookGerd Hoffmann
Extra care for the qemu vga should not be needed any more. Since release 0.12 qemu loads the vgabios into the PCI ROM bar, so everything works exactly like it does on real hardware. Change-Id: I4b9bf1244cad437cbe5168600aeee52031456033 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: http://review.coreboot.org/3333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-29cpu/amd/geode_lx/Kconfig: Select TSC_MONOTONIC_TIMERChristian Gmeiner
The following is an excerpt from serial log of the Bachmann OT200. $ grep usec coreboot_log clocks_per_usec: 500 Root Device init 48034 usecs CPU_CLUSTER: 0 init 133251 usecs PCI: 00:01.0 init 33376 usecs PCI: 00:01.1 init 9930 usecs PCI: 00:01.2 init 9929 usecs PCI: 00:04.0 init 9929 usecs PCI: 00:0f.0 init 185788 usecs PCI: 00:0f.2 init 21473 usecs PCI: 00:0f.3 init 9930 usecs PCI: 00:0f.4 init 9930 usecs PCI: 00:0f.5 init 9930 usecs PCI: 00:0f.6 init 9930 usecs PCI: 00:0f.7 init 9929 usecs Change-Id: I4d0805c4cf8fcb25ec107615787fc6da0c945a30 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: http://review.coreboot.org/3308 Tested-by: build bot (Jenkins)
2013-05-27util/inteltool: Add support for mobile 5 chipsetVladimir Serbinenko
Dump registers on mobile 5. Successfully tested on X201. Change-Id: I606371801d3ae6c96d3d404c9775c254bd0ffbc9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/2993 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-05-26beaglebone: initial Kconfig and MakefilesGabe Black
Initial structure of Beaglebone port Change-Id: Ia255ab207f424dcd525990cdc0d74953e012c087 Signed-off-by: David Hendricks <dhendrix@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26Get buildgcc to behave reasonably with the -p choice.Ronald G. Minnich
buildgcc has many wrong choices, and two right ones, but you would never guess that. It's even more frustrating when it spends lots of time building a full tool chain and you find out it's not the one you wanted and, still worse, you've forgotten what it does want and, even worse, it won't f-ing tell you what the two right choices are!. Have it tell you when you've done something wrong, and have it make reasonable decisions when you say things like -p arm instead of -p armv7a-eabi This change lowers my blood pressure 10 points. Change-Id: I44a59d7cb7a6260894d8bcb692a693ed25681ff8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3292 Tested-by: build bot (Jenkins)
2013-05-26Lenovo ThinkPad T60: Add support for `EARLY_CBMEM_INIT` needed for CBMEM consolePaul Menzel
Add code to support `EARLY_CBMEM_INIT` needed for CBMEM console support by copying GNUtoo’s commit for the Lenovo ThinkPad X60. commit 4560ca5003fe38a066616e8de1a8a414284750fd Author: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Date: Fri Apr 26 12:21:41 2013 +0200 Lenovo ThinkPad X60: Init CBMEM early for CBMEM console support. Reviewed-on: http://review.coreboot.org/3142 Change-Id: I0c4ca5a5e60f4bb3b91653a133ec71039fcca6ab Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3187 Tested-by: build bot (Jenkins) Reviewed-by: Denis Carikli <GNUtoo@no-log.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-05-26snow: Add a name to the serial console UART choice block.Gabe Black
This allows other boards to have the same choice block without confusing kconfig. Change-Id: Iea5a7f2d1c263aa7992f504b832ca9c862833c3f Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3293 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-05-26kconfig: fix choice dependency checkRoman Zippel
Properly check the dependency of choices as a group. Also fix that sym_check_deps() correctly terminates the dependency loop error check (otherwise it would continue printing the dependency chain). Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ======= Cherry-picked from the Linux kernel. Change-Id: I0c98760dd0f55cf2ff70c53e0b014288b59574c8 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3290 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26kconfig: reversed borderlines in inputboxRoel Kluin
Fix reversal of dlg.border.atr and dlg.dialog.atr for draw_box() Makes the inputbox look like expected Signed-off-by: Roel Kluin <12o3l@tiscali.nl> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ======= Cherry-picked from the Linux kernel. Change-Id: I596915aab0204ef0e392fefa56fad8e25204e207 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3289 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-26kconfig: add named choice groupRoman Zippel
As choice dependency are now fully checked, it's quite easy to add support for named choices. This lifts the restriction that a choice value can only appear once, although it still has to be within the same group, but multiple choices can be joined by giving them a name. While at it I cleaned up a little the choice type logic to simplify it a bit. Signed-off-by: Roman Zippel <zippel@linux-m68k.org> Signed-off-by: Sam Ravnborg <sam@ravnborg.org> ======= Cherry-picked from the Linux kernel. Change-Id: If0f00d1783907d606220cda5307b8960d3bfc38d Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3291 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-05-25Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h`Ronald G. Minnich
multiply_to_tsc was being copied everywhere, which is bad practice. Put it in the tsc.h include file where it belongs. Delete the copies of it. Per secunet, no copyright notice is needed. This might be a good time to get a copyright notice into tsc.h anyway. Change-Id: Ied0013ad4b1a9e5e2b330614bb867fd806f9a407 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3242 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber@secunet.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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