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2018-05-08mb/biostar: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ifc9d82270513f4b4f34d9cf210c37029202b5a5f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/sapphire: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I93b2ce6a26b3a64bd6f4e4c827e9f551b37c6dd0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nicola Corna <nicola@corna.info>
2018-05-08mb/broadcom: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Icf7c99ca55d2bcbca2c974d59a63e89758ba5ea6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08soc/intel/skylake: Support PCH UART 0 and 1 for consoleDuncan Laurie
The current PCH UART support for console is limited to UART2. This change adds support for specifying UART0 or UART1 to be used instead by changing CONFIG_UART_FOR_CONSOLE in the board level Kconfig. The default is still 2. This is tested with a board that uses UART0 for debug output. Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/26140 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08soc/intel/fsp_broadwell_de: Spell verb *set up* with spacePaul Menzel
Change-Id: If2e66f3531696d430b3ae133c4b7ec0d929713b7 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/26129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/siemens: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If67ea25a9e1363dde8aefe62b92ee7a61f0458b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-05-08mb/sifive: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8c6358d072b25ab4758637da989883daa600c8ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/winnet: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ie6a8364bdd272515e1567061ae0b117392c268aa Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/supermicro: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Icc633dc499568cf672f5e244e026e45a6eea5fd8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/ibase: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ief79d8cc1bfdd271e646d09679514560a2c79209 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/iei: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I2e05cfeeae0f1b3a43eab7ee8059dc13cf474022 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/iwill: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I39fd521ac2f619ae7b5e12755f09bea5d782eae1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/intel: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ie2c466a280d18979d5f9ca182793ed43431d2010 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08mb/superio: Rename global control devices as SUPERIO_DEVElyes HAOUAS
Use SUPERIO_DEV for global control device instead of DUMMY_DEV. Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25852 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/lenovo: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ic044fc074c43db683fcd85ce92a36a8c5a464a67 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-08ec/google/chromeec: add config for wake event typesPatrick Georgi
Avoids array overflow Change-Id: Ia49a782ba6729c740e3b91c500120132983f6b3c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25992 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/jetway: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I574d9e46ebe6993f356c3617f2e5ff21b5ef55a5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/google/poppy/variants/atlas: update DMIC NHLT configurationSathyanarayana Nujella
From coreboot side, include DMIC 4ch NHLT configuration and its DMIC blob. In OS side, cras picks the needed channels using UCM's channel map configuration. So, this patch updates to include DMIC 4ch config. BUG=b:79158926 TEST=Verified 4-ch record with arecord TEST=Also verified internal mic record with cras using 'cras_test_client --capture_file dmic.raw --rate 48000 --num_channels 2 --duration 10' Change-Id: Ic6df00c2f26ad9cdf54152ab021c2b10499c429c Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26019 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08Documentation: Add HiFive Unleashed documentationJonathan Neuschäfer
Change-Id: Ic97955e36feeaa18b5a0dbd502c722c06dcc1b31 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-05-08soc/intel/denverton_ns: Fill dimm info for SMBIOS table 17Julien Viard de Galbert
Rework display_fsp_smbios_memory_info_hob (shared code). Import code to convert memory HOB to dimm info for SMBIOS table 17 mostly copied from fsp1_1 mainboard_save_dimm_info. Change-Id: Id5c4ceaf4e65359f72ec764f0914b5daa82f257e Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23851 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/google/eve: Change rt5663 audio codec's irq as ExclusiveAndWakeHarsha Priya
This patch uses GPIO macro to define rt5663 headset codec's irq as ExclusiveAndWake. This change allows jack detection even when device is in D3 state. TEST=Plug in/out jack when the system is in deep sleep and wake up the system to ensure that jack insertion/removal is detected. Change-Id: Icb72337025a8408ed7ea9b6e60e938dcb88eae76 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/26016 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08arch/x86/acpi_device: Add macros to define gpio with wake flagHarsha Priya
This patch adds new macros to define gpio with an option to either enable irq wake (mark it as ExclusiveAndWake flag in SSDT) or disable it (mark it as just Exclusive flag in SSDT). Change-Id: Ia71559dcae65112b75e4c789328e4a6153e922b0 Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/25838 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08src/southbridge: Add required space before the open parenthesisElyes HAOUAS
Change-Id: If46db4d210e4b25221436ad1222433d3b00e08e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26035 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08mb/roda: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I0830e5519256122e3fe9f142c4c8e1e5e85f9a8c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/kontron: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Iac341f592acd777fe9ba22cfbca19d4cbdb4916e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/lippert: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I9a51ff76bc4fcd6ca659229c87cd7dd5bf83b43b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/pcengines: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8a05bb00dc640fafa1c8e2eaac6427fdb0169f39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/apple: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I14d82b0463d184ae89d7137f2dc6732bbb608b73 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08mb/gigabyte: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I37ba054022241c93c03e6c804e46f4e8a1c1143e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08console: Reduce default loglevel to DEBUGNico Huber
The former default SPEW is very noisy, intentionally. It is usually only useful to debug specific issues and doesn't carry much infor- mational value. Reducing the loglevel should also mitigate overflows in pre-CBMEM console buffers. Change-Id: Iebcd4681572c58f1d17085c5ef01a2dd49e981ca Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26053 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08Move `pci_ops_mmconf` from arch/x86/ to device/Nico Huber
MMConf is not architecture specific. We also always provide a pci_bus_default_ops() now if MMCONF_SUPPORT is selected. Change-Id: I3f9b403da29d3fa81914cc1519710ba7d1bf2bb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26062 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08device/pci_ops: Remove unnecessary weak implementationNico Huber
I doubt this is or will ever be referenced anywhere. And if, we probably shouldn't return. Change-Id: I3704fec694c5e5a9d5ff7d78d8bf2f23cf463e3c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08purism/librem13v1: Fix space->tabs and disable ME pci deviceYouness Alaoui
Change-Id: I7ffcea7bff988d3d4269e1334fc938932aed2eb4 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-08purism/librem13v1: Disable PCI Express AER capabilityYouness Alaoui
The Librem 13v1 does not seem to have working AER and this option was needed and tested on the Librem 13v1. Without it, the linux console gets spammed with AER errrors. Change-Id: I13d0afa085b426920d7a946e6209f924ce29ae52 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08intel/broadwell: Add option to enable/disable the PCIe AER capabilityYouness Alaoui
The Advanced Error Reporting capability was hardcoded in the PCIe extended capability list, but it might not always be possible. The Librem 13v1 does not seem to have working AER and this option was needed and tested on the Librem 13v1. Without it, the linux console gets spammed with AER errrors. Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08intel/broadwell: If L1 Sub state is disabled, do not set capabilityYouness Alaoui
I finally found out why disabling the L1 sub state option did not prevent some NVMe drives from locking up in L1 substate. I expect that the disabled L1 substate initialization that coreboot does is negated because Linux might itself configure it if it finds the capability enabled on the PCIe root port. Removing the capability from the PCIe root port when L1 sub states are disabled in the configuration should fix the problem. This was not tested because it's a difficult issue to reproduce and I do not have the problematic hardware that caused it anymore. Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08Documentation/Intel: Add MultiProcessorInit documentationSubrata Banik
Add documentation for MP service PPI using EFI interface on Intel 9th Gen Platforms. Documented so far: * Problem Statement * New Design Proposal * API interface * Code Flow changes * Benefits BRANCH=none BUG=b:74436746 TEST=none Change-Id: I5b6096ef31d8a523c00cbad39ab9d4884e735fde Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25921 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08drivers/aspeed/ast2050: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I31f53f5f0e3f1fd6bd9bdbb47ea67c12b3840850 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08drivers/xgi/z9s: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ia9c705d34b90ad44272a06790fbb1041029ef77d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26069 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08ec/lenovo/h8: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I3db9487c46b29510e59ec5c019d022f5cbaff354 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08arch/x86/acpi: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I54bebc245df6e967acd30a0b029557e23f8da529 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-08src/mainboard: Set ACPI OEM ID values to 6 characters longMartin Roth
Change OEM ID values to 6 characters to fix error compiling with IASL version 20180427. Also update table creator to 8 characters from 7. Change-Id: Id6c9a7b08dc4a9efeb69011393e29aa5a6bc54c4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-07mb/google/poppy/variants/nami: Invert polarity of EMR_GARAGE_DET#Shelley Chen
This gpio should be active low, but is not currently configured that way. Changing gpio configuration to reflect that. BUG=b:73121017, b:77941823 BRANCH=None TEST=iotools mmio_read32 0xfdae0588 (GPP_E1) Make sure that when pen is ejected, gpio is low and when pen is inserted, gpio is high. Also tested that wake upon pen eject is working. Change-Id: Ic49eea6412c3378dca39a3338b43df12bc27037d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26017 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-07mb/msi: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I7f29fe3b85bc56ff3f2d225822c415513e961459 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2018-05-07mb/winent: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ice673efd52e414e4064734883ca92dce5fc059cd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26093 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-07mb/sunw: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I348a7ad368cf5b5a7837c45038a1659a581c518f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2018-05-07lib/bootmem: ensure ramstage memory isn't given to OSAaron Durbin
When RELOCATABLE_RAMSTAGE is employed ramstage lives within the cbmem area. Don't mark it as OS usable under that circumstance. Change-Id: Ie15775806632bd943b8217c433bc13708904c696 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-06AGESA: Remove remains of HT recoveryKyösti Mälkki
While built, this code was never called. Change-Id: Ie8216d8f4636330d38ea02aab83bc9e440864f17 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-06AGESA f14: Remove early HT initKyösti Mälkki
Syncronise HT init code with f12 vendorcode. Constructor for HT init is not required since init itself is not called. Change-Id: I0552c4d019c700f84d98473978afb18fe4eea1e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 20:27:11 +0000