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2018-06-07util/docker/docs.coreboot.org: Downgrade sphinxPatrick Georgi
Sphinx >= 1.6 can't use recommonmark. debian/stable is ancient enough to have an older version. Change-Id: I287deab9168ab6124b05d0c6d6e8cdbd7fdc2eec Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/26699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-06-07mediatek: Move uart, timer and cbmem code to a common directory.Tristan Shieh
This patch moves uart, timer and cbmem code which can be reused into a common directory under soc/mediatek. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-06-07mediatek: Refactor to sharing code among similar SOCsTristan Shieh
This patch refactor cbmem and timer code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26881 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07mediatek: Refine whitespace and formating changesTristan Shieh
This patch fix whitespace and formating issues: 1. Using two spaces between code and single line comment. 2. No space after asterisk. 3. Fix checkpatch error. 4. Remove spaces after cast operators. BUG=b:80501386 BRANCH=none TEST=the refactored code works fine on the new platform (with the rest of the patches applied) and Elm platform Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/26880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07tint: change the tint download link from HTTP Debian to HTTPS FSFMike Banon
Last time there was a request to change a link from HTTP to HTTPS, also it seems more ethical to use a link to the Free Software Foundation server. SHA1 is the same - 7fcaa428c6d0de7096d1e4fbfd14848096ae5aad. Change-Id: I55147ee2668de03ba6e9feb84936de24b2a001df Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07tint: fix the "Paused - Press any key to continue" message for pauseMike Banon
Earlier this message has not been shown even at the corner of screen. This fixes it by refreshing the screen, and moves it to the center. Change-Id: If4e33e884c00c17f19ab330167d9293c8396ff3e Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-07tint: make it possible to reboot by pressing 'q' key two timesMike Banon
Earlier it was impossible to exit without pressing the power button. Change-Id: Ia56d639fa8e563047fb3d2723695626a449ead40 Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23853 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Tested on Intel D945GCLF, still boots. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25592 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07tint: upgrade the outdated tint payload from 0.03b to 0.04+nmu1Mike Banon
Fixes two buffer overflows and opens a road to further improvements. All the previous adjustments to libpayload_tint.patch (including the latest "use the current time as random seed") have been preserved. Change-Id: I22e65d18a0b1551f7049c4afe7f95868f584cf9b Signed-off-by: Mike Banon <mikebdp2@gmail.com> Reviewed-on: https://review.coreboot.org/23852 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans
This adds a common function to decode the TSEG size from the ESMRAM register. This will come in handy when SMM in TSEG is implemented. This function is used both in romstage and in ramstage. Change-Id: I4e163598752fb6cd036aec229fce439ebad74def Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23448 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07arch/x86/smbios: Conditionally call SMBIOS opsNaresh G Solanki
Check whether device is enabled before calling smbios ops. BUG=None BRANCH=None TEST=Build & boot Soraka. Change-Id: I79681c10679e1de3a2d177503f29239968d0c157 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-07google/chromeec: Set proper dev opsNaresh G Solanki
For enable_resource & set_resource, use default DEVICE_NOOP so that they are not reported as missing during enumeration. BUG=None BRANCH=None TEST= Build & boot soraka. Change-Id: I0fcfb8df39c6313c8a5bab5b780a8ffa7531d210 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26869 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07util/lint: Add filename checkerMartin Roth
Check that filenames have only alphanumeric characters plus underscore, dash, and period. Change-Id: I7bf0be15d588aa1a5ece628b56e871662d6af44b Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07Documentation: Rename file with space in filenameMartin Roth
Change-Id: I10203de578c4dd0b8915dad4b0d456531049328f Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-07mainboard/google/kahlee: Remove colon from filenamesMartin Roth
Change-Id: I3e0ca62ad88aea5c99f9f0902ad8553656469a1c Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/26936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06mb/google/octopus: Update GPIOs as per latest schematicsFurquan Shaikh
Update GPIOs in baseboard to match latest schematics: 1. Get rid of STEST GPIOs(GPIO_{62,84-89}) 2. Get rid of SD_CD_ODL(GPIO_134) 3. Get rid of KB control GPIOs(GPIO_{144-146}) 4. Configure GPIOs for pen eject (GPIO_{144,145}). Additionally, fix the configuration for other pen GPIOs. BUG=b:109764138 Change-Id: I8e40dd90b2784596f055538e57ea67482c4c517a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26874 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06mb/*/*: Add a few VBT filesArthur Heymans
These files are directly extracted from the vendor firmware. Change-Id: I1dea2843255e4a3e93fbb734dea284be029dbc45 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06drivers/intel/gma: Include mainboard data.vbtArthur Heymans
This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path to point to the mainboard dir and to select INTEL_GMA_ADD_VBT_DATA_FILE by default. Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-06arch/x86: Always select RELOCATABLE_MODULESKyösti Mälkki
All boards except those with NO_RELOCATABLE_RAMSTAGE or explicit select already had this feature built. Change-Id: I838e12141243ec49c2555c09269e07476eb0cfad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06intel/e7505: Remove ROMCC workaroundKyösti Mälkki
Choose codepath as if ROMCC_IF_BUG_FIXED was set. Change-Id: I74b4fe4a915b70f63ea018035381b64f53af3c7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06Documentation/releases: Add release notesMartin Roth
This adds the release notes for all of our old releases that have notes to the documentation directory. The release notes for the next release, 4.9 is added here as well. I would request that people document their changes for the next release themselves if they wish them to be in the release notes. Change-Id: I7440a3130f2f7d80c4434d2b5a918e62bbd08fbb Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06mb/lenovo: Add ThinkPad W530 supportEvgeny Zinoviev
Tested and working: - Wi-Fi - Ethernet - WWAN ? (interface is created in linux, didn't actually test it, should work) - Bluetooth - Speakers - Internal mic - SD card reader - Suspend and resume - Keyboard, touchpad, trackpoint - Fan - Webcam - 4 RAM slots - All USB ports - mSATA - VGA ROM (FIXME: black screen after resume from s3) - Native graphics initialization (FIXME: probably incorrect panel frequency, etc. in GRUB; in linux everything's fine incl. resume from s3) - libgfxinit - GRUB payload - SeaBIOS payload - Internal flashing using flashrom Not tested yet: - Fingerprint reader - Colorimeter - Smart card reader - Docking station - VGA output - Optical disc drive - Discrete graphics TODO: - Test BDC detection Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/26136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-06arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki
To flip the Kconfig default, flag some platforms with NO_RELOCATABLE_RAMSTAGE. Change-Id: I72c6d07e5a60789bbe0e068a0130d7e3bd07a1d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06arch/x86: Use fixed size limit with RELOCATABLE_RAMSTAGEKyösti Mälkki
With RELOCATABLE_RAMSTAGE, variables RAMBASE and RAMTOP have no meaning any more. Change-Id: I711fe98a399177c2d3cb2a9dcdefba61031fb76d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06hp/compaq_8200_elite: Fix TPM not visible in OSPatrick Rudolph
Chip sections must be covered by a PCI device. Fixes chip_ops not being executed and TPM shows up in OS. Change-Id: Id0ecd2f2f3e303f2228743369a8025b327bee61d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/26750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06mb/google/octopus: Fix invalid IOSSTATE settings for 1.8V pinsShamile Khan
When the normal termination is None, the standby termination is none also as per Doc# 572688. So when termination is only needed in standby, use the IOSSTATE setting that drives low/high via the Tx mode instead. Also disabled Speaker in Standby state to save power. BUG=b:79874891, b:79982669 BRANCH=None TEST=Compiled and flashed image on Bip. Checked that suspend_resume cycles pass. Checked that bluetooth is functional on resume. On Yorp, checked that speaker is functional after a suspend/resume cycle. Change-Id: I6a3852548f944176a80feb32e9885b03b8af25db Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/26762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06mb/google/poppy/variants/atlas: update HP IRQ pin's pad configSathyanarayana Nujella
Issue observed on the board is: too many jack interrupts. cat /proc/interrupts | grep da7219 58: 84292 15709 0 0 IO-APIC 58-fasteoi da7219-aad Updated pad configuration for Jack IRQ pin to fix the issue. BUG=b:109655907 TEST=Jack insertion & removal detection is working. Change-Id: I41ef9d40325677b01ca94ec3215e7feded76dcc3 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06mb/google/poppy/variants/nami: Add delay to enable_gpio during Elan power onShelley Chen
During measurement of signals during Elan touchscreen power on, saw that the enable_gpio delay was not sufficient as there is a +1.5 ms delay during power on. Adding more delay to take this into account. BUG=b:78311818 BRANCH=None TEST=probe power on signals to ensure meet timing requirements Change-Id: Id661a202188a97aef97514ebecd0be6fc022d21e Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06mb/google/poppy/variants/nami: Fix Elan touchscreen power off sequenceShelley Chen
Power off does not seem to use the ACPI _OFF function, but rather the smihandler. Creating variant_smi_sleep function for nami to handle the power off sequence during reboot/power off. BUG=b:78311818 BRANCH=None TEST=Run "poweroff" command from AP console with SMI_DEBUG enabled Make sure delays are consistent with spec Change-Id: Ifeea545fe268be249793b3e508c51f5e4c1a3460 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/26724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06arch/x86: Drop leftover ROMCC supportKyösti Mälkki
Remove the last bits of building romstage with romcc. Change-Id: I70bb1ed23a5aeb87bf7641e0b0bd604a4e622e61 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06src/driver/i2c/{generic,hid,tpm,max}: Update device name based on devicetree.cbNaresh G Solanki
Name i2c device structure based on that in devicetree.cb Now log looks like: I2C: 01:0a (WCOM Touchscreen) I2C: 03:13 (Realtek RT5663) I2C: 03:39 (SSM4567 Right Speaker Amp) I2C: 03:3a (SSM4567 Left Speaker Amp) BUG=None BRANCH=None TEST=Build & boot Soraka Change-Id: I5dbb66ab705cd8601b8b1dc94bc6ee9f181b7be2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/26830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06cpu/intel/model_{6xx,f2x,f3x,f4x}: Remove unneeded includeElyes HAOUAS
Change-Id: I7d5843aada364b557e0618268ad48c650aa54d1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-06soc/intel/common/block: Move i2c common functions into block/i2cSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/i2c. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Move gspi common functions into block/gspiSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/gspi. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNLSubrata Banik
This patch creates a glue layer between SOC and common block IPs in terms of PCH. All common IP blocks now can be selected based on SOC_INTEL_COMMON_PCH_BASE config option. BUG=none BRANCH=b:78109109 TEST=Build and boot Cannonlake RVP and EVE. Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/pch: Make infrastructure ready for pch common codeSubrata Banik
This patch is intended to make Intel common PCH code based on Gen-6 Sunrisepoint PCH (SPT). All common PCH code blocks between Gen-6 till latest-PCH should be part of soc/intel/common/pch/ directory. A SoC Kconfig might select this option to include base PCH package while building new SOC block. Currently majority of common IP code blocks are part of soc/intel/common/block/ and SoC Kconfig just select those Kconfig option. Now addition to that SoC might only selects required base PCH block to include those common IP block selections. BUG=none BRANCH=b:78109109 TEST=soc code can select PCH config option Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06mb/google/octopus: Enable wake-over-wifi for octopus variantsFurquan Shaikh
This change enables wake-over-wifi functionality for all octopus variants by making the following changeS: 1. Configure GPIO_119 as SCI active-low 2. Update GPE0_DW1 to include the group that GPIO_119 falls under 3. Add wake property to wifi device BUG=b:77224247 TEST=Verified that wake-over-wifi works on yorp. Change-Id: Ibae199c43e4d96da4c2f68f71a849c2f23d3e7b9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06soc/intel/apollolake: Add missing entries to pmc_to_gpio_route for GLKFurquan Shaikh
This change adds missing entries in PMC to GPIO route mapping for GLK. BUG=b:77224247 Change-Id: I66cadaa23b8bd4518a199733c8fba81168e60323 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-06soc/intel/apollolake: Fix macro name for GPIO_GPE_NW group 2Furquan Shaikh
Bit 63 is part of GPIO_GPE_NW group 1 and group 2 starts from bit 64. This change corrects macro name to GPIO_GPE_NW_95_64 to reflect this. BUG=b:77224247 Change-Id: Ib94617ad102eea5084281f0dda3475e33d3a7833 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Get rid of nextdev member in struct deviceFurquan Shaikh
Now that chips and devices are treated differently and the device tree actually contains only devices, next and nextdev are exactly the same for all devices in the tree. This change gets rid of nextdev pointer and updates all uses of nextdev to next. BUG=b:80081934 TEST=Verified that static.c generated for all boards built by abuild is same with and without this change. Change-Id: Ie50b3d769a78fe0beddba2e5551441b43cb212a2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Get rid of struct headerFurquan Shaikh
Now that chips and devices are treated differently in sconfig, this change gets rid of struct header and add_header function which were responsible for maintaining list of headers that need to be added to static.c. Instead, struct chip is re-factored into struct chip and struct chip_instance, where chip is a list of unique chips required by the mainboard whereas chip_instance is an instance of the chip. One chip can have multiple instances dependending upon the devices in the system. Also, struct device is updated to hold a pointer to chip instance instead of the chip structure. This unique list of chips is then used to add appropriate headers to static.c BUG=b:80081934 TEST=Verified using abuild that all boards compile successfully. Change-Id: I6fccdf7c361b4f55a831195adcda9b21932755aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26739 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05util/sconfig: Add helper function for allocating memoryFurquan Shaikh
Add a helper function s_alloc (sconfig alloc) that allocates memory using calloc to get 0 initialized memory and checks to ensure it is not NULL. BUG=b:80081934 Change-Id: I56a70cf4865c50ed238226ace86e867bb1ec53db Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Get rid of bus pointer in device structureFurquan Shaikh
The only reason bus pointer existed in device structure in sconfig was to allow a node to point to the parent which could be a chip and bus which is the true parent in device tree hierarchy. Now that chip is no longer a device, there is no need for separate bus and parent pointers. This change gets rid of the redundant bus pointer in struct device in sconfig. BUG=b:80081934 TEST=Verified that static.c generated for all boards built by abuild is same with and without this change. Change-Id: I21f8fe1545a9ed53d66d6d4462df4a5d63023844 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Re-factor emitting of headers to static.cFurquan Shaikh
This change removes call to add_header from parsing functions and moves it to a local function within main.c. It also adds a new function emit_headers that is responsible for creating the linked list for chip headers and emitting those to static.c BUG=b:80081934 TEST=Verified that static.c for all files compiled using abuild is the same with and without this change. Change-Id: I24d526e81323115d3cc927242a4b9e49414afbe0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05util/sconfig: Re-factor sconfig to not assume chip as deviceFurquan Shaikh
This change adds a new structure "struct chip" to identify elements of type chip rather than re-using the structure for device. Until now chip was treated as a device while generating the parse tree and then device tree postprocessing skipped over all the chip entries in children and sibling pointers of device nodes. With this change, the device tree will only contain struct device in the parsed tree. It helps by avoiding unnecessary pointers to chip structure as children or next_sibling and then skipping those elements in post processing. Every device can then hold a pointer to its chip. When generating static.c, chip structure is emitted before device structure to ensure that the device structure has chip within its scope. Externally, the only visible change in static.c should be the order in which chip/device elements are emitted i.e. previously all chips under a particular device were emitted to static.c and then the devices using those chips. Now, all chips are emitted before all the devices in static.c BUG=b:80081934 TEST=Verified that abuild is successful for all boards. Also, verified that static.c generated for eve, kahlee, scarlet, asrock imb_a180 is unchanged from before in node definitions. Change-Id: I255092f527c8eecb144385eb681df20e54caf8f5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/26720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05mb/google/poppy/variants/nami: Disable rear camera/DMIC for vayne skuid 3A67Van Chen
Since Vayne added one more skuid 3A67, we need to disable rear camera/DMIC for vayne skuid 3A67. BUG=b:75073617 BRANCH=master TEST=Verify if only front camera/DMIC shown on Vayne Change-Id: I9131b4c41bf189829be4e7e6bfaf4a96765cfa15 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26855 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05soc/intel/{apollolake, geminilake}: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization for APL and GLK. Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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