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2015-04-17pistachio: report UART register widthVadim Bendebury
Pistachio UART closely matches 8250, the only difference is that its register file is mapped to a 32 bit bus. Provide a function to report register with so that the Coreboot table entry gets correct value. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: Icd72b115b4f339800d6c8b210a6617398232f806 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e1dc4156949b20efafbca2c19ff424436a400087 Original-Change-Id: Icafb014af338e05bbf1044b791683733685ffab3 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240028 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9740 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17libpayload: read register width from coreboot tableVadim Bendebury
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I05891a9471a5369d3bfafe90cd0c9b0a7e5a667e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17uart: pass register width in the coreboot tableVadim Bendebury
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I30b742146069450941164afb04641b967a214d6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9738 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-17libpayload: sync arch/arm/cache.c with corebootDavid Hendricks
There was a recent patch by Deepa Dinamani applied to coreboot's cache.c which fixed a bug that occurred when icache is on but dcache is off ("arch: armv7: Fix cache sync instructions."). Although this bug is not likely to be encountered by the time libpayload is run, it's worth applying it to keep things in sync. BUG=none BRANCH=none TEST=n/a since we have icache and dcache enabled on all ARM platforms when libpayload is run. Change-Id: I83d9f96acb702975585e5d47c90e2ddaca488f6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31f985b58ac9227684fbe27481129ba01fd3ab8a Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I4ab0d97ef3a97dcd0fa96e10273c3b32486e0b40 Original-Reviewed-on: https://chromium-review.googlesource.com/243276 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9737 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17blaze: add new Hynix 2GB BCTNeil Chen
- Hynix H5TC4G63CFR-PBA, ramcode = 5 BUG=chrome-os-partner:34695 TEST=emerged coreboot, booted successfully into kernel. Change-Id: I53f9ebd9c38c645d1eb8b685d39e8beb55bd3c6a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ee6fdcc28402fe324d08b713498488d863d1d30f Original-Change-Id: I829d4e1f992eadd445c313729eb4bca5ce602f53 Original-Reviewed-on: https://chromium-review.googlesource.com/245947 Original-Reviewed-by: Neil Chen <neilc%nvidia.com@gtempaccount.com> Original-Tested-by: Neil Chen <neilc%nvidia.com@gtempaccount.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: Neil Chen <neilc%nvidia.com@gtempaccount.com> Reviewed-on: http://review.coreboot.org/9736 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17exynos: return correct value when init_default_cbfs_media failsDaisuke Nojiri
BUG=none BRANCH=ToT TEST=Built daisy. Change-Id: I64033f8e7beb247b2b8bd66e58de6c5e263ee634 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1ff51e887a07a0f2426e5111df683ce2a9d4097d Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Id6e006be1db08933dc97b5e797a85f3cbf9f6486 Original-Reviewed-on: https://chromium-review.googlesource.com/232513 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9735 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: detect sdram size at runtimehuang lin
we use Kconfig define sdram size before, but there may use different sdram size in the same overlay, so we must detect sdram size at runtime now. If we use 4G byte sdram, we can use[0x00000000:0xff000000], since the [0xff000000:0xffffffff] is the register space. BUG=chrome-os-partner:35521 TEST=Boot from mighty BRANCH=None Change-Id: I7a167c268483743c3eaed8b71c7ec545a688270c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ad4f27dd08c467888eee87e3d9c4ab3077751898 Original-Change-Id: Ib32aed50c9cae6db495ff3bab28266de91f3e73b Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243139 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9734 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17veyron: move setup_chromeos_gpios() prototype to board.hJulius Werner
I always had that TODO comment in there but I had already forgotten what I even meant by it. It's really just a simple cleanup... this function is (currently) veyron-specific and doesn't belong in common code. BRANCH=veyron BUG=None TEST=Booted Jerry. Change-Id: Iccd6130c90e67b8ee905e188857c99deda966f14 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d188398704575ad2fedc2a715e609521da2332b0 Original-Change-Id: I6ce701a15a6542a615d3d81f70aa71662567d4fa Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241190 Reviewed-on: http://review.coreboot.org/9733 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: Handle framebuffer through memlayout, not the resource systemJulius Werner
We've traditionally tucked the framebuffer at the end of memory (above CBMEM) on ARM and declared it reserved through coreboot's resource allocator. This causes depthcharge to mark this area as reserved in the kernel's device tree, which may be necessary to avoid display corruption on handoff but also wastes space that the OS could use instead. Since rk3288 boards now have proper display shutdown code in depthcharge, keeping the framebuffer memory reserved across the handoff (and thus throughout the lifetime of the system) should no longer be necessary. For now let's just switch the rk3288 implementation to define it through memlayout instead, which is not communicated through the coreboot tables and will get treated as normal memory by depthcharge. Note that this causes it to get wiped in developer/recovery mode, which should not be a problem because that is done in response to VbInit() (long before any images are drawn) and 0 is the default value for a corebootfb anyway (a black pixel). Eventually, we might want to think about adding more memory types to coreboot's resource system (e.g. "reserved until kernel handoff", or something specifically for the frame buffer) to model this situation better, and maybe merge it with memlayout somehow. CQ-DEPEND=CL:239470 BRANCH=veyron BUG=chrome-os-partner:34713 TEST=Booted Jerry, noticed that 'free' now displays 0x7f000 more bytes than before (curiously not 0x80000 bytes, I guess there's some alignment waste in the kernel somewhere). Made sure the memory map output from coreboot looks as expected, there's no visible display corruption in developer/recovery mode and the 'cbmem' utility still works. Change-Id: I12b7bfc1b7525f5a08cb7c64f0ff1b174df252d4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10afdba54dd5d680acec9cb3fe5b9234e33ca5a2 Original-Change-Id: I1950407d3b734e2845ef31bcef7bc59b96c2ea03 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240819 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9732 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17arch/mips: Fix bug when performing cache operationsIonela Voinescu
Each type of cache might have different cache line size. Call the proper get_<*>cache_line function for each cache type. Fixes problem with get_L2cache_line which previously targeted L3 cache line in the config register, instead of L2 cache. TODO: add support for tertiary caches and have cache operations be called per CPU, not per architecture. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; worked as expected; BRANCH=none Change-Id: I7de946cbd6bac716e99fe07cb0deb5aa76c84171 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 62e2803c6f2a3ad02dc88f50a4ae2ea00487e3f4 Original-Change-Id: I03071f24aacac1805cfd89e4f44b14ed1c1e984e Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241853 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17spi: Add function to read flash status registerDuncan Laurie
Add a function that allows reading of the status register from the SPI chip. This can be used to determine whether write protection is enabled on the chip. BUG=chrome-os-partner:35209 BRANCH=haswell TEST=build and boot on peppy Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/240702 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit c58f17689162b291a7cdb57649a237de21b73545) Change-Id: Ib7fead2cc4ea4339ece322dd18403362c9c79c7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fbdf0d72892eef4a742a418a347ecf650c01ea5 Original-Change-Id: I2541b22c51e43f7b7542ee0f48618cf411976a98 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241128 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/9730 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17ARM: Remove -mno-unaligned-accessJulius Werner
We've decided that it is generally okay for coreboot to expect unaligned accesses to work. Trying to find all instances of unaligned access opportunities and working around them in software would be an unsustainable whack-a-mole contest. Instead, architectures and boards need to make sure they conform to this, which on ARM and ARM64 requires setting up paging early in the bootblock. Other architectures (x86, ARM64, MIPS) already generate code in this manner. ARM still had an -mno-unaligned-access flag hanging around that has been copied so many times its initial origin was lost in time (probably U-Boot). Let's remove it for consistency between architectures and to improve code generation. BRANCH=veyron BUG=None TEST=Booted Jerry and Blaze. Looked at the disassembly for timestamp_sync() and confirmed that it only gives you half as much eye cancer as before (GCC still somehow insists on byte accesses when zeroing fields which is very odd, but at least that terrible AND/OR mess is gone). Measured a boot time increase of about 11ms on Jerry (mostly faster timestamp and CBFS accesses). Could not test Storm because despite our claimed abundance of test devices, every time I get one of them it magically disappears again in less than a week. Change-Id: I8fc08cc7ce4471651a51ee795269909ef69277c8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07591fadb89bd127fe065abf0b9ba3facecf1aeb Original-Change-Id: I1d046e05bb11822b86e467eafb6aa92e8fbce774 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/241732 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9728 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-04-17libpayload: Take flash parameters from corebootDan Ehrenberg
A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: I92b7ff0ce66af8d096ec09a4c900829ef6c867e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17drivers/spi: Pass flash parameters from coreboot to payloadDan Ehrenberg
A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9726 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17Add delay before reading GPIOs in gpio_base2_value()David Hendricks
This adds a 10us delay in between (re-)configuring and reading GPIOs in gpio_base2_value() to give the values stored some time to update. As far as I know this hasn't bitten us since the function was added, but adding a short delay here seems like the right thing to do. BUG=none BRANCH=none TEST=built and booted on Brain Change-Id: I869cf375680435ad87729f93d29a623bdf09dfbc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2484900fc9ceba87220a293de8ef20c3b9b20cfd Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I79616a09d8d2ce4e416ffc94e35798dd25a6250d Original-Reviewed-on: https://chromium-review.googlesource.com/240854 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9725 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17urara: add board id information for urara boardIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio FPGA; works as expected. BRANCH=none Change-Id: If4493fcb37cf649fb0a56d594ac58556da3aa571 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f6764396be1ab17875d9c73624cce48dc6790e6 Original-Change-Id: I925ebd6ea4fc30c1c1d91559f96eaad62d06aba8 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/239490 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9724 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17as3277: Fix month-off-by-one error for RTC driverJulius Werner
The AS3277 RTC code seems to closely follow the corresponding Linux driver. Unfortunately, while coreboot (and even other parts of Linux, like mktime()) directly follows the standard IBM PC RTC time representation (except for the BCD part), Linux' struct rtc_time decided to use 0-based (instead of 1-based) months instead. This patch removes the faulty month offset that was copied into our driver so that we will generate correct timestamps again. BRANCH=nyan BUG=chrome-os-partner:34108 TEST=firmware_EventLog (pre-release version) gets further than before (and then craps up on unrelated problems with suspend/resume events). Change-Id: Ica221a8bcfd7c1c6cd7ba382d760b586d511e3a3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b55c3f5bbecc776a71338256b910aecccac1e04 Original-Change-Id: I163fa4778ec534cd9e6f92a6b6dc55e9871a6a82 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238122 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9723 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17bg4cd: define custom romstage entryDaisuke Nojiri
this change defines a custom romstage entry for bg4cd. the entry code stalls subcores, sets up the stack, and clears the bss before jumping to main. BUG=none BRANCH=tot TEST=built all current boards. booted cosmos p1 Change-Id: Idde43f94555bec7804a16928c58ce673956a39e5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a35e12eb29b351cc0baaea24344f00d2ba905f6 Original-Change-Id: I9172e873a43847f3ea82cd1d9fd0841f0db83994 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238022 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9722 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17arm: allow custom stage entry codeDaisuke Nojiri
this change defines stage_entry as a weak symbol so that a board can implement custom stage entry code. BUG=none BRANCH=tot TEST=built all current boards. booted cosmos p1. Change-Id: If8f6945ecdc5047558bb6359aa997867e36f33b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 86d5008981d0b01652907baab47a476d784a2ceb Original-Change-Id: Ib43158c4013e6393d86a9aef37cf444a48b9fc79 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238021 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9721 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17rk3288: Add a config variable hack to skip display initDavid Hendricks
The current display init code causes Brain to crash when trying to allocate resources. This just avoids doing display init if a config variable is set. Once code has been implemented to properly setup different types of displays we can get rid of this hack. BUG=none BRANCH=none TEST=built and booted (to depthcharge) on Brain, compiled for pinky with FEATURES=noclean and ensured config variable is 0 Change-Id: I9a7266c6bff5b7a6eb05b2b21fb65797bee392d6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 804632ca67eaaf4174ca597d83b8923cb9abd1b7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I04c9e8181c58fa0608fd20776fa8c4798a023474 Original-Reviewed-on: https://chromium-review.googlesource.com/235922 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9720 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-17veyron: Activate Winbond SPI driverJulius Werner
This patch activates the chip driver for Winbond SPI flash (which, incidentally, looks 99.9% the same as the Gigadevice driver but still requires some extra 500+ bytes of object code... there's definitely room for improvement here). Shuffle around rk3288 memlayout to make a little more room in the bootblock. BRANCH=veyron BUG=chrome-os-partner:34176 TEST=Booted Pinky. Checked bootblock and verstage memsz of final binary and noticed that both only have less than 500 bytes left against their memlayout boundary. The next piece of code we add will cause some serious headaches... Change-Id: I97ea6ac334104e4219e310afc557c164b2ff19d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8769e5a34ad3cd417132646fbb58ff51c29fb640 Original-Change-Id: Id2f1204c30aa28251cf85cb80d7ca44947388dba Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236977 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9719 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15rk3288: support edp HPD functionhuang lin
we use the delay 200ms to meet the edp power timing request before, it waste time, so we use the HPD function to detect the edp panel now. In previous version, the hardware may not support the edp HPD function, so in the code it will spend 200ms to detect hpd single, if it don't get the hpd single, it will contiue the edp initialization process, to compatible all of the hardware version. BUG=chrome-os-partner:35623 TEST=Boot from Mighty, and display normal BRANCH=None Change-Id: I82c6a80e37fa42eef3521e6ebbf190d7e80fcece Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 7a5343eb9af12cae9a15284217762a91ae24bac6 Original-Change-Id: I21c0ef6ce4643e90a192d8b86659264895b5fda9 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242792 Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: http://review.coreboot.org/9659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-15rk3288: meet the backlight power timing requesthuang lin
backlight timing: LED_VCC->LED_PWM->LED_EN, we modify the code to meet the timing. BUG=chrome-os-partner:36201 TEST=Boot from jerry, and scope the backlight timing BRANCH=None Change-Id: I6bfa6af176400086e4af0112a63127c1152ca70e Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 52ac0b2944cea7dc860bfea12fe44851436bb7f7 Original-Change-Id: I6c53a822410ad706383c6d9fa2b5f0437775f710 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/244639 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-15veyron_rialto: Change recovery GPIO to PUSH_KEY.Hung-Te Lin
The recovery button on Rialto should be GPIO 255, the LED Push Key. Note we want to keep the recovery button on servo functional because many protos are not assembled and developers can't "push" the push key. The GPIO passed to payloads (and kernel) is only mapped to Push Key. BUG=none TEST=emerge-veyron_rialto coreboot chromeos-bootimage BRANCH=veyron_rialto Change-Id: I66f94cf232caa53a3b28db517620e4b6e9b9af0e Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 66ee55f6312efaeb337eb2881cd5eff5365b4105 Original-Change-Id: I0a7ebeed6506fbd938084c9a078a7cf1c7b914b9 Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/244515 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-15veyron_rialto: Fix boot failure in romstage.Hung-Te Lin
The FMAP for Rialto has no ecrwhash and would cause verstage to incorrectly load ramstage (instead of romstage) when looking for subsection inside RW blob. We have to override the index of stages to boot correctly. BRANCH=veyron_rialto BUG=none TEST=emerge-veyron_rialto coreboot chromeos-bootimage Boots successfully on Rialto boards. Change-Id: I031703d97a68e42dc17630ab5df85f8cba47e5e5 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 24ba4b16b4a2fe5469296f8d40286ed926cefc3c Original-Change-Id: I637ea23e1e8265781e52367d1306dbf854c2ccad Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/244577 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9656 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-15rk3288: set the rk808 BUCK default inductor current to max valuehuang lin
Our use of the bucks may exceed their default maximum inductor current. Just set it to the highest possible value for every buck we configure to avoid problems... the kernel can later fine-tune the values further if needed. (Also some slight grammar updates while I'm in there.) BRANCH=veyron TEST=Build and Boot on Jerry BUG=None Change-Id: If8258cf4feefe191604365405bff1f20c8ab8746 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 065a163bb902b8c96d05bfef6ed4885aa20f31cc Original-Change-Id: I3801cabeb93d7bf7ecc02db0e69d4932c9394db9 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/242785 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: http://review.coreboot.org/9655 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-15rk3288: Fix failing LPDDR3 reboot testjinkun.hong
tMRD request 10nCK in LPDDR3, we set the DDR_PCTL_TMRD BIT0~BIT2 to generate this signal, but the max value we can set is 7, so the standard can not be met. So, now we send the Mode Register Set command manually, and hence we can add the delay manually. BUG=chrome-os-partner:34608 TEST=loop reboot BRANCH=veyron Change-Id: Id974ab935c2df6ea35dcdd240378ffc68de0204d Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: b60a4de6ff3ad3720c2c06ed7de03ed942360e6c Original-Change-Id: I0d29ea9cd82ef018e835ae53090a47d0299ef61d Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242176 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9654 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-15rk3288: Fix failing DDR3 reboot testjinkun.hong
We want a reset signal to last 200us. The length of a reset signal is represented by BIT0~BIT16 in DDR_PUBL_PTR2. When DDR memory runs at 667MHz, the calculated value for the reset signal is 0x20850, which is bigger than the maximum value that can be described with 17 bits (0x1ffff). As a result, the memory controller only sees 0x850, which generates a 3.5us reset cycle instead, which violates the standard and negatively impacts memory stability. So instead, we now set it to the maximum value (0x1ffff) to prevent this overflow, resulting in a reset signal of 196us for 667MHz DDR memory. BUG=chrome-os-partner:34875 TEST=loop reboot BRANCH=veyron Change-Id: Ia01f8a0414b49fa3ecf4d543cfa1822e29ee4cc4 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 767a4a3cb8dff47cb15064d335b78ffa5815914d Original-Change-Id: I9b410e1605c87f12a5ca96ead12f8527ca4f417f Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242175 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-15google/veyron_*: Remove unused sdram-ddr-hynix-2GB.inchuang lin
BRANCH=None TEST=Build speedy, pinky, mighty BUG=None Change-Id: If561872274bcdc2652c2bfe80cf5bd0501ad6b64 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e6be62b4e64b13e285eb0480fdc65d814c6dadc0 Original-Change-Id: I7c97d54f3a4c94f7e23d3e85b808cd64b1cacec7 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241939 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9651 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-15Jerry: add SAMSUNG K4B4G1646Q-HYK0 ddr3 sdram supportPaul Ma
K4B4G1646Q-HYK0 is a variant of K4B4G1646D-BYK0 with a different physical package and the same config parameters. BRANCH=none BUG=chrome-os-partner:34940 TEST=boot on Jerry board with K4B4G1646Q-HYK0 Change-Id: I485eede309850ef6b3a52e2a548b6b032d281293 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e925d784e1ebe444f5a5bcab47c8a661b0c6c527 Original-Change-Id: I31bcb348a45ff76e8e08127063bd0d04443ccb79 Original-Signed-off-by: Paul Ma <magf@bitland.com.cn> Original-Reviewed-on: https://chromium-review.googlesource.com/241787 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Trybot-Ready: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9650 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-15veyron: support H5TC4G63CFR sdram in jerryhuang lin
BRANCH=None TEST=Boot and run jerry rev2 board BUG=None Change-Id: I95ec99e444c9cff3008bac5d1e6c3365fc2229a0 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: f9075e6172d1ae503dc26bac8f1057455dc93c39 Original-Change-Id: Ice60a4576c9eb386599a545c1b8d470e8a2eed68 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/236500 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Paul Ma <magf@bitland.com.cn> Original-Tested-by: Paul Ma <magf@bitland.com.cn> Reviewed-on: http://review.coreboot.org/9635 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-04-15veyron: Add veyron_rialto boardjinkun.hong
Derived from of veyron_brain with new memory configuration. BUG=chrome-os-partner:35072 TEST=built and boot on rialto-rev0 boards. BRANCH=veyron Change-Id: I2c6f74d231e39de76ef2399fdb20efae977b34fa Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 17d66e5f58562427badd6973ebb053f58573c040 Original-Change-Id: I8626ff5da8098ca120481b8cda0c6703f806711e Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238946 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Trybot-Ready: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-15ipq806x: load and start RPMVadim Bendebury
This patch finds the RPM image in the CBFS, loads it as defined by the MBN header and signals to the RPM processor where the image is located and waits for confirmation of the RPM starting. The interactions with the RPM processor are copied as is from the vendor provided sample code. Debug messages added to help identify problems with loading the blobs, should they ever happen. BRANCH=storm BUG=chrome-os-partner:34161 TEST=ramstage reports both TZBSP and RPM starting. Change-Id: I81e86684f9d1b614f2059ee82c6561f9484605de Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bbf2eda04a6e72b4f7b780f493b5a1cea0abfeb7 Original-Change-Id: Ic10af0744574c0eca9b5ab7567808c1b8d7fe0c2 Original-Signed-off-by: Vikas Das <vdas@codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236661 Original-Reviewed-by: Varadarajan Narayanan <varada@qti.qualcomm.com> Reviewed-on: http://review.coreboot.org/9692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15storm: Add watchdog reset api.Deepa Dinamani
Use the apps processor watchdog reset to do a hard reset. The watchdog reset drives the RESETOUT on the chip. Modify register address definitions to be able to use pointers and pointer arithmetics. BRANCH=storm BUG=chrome-os-partner:34334 TEST=the chip resets and the control returns to start of SBL. Change-Id: Ib5772ab152b27058fde1be9de2d2ac26bfe00ca4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d50413cb614ef05ada93be1252fe5ef617a94d91 Original-Change-Id: I9b249d057b473429335587f7241ca462b4a6a8b7 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/236141 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Reviewed-on: http://review.coreboot.org/9691 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15ipq806x: Load TZBSP blob from coreboot ramstageVikas Das
Read the TZBSP blob from CBFS and run it. A side effect of the blob execution is switching the processor into User mode. Starting TZBSP requires processor running in Supervisor mode, TZBSP code is compiled for ARM. Coreboot is executing in System mode and is compiled for Thumb. An assembler wrapper switches the execution mode and interfaces between Thumb and ARM modes. BUG=chrome-os-partner:34161 BRANCH=Storm TEST=manual With the preceeding patches the system successfully loads to depthcharge in recovery mode. Change-Id: I812b5cef95ba5562a005e005162d6391e502ecf8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7065cf3d17964a1d9038ec8906b469a08a79c6e2 Original-Change-Id: Ib14dbcbcbe489b595f4247d489d50f76a0e65948 Original-Signed-off-by: Varadarajan Narayanan <varada@qti.qualcomm.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9690 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15storm: adjust rombase startup to vboot2Vadim Bendebury
Memory needs to be initialized before rombase proceeds. BRANCH=storm BUG=chrome-os-partner:34161 TEST=boots into depthcharge Change-Id: Id16b17685ff15c2a69d630eb8042e15549ae8b21 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e8aeb38206b806d5656052d0f210faa769e28b8 Original-Change-Id: I0616c7dc7f08332ac0d96d4baf2618b067606fdf Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234544 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9689 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15storm: use different CBFS caches before and after DRAM is availableVadim Bendebury
Booting depthcharge requires much larger CBFS cache, but by the time depthcharge is being booted DRAM is already initialized. Use different memory spaces for CBFS cache before and after DRAM is available. Also, make sure that CBMEM uses memory below CBFS cache in DRAM. BRANCH=storm BUG=chrome-os-partner:34161 TEST=with this change on Storm ramstage finds and boots depthcharge in recovery mode Change-Id: Icd1bbf4bcc5f9d92b2653b5a8891409105a25353 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e1e0b029b7fb09b84784373150cc4ce9eea7b3f5 Original-Change-Id: I33fd97806b2db6fab2adc44b67e5f54258642967 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234543 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9688 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15storm: configure/enable vboot2 supportVadim Bendebury
Select vboot NV driver. BRANCH=stotm BUG=chrome-os-partner:34161 TEST=with caches disabled Storm starts up and initializes DRAM successfully. Change-Id: Ib2e509e0c32a7a836a0fc6c0d5d05cc9bf68cbf6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a4cf8b26be99b04774ee3d1eb4b28039813e020 Original-Change-Id: Ie220aade420e1e54e2fa46295d03af494466ab43 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234645 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9687 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15ipq8064: add DRAM initialization codeVadim Bendebury
Read two blobs from CBFS: cdt.mbn (memory configuration descriptor) and ddr.mbn (actual memory initialization code). Pointer to CDT which starts right above the MBN header is passed to the memory initialization routine. Zero return value means memory initialization succeeded. BRANCH=storm BUG=chrome-os-partner:34161 TEST=with upcoming patches memory initialization succeeds. Change-Id: Ia0903dc4446c03f7f0dc3f4cc3a34e90a8064afc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1d79dadd7d47dd6d01e031bc77810c9e85dd854b Original-Change-Id: Ib5a7e4fe0eb24a7bd090ec3553c57cd1b7e41512 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234644 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9686 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15ipq806x: add i2c driverVadim Bendebury
this change ports i2c and other relevant drivers from depthcharge for ipq806x. BUG=chrome-os-partner:33647 BRANCH=ToT TEST=Booted storm using vboot2 Change-Id: I3d9a431aa8adb9b91dbccdf031647dfadbafc24c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a0c615d0a49fd9c0ffa231353800882fff6ab90b Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Id7cc3932ed4ae54f46336aaebde35e84125ebebd Original-Reviewed-on: https://chromium-review.googlesource.com/229428 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9685 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15google/storm: prepare enabling vboot2Vadim Bendebury
This change sets up the list of source files for vboot2's verstage without enabling it. BRANCH=storm BUG=chrome-os-partner:34161 TEST=not much testing yet, just successful compilation. Change-Id: I4052c20795459bf0e057c0f0952226ea4a8c89f1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 48847ab8acfbe4b33d61d3d012c72c025cd8f364 Original-Change-Id: I1d7944e681f8a4b113a90ac028a0faba4423be89 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234643 Reviewed-on: http://review.coreboot.org/9684 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15ipq806x: modify imem layoutDeepa Dinamani
With introduction of uber-sbl SRAM usage pattern is changing, this introduces the new memory layout. This patch overlays DDR initialization code with uber-sbl, as uber-sbl goes out of scope as soon as bootblock starts. A 4K block at offset 0x3f000 added in the comments, this is a shared structure used by different QCA modules. This suggested layout is not final, but will allow to move closer to the production image. BRANCH=storm BUG=chrome-os-partner:34161 TEST=with other patches applied Storm boots all the way to rombase and initializes DRAM. Change-Id: I46af81b39b09935aa7fffdabda223e7e64c7a446 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a20c0570361038c0ae406dcb1f4bc657eea120f6 Original-Change-Id: I927f6ffc524fc8f0effd7b91d3f5d1e8d6be1530 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229023 Reviewed-on: http://review.coreboot.org/9683 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15soc/ipq806x: Disable LPAE mode.Deepa Dinamani
LPAE (large physical address extension) is not available on this SOC core, do not enable it. [pg: we already had this one, but somehow LPAE slipped in again] BUG=chrome-os-partner:27784 TEST=coreboot still comes up on AP148 Change-Id: Iaa80022c611f7377d8f4100487d32654150836d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e6e12c39efd54e4fcbd444134bf30e211948a71b Original-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198023 Original-Reviewed-by: deepa dinamani <deepad@quicinc.com> Reviewed-on: http://review.coreboot.org/9682 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15storm: add code for detecting rec/dev/write protect switches' statusDaisuke Nojiri
The gpio access code has been moved to a separate file to match other platforms. Accessor functions are added to read different switches state. They will be read by verstage, when it is enabled, and by ramstage, for passing the values to depthcharge. It is unfortunate that the gpio values are not being cached and can change by the time CBMEM table is filled, but we have to live with that for now. BUG=chrome-os-partner:33756,chrome-os-partner:34161 BRANCH=storm TEST=none yet. Change-Id: I229fed0e35d643912f929671d5fc25aee5d1d167 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e15aa281a1dbf2c463650b6c04991436022d8d4 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I940b54cd3cf046b94d57d59d370e634a70a8bbeb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229426 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9681 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15ipq806x: set architecture to ARMV7Vadim Bendebury
BUG=chrome-os-partner:33646 BRANCH=ToT TEST=Built storm. Change-Id: I4b2cb54369dee7e6e61c2173d2be0f50430123fb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0aab7fe31b78bae264cc2e6fa04fe7047315d08f Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ic509e1fd375a320b8e37a07a7f5b9a6fa211ace3 Original-Reviewed-on: https://chromium-review.googlesource.com/229427 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9680 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15broadwell: Fixes for _SWS supportDuncan Laurie
- These should be 64bit values so when they try to return -1 it is interpreted properly by the kernel. - The GPE value needs to be reset at the start so it does not return stale data from a previous resume. - If a GPE register is zero the value should only be updated if it has not yet found a set bit. BUG=chrome-os-partner:34532 BRANCH=samus,auron TEST=build and boot on samus, suspend/resume with various wake sources and ensure the reported _SWS values are correct in every case. Original-Change-Id: Ic6897f20ad2f321f3566694c032b75a3db120556 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/235012 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit be3c79b87b81563f744eb885708a52730debaccb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I801c6e4f90dde0f5f69685f987a9831ee5e99e4a Reviewed-on: http://review.coreboot.org/9699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15broadwell: Remove unused bootblock codeDuncan Laurie
This code that stores the initial timestamp is not being used, instead the timestamp is passed to romstage_main(). BUG=chrome-os-partner:28234 BRANCH=samus,auron TEST=build and boot on samus Original-Change-Id: I0e0fa1ba74ab93d4454fdfa12208e712d2ae913c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234402 Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 838112cf79e2b4d51e5dc87d5ac9cd7e03807f29) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8fd7ba72c14c1e39f7bfa3a1ae8d03289a2abf73 Reviewed-on: http://review.coreboot.org/9698 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15broadwell: Clean up ME device and add new ME10 flowDuncan Laurie
In order to avoid a 300ms timeout waiting for mbp_cleared flag to be set there is a new flow for the ME10 1.5MB firwmare that we can follow which will save significant boot time. This requires sending new commands that do not generate an ACK message, and ensuring an HMRFPO LOCK message is sent. In addition now that the delay is removed clean up the ME path to do the work in init() step and add a final() step that does the disabling of the PCI device. BUG=chrome-os-partner:30637,chrome-os-partner:34134 BRANCH=samus,auron TEST=build and boot on samus, measure ~300ms speedup in boot time Original-Change-Id: I753087ecd65f6ebed9f812318a359f893e01da9f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234400 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 25aff4b188dc94a99af30869a162e01e3fa8dee7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia35373548a902a718155a1a57057f55067d2f3ac Reviewed-on: http://review.coreboot.org/9697 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-15soc/baytrail: Use microcode from the blobs repositoryMarc Jones
Remove the blobs from the coreboot tree and get them from 3rdparty. Change-Id: I0798091530be9654d7e073839b4efeb3f9c0302c Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9694 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-04-15soc/broadwell: Use microcode from the blobs repositoryMarc Jones
Remove the blobs from the coreboot tree and get them from 3rdparty. Change-Id: I4938b5c47e6ae7059eda144b664aeafdd674f0fb Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9693 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-04 08:17:27 +0000