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2020-05-13soc/amd/picasso: Mark FCH MMIO addresses as non-postedRaul E Rangel
Immediately following FSP-S, update the data fabric routing registers to make the region between HPET and LAPIC as non-posted. If AGESA is modified to do this, we can delete data_fabric_util.c. If AGESA is modified to not program the registers, then we can simplify data_fabric_set_mmio_np(). BUG=b:147042464, b:156296146 TEST=boot trembyle Change-Id: Idbafaac158f5a4c533d2d88db79bb4d6244e5355 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41268 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Add data fabric pci_devsRaul E Rangel
The device ids are already defined in include/device/pci_ids.h as PCI_DEVICE_ID_AMD_FAM17H_DF*. BUG=b:147042464 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic68a1067e5976af972592d7352c40a5c66dbeb8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-13soc/amd/picasso: Add data fabric register definitionsRaul E Rangel
These are used to setup the data fabric. Definitions came from 55570-B1 Rev 3.14 - PPR for AMD Family 17h Model 18h BUG=b:147042464 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib51f6e2fd304da9948d6625608af71f25b974854 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41266 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Delete northbridgeMarshall Dawson
Family 17h devices are designed with a new internal architecture, frequently referred to as the data fabric. Although designed to behave somewhat like the older integrated northbridge designs, the D18Fx definitions are completely new. The previous northbridge.c was copied from stoneyridge which is completely different. Change-Id: Id70cbda99657249179fb8cf5e461dd6a37ec9153 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41265 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Extract reset flags from northbridge.hRaul E Rangel
These are not northbridge functions. BUG=b:147042464 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia9e7d4c7554788a9fdbfdb90e6ead60060cc4c30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41264 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Move ACP register to acp.hRaul E Rangel
This is a device specific register, not a northbridge register. BUG=b:147042464 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I97b63571e336f541dcb274e4c8c608f6fc59ff42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41263 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Move acpi_fill_mcfgRaul E Rangel
Move this with the other acpi functions. BUG=b:147042464 TEST=build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I24bd5c7d7c90968759ac745012e7bbc47f0ef6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41262 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/common/block/psp: Remove unused northbridge headerRaul E Rangel
BUG=b:147042464 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5df618f69a7dcca47b9733efb3699b37fd171e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41261 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13mb/google/volteer: Enable keyboard backlight featureAngel Pons
This enables the keyboard backlight feature in ACPI for volteer. BUG=b:156326050 TEST=Verified 'KBLT' shows up in the DSDT ACPI table. Change-Id: Id1b1bb059368b0cc36cb06e6cdb8b989060a1dde Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-13mb/google/dedede/variants/waddledoo: Modify ELAN touchscreen slave addressIan Feng
Modify ELAN EKTH6918 USI touchscreen slave address to 0x10. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I999967b0f37c82ff7811e3b6117baab795a11195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-13mb/google/octopus/variants/foob: Disable xHCI compliance modeTommie
When any USB image disk is connected to the DUT through HUAWEI/APPLE Dongle, press Ctrl + u on the dev screen, it cannot boot from USB. We found the SS hub cannot be enumerated. So disable xHCI compliance mode. BRANCH=octopus BUG=b:155347573 TEST=Confirm successful boot from USB Change-Id: Iea4a3df156da0627336f7d6c1e03837b6cf0e7f2 Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40905 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/common/block/spi: Include mmio.h in fch_spi_ctrl.cFurquan Shaikh
fch_spi_ctrl.c uses read*()/write*() functions which are declared in arch/mmio.h. This change includes the file arch/mmio.h in fch_spi_ctrl.c. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I6540004512af1f59f5fb300a3a4818b87ad94bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/41271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-13soc/amd/common/block/lpc: Add helper function lpc_early_init()Furquan Shaikh
This change adds a helper function lpc_early_init() which does the following things: 1. Enables LPC controller 2. Disables any LPC decodes (These can be set up later by SoC or mainboard as required). 3. Sets SPI base so that MMIO base for SPI and eSPI controllers is initialized. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I016f29339466c3fee92fe9b62a13d72297c29b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-12util/sconfig: Add LPC and ESPI busesRaul E Rangel
Picasso has an LPC and eSPI bridge on the same PCI DEVFN. They can both be active at the same time. This adds a way to specify which devices belong on which bus. i.e., device pci 14.3 on # - D14F3 bridge device espi 0 on chip ec/google/chromeec device pnp 0c09.0 on end end end device lpc 0 on end end BUG=b:154445472 TEST=Built trembyle and saw static.c contained the espi bus. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0c2f40813c05680f72e5f30cbb13617e8f994841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12soc/intel/skylake: Add ability to set root port ASPMWim Vervoorn
The default setting of the root port ASPM configuration can be overridden from the device tree by using a non zero value. BUG=N/A TEST=tested on facebook monolith Change-Id: I85c545d5eacb10f43b94228f1caf1163028645e0 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-05-12soc/intel/tigerlake: Correct IRQ interruptWonkyu Kim
Current Interrupt setting use 2nd parameters as device function number. - Correct as interrupt pin number according to _PRT package format. {Address, pin, Source, Source index} - Use irq number directly rather than irq definition as its number is not for PCI device. The issue found while enabling GBE and GBE interrupt is not working without this change. Reference - ACPI spec 6.2.13 _PRT - FSP reference code: https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/TGL.3163.01/ ClientOneSiliconPkg/IpBlock/Itss/LibraryPrivate/PeiItssPolicyLib/ PeiItssPolicyLibVer2.c - BIOS reference code: https://github.com/otcshare/CCG-TGL-Generic-Full/blob/master/ TigerLakeBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl TEST=boot to OS with GBE enabled and check GBE interrupt Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I8084b30c668c155ebabbee90b5f70054813b328e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12southbridge/intel/common: Add Process CallChristian Walter
Add functionality to use process call cycle. It can be used to write/read data to/from e.g. EEPROM attached to SMBus Controller via I2C. Tested on: * C246 Change-Id: Ifdac6cf70a4ce744601f5d152a83d2125ea88360 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39875 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12device/pci_device: Extract pci_domain_set_resources from SOCRaul E Rangel
pci_domain_set_resources is duplicated in all the SOCs. This change promotes the duplicated function. Picasso was adding it again in the northbridge patch. I decided to promote the function instead of duplicating it. BUG=b:147042464 TEST=Build and boot trembyle. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iba9661ac2c3a1803783d5aa32404143c9144aea5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12soc/intel/jasperlake: Remove deprecated UPDsRonak Kanabar
IedSize and EnableC6Dram are removed in JSL FSP v2114 so remove them from 'fsp_params.c'. BUG=155054804 BRANCH=None TEST=Build and boot JSLRVP Change-Id: I47bd3f87bdb59625098c0d734695f02d738f8bbd Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41239 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12soc/intel/jasperlake: Add SATA related UPDs configurationRonak Kanabar
This patch control SATA related UPDs based on the devicetree configuration as per each board's requirement. BUG=b:155595624 BRANCH=None TEST=Build, boot JSLRVP, Verified UPD values from FSP log Change-Id: I4f7e7508b8cd483508293ee3e7b760574d8f025f Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-12mb/intel/jasperlake_rvp: Remove SataEnable deviceetree configRonak Kanabar
SataEnable UPD override will be filled using devicetree pci device status check. Change-Id: I957dfcf139acd4f4dd5723bc1b010ec45ec91651 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41227 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12soc/amd/common/block/lpc: Configure io/mmio windows differently for LPC and eSPIFurquan Shaikh
This change updates lpc_enable_children_resources() to configure IO and MMIO resources differently depending upon whether the mainboard wants to setup decode windows for LPC or eSPI. BUG=b:154445472,b:153675913 Change-Id: Ie8803e934f39388aeb6e3cbd7157664cb357ab23 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-12soc/amd/common/block/lpc: Provide an option to use static eSPI BARFurquan Shaikh
This change provides a helper function espi_update_static_bar() that informs the eSPI common driver about the static BAR to use for eSPI controller instead of reading the SPIBASE. This is required to support the case of verstage running on PSP. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1f11bb2e29ea0acd71ba6984e42573cfe914e5d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-12soc/intel/tigerlake: Control SATA and DMI power optimizationShaunak Saha
FSP provides the UPD's for SATA and DMI power optimization. In this patch we are adding the soc's config support to set those power optimization bits in FSP. By default those optimizations are enabled. To disable those we need to set the DmiPwrOptimizeDisable and SataPwrOptimizeDisable to 1 in devicetree. BUG=b:151162424 BRANCH=None TEST=Build and boot volteer and TGL RVP. Change-Id: Iefc5e7e48d69dccae43dc595dff2f824e53f5749 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12soc/amd/common/block/lpc: Add helpers for managing eSPI decodeFurquan Shaikh
This change adds the following helper functions for eSPI decode: 1. espi_open_io_window() - Open generic IO window decoded by eSPI 2. espi_open_mmio_window() - Open generic MMIO window decoded by eSPI 3. espi_configure_decodes() - Configures standard and generic I/O windows using the espi configuration provided by mainboard in device tree. BUG=b:153675913,b:154445472 Change-Id: Idb49ef0477280eb46ecad65131d4cd7357618941 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41073 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12soc/amd/common/block: Add header file for eSPI register definitionsFurquan Shaikh
This change adds eSPI register definitions for I/O and MMIO decode using eSPI on AMD SoCs. Additionally, it also adds a macro to define the offset of ESPI MMIO base from SPI MMIO base. BUG=b:153675913 Change-Id: Ifb70ae0c63cc823334a1d851faf4dda6d1c1fc1a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12espi: Add support for debug helper to print slave capabilitiesFurquan Shaikh
This change adds a Kconfig option to enable eSPI debugging that pulls in a helper function to print slave capabilities. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I8ff250fe85dfa9370bf93ce3c7e2de5c069bf9e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12espi: Add some helper functions for espi capability checkFurquan Shaikh
This change adds helper functions that can be used to check support for different slave capabilities. BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic66b06f9efcafd0eda4c6029fa67489de76bbed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-12espi: Add definitions for eSPI VW index messsagesFurquan Shaikh
This change adds eSPI VW index message definitions as per per Enhanced Serial Peripheral Interface Base Specification (document # 327432-004 Revision 1.0) Chapter 5 "Transaction Layer". BUG=b:153675913 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I5c04d4de222e16d3b8e2a5fb2fc4107ea278a35b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41252 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12espi: Add definitions for eSPI slave registersFurquan Shaikh
This change adds eSPI slave register definitions as per Enhanced Serial Peripheral Interface Base Specification (document # 327432-004 Revision 1.0) Chapter 7 "Slave Registers". BUG=b:153675913 Change-Id: Icee53817476b7d50ff26e64bbc2c3f5afb19a7cd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-12soc/amd/common/block/lpc: Set LPC_IO_PORT_DECODE_ENABLE to 0 when disabling ↵Furquan Shaikh
decodes This change sets LPC_IO_PORT_DECODE_ENABLE to 0 as part of lpc_disable_decodes() to ensure that the I/O port decodes are also disabled. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1474f561997f2ee1231bd0fcaab4d4d4e98ff923 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12soc/amd/picasso: Use SPI configuration support from common block SPI driverFurquan Shaikh
This change switches to using the common block SPI driver for performing early SPI initialization and for re-configuring SPI speed and mode after FSP-S has run. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia3186ce59b66c2f44522a94fa52659b4942649b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-12soc/amd/picasso: Add support for using common SoC configurationFurquan Shaikh
This change adds support for using common SoC configuration by adding soc_amd_common_config to soc_amd_picasso_config and helper function to return pointer to the structure to amd common block code. Change-Id: I8bd4eac3b19c9ded2d9a3e95ac077f014730f9d1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12soc/amd/common/block/spi: Add support for common SPI configurationFurquan Shaikh
This change adds support for following SPI configuration functions to common block SPI driver and exposes them to be used by SoC: 1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM, enables prefetching, disables 4dw burst mode and sets SPI speed and mode. 2. fch_spi_config_modes(): This allows SoC to configure SPI speed and mode. It uses SPI settings from soc_amd_common_config to configure the speed and mode. These functions expect SoC to include soc_amd_common_config in SoC chip config and mainboard to configure these settings in device tree. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41248 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12Doc/mb/lenovo: Fix broken linkAngel Pons
Change-Id: Iafa7e0f3734042e35e8b4ea440baf1c3c3d147e9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-12pciexp_device: Add option to allocate prefetch memory above 4G boundaryFurquan Shaikh
This change adds a Kconfig option to request allocation of prefetch memory for hotplug devices above the 4G boundary. In order to select this option by default and still allow users to disable this if required, another option is added to request allocation of prefetch memory below 4G boundary which defaults to n but can be overriden by mainboards. Without this change, if the number of pciexp bridges supporting hot-plug is more than 4 or if the reserved prefetch memory size for hot-plug cases was increased, then the resource allocator would fail to satisfy the resource requirement below 4G boundary. BUG=b:149186922 TEST=Enabled resource allocation above 4G for prefetch memory on volteer and verified that it gets allocated above 4G boundary. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I061d935eef9fcda352230b03b5cf14e467924e50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39489 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12pci_device: Extend PCI domain limit to 64-bitFurquan Shaikh
This change updates the resource limit for PCI domain to allow resource allocation above 4G boundary. The resource limit is set to the highest physical address for the CPU. BUG=b:149186922 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Idfcc9a390d309886ee2b7880b29502c740e6578e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39488 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12device: Enable resource allocation above 4G boundaryFurquan Shaikh
This change adds support for allocating resources above the 4G boundary by making use of memranges for resource windows enabled in the previous CL. It adds a new resource flag IORESOURCE_ABOVE_4G which is used in the following ways: a) Downstream device resources can set this flag to indicate that they would like to have their resource allocation above the 4G boundary. These semantics will have to be enabled in the drivers managing the devices. It can also be extended to be enabled via devicetree. This flag is automatically propagated by the resource allocator from downstream devices to the upstream bridges in pass 1. It is done to ensure that the resource allocator has a global view of downstream requirements during pass 2 at domain level. b) Bridges have a single resource window for each of mem and prefmem resource types. Thus, if any downstream resource of the bridge requests allocation above 4G boundary, all the other downstream resources of the same type under the bridge will be allocated above 4G boundary. c) During pass 2, resource allocator at domain level splits IORESOURCE_MEM into two different memory ranges -- one for the window below 4G and other above 4G. Resource allocation happens separately for each of these windows. d) At the bridge level, there is no extra logic required since the resource will live entirely above or below the 4G boundary. Hence, all downstream devices of any bridge will fall within the window allocated to the bridge resource. To handle this case separately from that of domain, initializing of memranges for a bridge is done differently than the domain. Limitation: Resources of a given type at the bridge or downstream devices cannot live both above and below 4G boundary. Thus, if a bridge has some downstream resources requesting allocation for a given type above 4G boundary and other resources of the same type requesting allocation below 4G boundary, then all these resources of the same type get allocated above 4G boundary. BUG=b:149186922 TEST=Verified that resources get allocated above the 4G boundary correctly on volteer. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I7fb2a75cc280a307300d29ddabaebfc49175548f Reviewed-on: https://review.coreboot.org/c/coreboot/+/39487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-12device: Enable resource allocator to use multiple rangesFurquan Shaikh
This change updates the resource allocator in coreboot to allow using multiple ranges for resource allocation rather than restricting available window to a single base/limit pair. This is done in preparation to allow 64-bit resource allocation. Following changes are made as part of this: a) Resource allocator still makes 2 passes at the entire tree. The first pass is to gather the resource requirements of each device under each domain. It walks recursively in DFS fashion to gather the requirements of the leaf devices and propagates this back up to the downstream bridges of the domain. Domain is special in the sense that it has fixed resource ranges. Hence, the resource requirements from the downstream devices have no effect on the domain resource windows. This results in domain resource limits being unmodified after the first pass. b) Once the requirements for all the devices under the domain are gathered, resource allocator walks a second time to allocate resources to downstream devices as per the requirements. Here, instead of maintaining a single window for allocating resources, it creates a list of memranges starting with the resource window at domain and then applying constraints to create holes for any fixed resources. This ensures that there is no overlap with fixed resources under the domain. c) Domain does not differentiate between mem and prefmem. Since they are allocated space from the same resource window at the domain level, it considers all resource requests from downstream devices of the domain independent of the prefetch type. d) Once resource allocation is done at the domain level, resource allocator walks down the downstream bridges and continues the same process until it reaches the leaves. Bridges have separate windows for mem and prefmem. Hence, unlike domain, the resource allocator at bridge level ensures that downstream requirements are satisfied by taking prefetch type into consideration. e) This whole 2-pass process is performed for every domain in the system under the assumption that domains do not have overlapping address spaces. Noticeable differences from previous resource allocator: a) Changes in print logs observed due to flows being slightly different. b) Base, limit and size of domain resources are no longer updated based on downstream requirements. c) Memranges are used instead of a single base/limit pair for determining resource allocation. d) Previously, if a resource request did not fit in the available base/limit window, then the resource would be allocated over DRAM or any other address space defeating the principle of "no overlap". With this change, any time a resource cannot fit in the available ranges, it complains and ensures that the resource is effectively disabled by setting base same as the limit. e) Resource allocator no longer looks at multiple links to determine the right bus for a resource. None of the current boards have multiple buses under any downstream device of the domain. The only device with multiple links seems to be the cpu cluster device for some AMD platforms. BUG=b:149186922 TEST=Verified that resource allocation looks correct based on addresses assigned on Volteer. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia1f089877c62e119c6a994a10809c9cc0050ec9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39486 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12inteltool: fix dumping of Lynx Point LP and Wildcat Point PM registersIru Cai
Currently inteltool uses the addresses and names of the PCH of previous generations. It's wrong for Lynx Point LP and Wildcat Point. The addresses and names of the I/O registers can be found in "Mobile 4th Generation Intel Core Processor Family I/O Datasheet" (Document Number: 329003-003) for Lynx Point LP and "Mobile 5th Generation Intel Core Processor Family I/O, Intel Core M Processor Family I/O, Mobile Intel Pentium Processor Family I/O, and Mobile Intel Celeron Processor Family I/O Datasheet" (Document Number: 330837-004) for Wildcat Point. Change-Id: If6ba718ccff077aa89affec89018bd7923527466 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40273 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12Documentation/getting_started: Fix typoPaul Menzel
Change-Id: I41571c45719dfade49a021b6bafe80afdcb7b581 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-12soc/intel/skl: Drop weak mainboard_memory_init_paramsAngel Pons
We should not need that. Change-Id: Ic0181a300670ed7ee999dafedac79f3f89bfbee9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner
2020-05-12Revert "sb/intel/common/acpi: Add more Windows versions"Nico Huber
This reverts commit cc805d9dd64ca2d3c8de2b2de2ea7c53b387ff8f. Advertising certain Windows versions triggers different paths in the OS. As there may also be device specific quirks in the OS, such changes need to be tested thoroughly on all affected devices. There was at least one very subtle regression introduced by this. When Linux sees "Windows 2012" support advertised, it disables the `acpi_video` backlight controls, at least on devices with Intel IGD. Without user-space handling the ACPI events, keyboard backlight controls stop working. Moreover, the commit message didn't state any reason for this change. Why was it merged? Change-Id: I722075f8e8f836b039fb8b8277e665fb49dac8f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12Revert "mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method"Nico Huber
This reverts commit b3100775ae29caebd068db8f6209561abda2fb0c. This was part of a series that moved things to common code and causes regressions. Change-Id: I239906e498c8352e6880408744f176a8aeb13dc8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12nb/intel/i440bx: Drop mainboard_enable_serial()Keith Hui
All boards using this northbridge now enable serial in bootblock, so this is no longer needed. Change-Id: I6baf2de81870dbba2a7f1abb3f1fdd6716d64511 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41048 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12soc/amd/common/block/lpc: Split lpc_set_spibase() into two functionsFurquan Shaikh
This change splits lpc_set_spibase() into two separate functions: lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI controller (if supported by platforms) lpc_enable_spi_rom() - Enables SPI ROM This split is done to allow setting of MMIO base independent of ROM enable bits. On platforms like Picasso, eSPI base is determined by the same register and hence eSPI can set the BAR without having to touch the enable bits. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-12soc/amd/common/block: Add support for common config for AMD SoCsFurquan Shaikh
This change adds support for struct soc_amd_common_config that allows multiple AMD SoCs to share common configuration. This can then be used by common/block drivers to get the required configuration from device tree. It also provides function declaration for soc_get_common_config() that needs to be provided by SoCs making use of the common configuration structure. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Idb0d797525414c99894a8e4ede65469381db7794 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41246 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12Documentation/releases: Update for 4.12Patrick Georgi
Fill in some blanks for 4.12, mark it done, add template for 4.13. Also update the list of vboot supported boards. Change-Id: Id6b663f13367eb40e66af30aadd33991c8dd635c Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-12nb/intel/sandybridge: Reorder IOSAV writesAngel Pons
We only write to the IOSAV LFSR registers twice, but we do so between the writes to the other four IOSAV per-subsequence registers. Since we know that the IOSAV is sleeping when we program the subsequences, we might as well do the two oddball LFSR register writes after we have programmed the always-written-to group of four registers. That way, subsequent changes can reproducibly replace the four writes with a single macro. Tested on Asus P8Z77-V LX2, still boots. Change-Id: If7bb14a9862a53a3eba565d17401347dcc9ffbe9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40973 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12nb/intel/sandybridge: Reorder register writeAngel Pons
Reorder the order of the operands in three register writes, so that replacing them with macros in a follow-up does not change the binary. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I44aee9c0f49770586de322ee7f44c3609dbadd0b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40972 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 21:21:33 +0000