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2016-03-23arch/x86: introduce postcar stage/phaseAaron Durbin
Certain chipsets don't have a memory-mapped boot media so their code execution for stages prior to DRAM initialization is backed by SRAM or cache-as-ram. The postcar stage/phase handles the cache-as-ram situation where in order to tear down cache-as-ram one needs to be executing out of a backing store that isn't transient. By current definition, cache-as-ram is volatile and tearing it down leads to its contents disappearing. Therefore provide a shim layer, postcar, that's loaded into memory and executed which does 2 things: 1. Tears down cache-as-ram with a chipset helper function. 2. Loads and runs ramstage. Because those 2 things are executed out of ram there's no issue of the code's backing store while executing the code that tears down cache-as-ram. The current implementation makes no assumption regarding cacheability of the DRAM itself. If the chipset code wishes to cache DRAM for loading of the postcar stage/phase then it's also up to the chipset to handle any coherency issues pertaining to cache-as-ram destruction. Change-Id: Ia58efdadd0b48f20cfe7de2f49ab462306c3a19b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14140 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-22gpio: Add support for binary_first base3 number systemJulius Werner
This patch adds support for an alternative ternary number system in which group of GPIOs can be interpreted. In this system, the digit combinations that would form a binary number (i.e. that contain no 'Z' state) are used to represent the lower values in the way they're used in the normal binary system, and all the combinations that do contain a 'Z' are used to represent values above those. We can use this for boards that originally get strapped with binary board IDs but eventually require more revisions than that representation allows. We can switch their code to binary_first base3 and all old revisions with already produced boards will still get read as the correct numbers. Credit for the algorithm idea goes to Haran Talmon. BRANCH=None BUG=None TEST=Stubbed out the actual GPIO reading and simulated all combinations of 4 ternary digits for both number systems. Change-Id: Ib5127656455f97f890ce2999ba5ac5f58a20cf93 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14116 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-22MAINTAINERS: Add maintainer for Braswell SOC & Reference boardMartin Roth
Change-Id: If3b49c3056abe6e1c1a14578d6c62a866bc6834d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14127 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2016-03-22lib/rmodule: export parameters in struct rmod_stage_loadAaron Durbin
In order for a caller to utilize an rmodule's parameters section after calling rmodule_stage_load() export the rmodule's parameter pointer in struct rmod_stage_load. Change-Id: I9cd51652cf8cdb3fae773256989851638aa1a60f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14139 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-21soc/apollolake: Add skeleton ACPI entryLance Zhao
Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/13348 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-21nb/intel/sandybridge: increase MMCONF_BASE_ADDRESSPatrick Rudolph
Set MMCONF_BASE_ADDRESS to 0xf8000000. It was already done for some boards, but not all. The sandybridge chipset code assumes 64 pci buses behind MMCONF. Therefore, only 64MiB of physical address space is required. Increasing the address allows to use additional 128MiB of MMIO space and to use the Intel IGD and a PEG at the same time. Previously it wasn't possible to use both at the same time, as two 256MiB areas won't fit into MMIO space. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Onboard GPU Intel IvyBridge Desktop * PEG GPU AMD RV770 Change-Id: I3bf72439056c8089ada6899bb0605e5cd9d89cd6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-03-21mediatek/mt8173: Enable ARM trusted firmware integrationPatrick Georgi
In Chromium OS downstream this was done together with adding the support for ATF, but unfortunately ATF upstream isn't ready yet. This commit is a reminder to enable things once ATF caught up. Change-Id: Id0d6908d906a1e54cdda4f232d572d996d9c556f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13968 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21mediatek/mt8173: Remove bl31 board parameters passing mechanismJimmy Huang
As the DA9212 and MT6311 external buck can be controlled by hardware since rev-5 board, we don't need to pass any board specific parameter to ARM TF. BRANCH=none BUG=none TEST=build pass Change-Id: I43eebe25ab14d3dd84e8bb4286e2bb55c8c3c063 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c4dfe61c69042e464b384e2e0edbc55eda23a74 Original-Change-Id: I541357fee6afb1ff2d771bcb073f7c9a9db52f00 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332344 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14124 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21google/oak: Move external buck initialization to coreboothenryc.chen
Remove the code which is passing parameters to ARMTF and move external buck initilizaton from ARMTF to coreboot. BRANCH=none BUG=none TEST=verified on Oak rev4/rev5 Change-Id: I4f4b30acbee9b42a202b326f2fe4517cb4b9d83c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37bec54b4d8a3bce38878e292e4821da3959026a Original-Change-Id: Ib81709812a064f6daf13c9b4d6525f1858c81393 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332343 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14123 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21mediatek/mt8173: Add da9212 driverhenryc.chen
Add secondary PMIC for external buck control on Oak rev0/1/2/5 BRANCH=none BUG=none TEST=verified on Oak rev4/rev5 Change-Id: Ia000b0c7d61e8396856656247f9627e33b21b19b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 241508e7d781fac8ee085ee81962043dd654c52d Original-Change-Id: I6c75e2462363a5523bf1ebb03af7a36740293624 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332342 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21mediatek/mt8173: Add mt6311 driverhenryc.chen
Add secondary PMIC for external buck control on Oak rev3/4 BRANCH=none BUG=none TEST=verified on Oak rev4/rev5 Change-Id: I24c18a1cf71fc57deacedcbeb6a100b131c28077 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7f7f8ceac795d8193194a6918a73c4b391009025 Original-Change-Id: I312d8281d2c09d8bc43f092edef3e405d51ee7d0 Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332341 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14121 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21device: Add i2c read/write register field APIYidi Lin
i2c_read_field() - read the value from the specific register field i2c_write_field() - write the value to the specific register field BRANCH=none BUG=none TEST=none Change-Id: I2098715b4583c1936c93b3ff45ec330910964304 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0817fc76d07491b39c066f1393a6435f0831b50c Original-Change-Id: I92c187a89d10cfcecf3dfd9291e0bc015459c393 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332712 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain setTimothy Pearson
Under certain conditions (training abort) BlockRxDqsLock could remain set in violation of the BKDG. Ensure BlockRxDqsLock is reset to 0 after a lane training abort. Change-Id: I1a49a24d02b2b7cacae074794ec274a424a9e66b Reviewed-on: https://review.coreboot.org/14144 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21Documentation: x86 MTRR setup, TempRamExit and MTRR loadingLee Leahy
Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14113 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21Documentation/Intel: Add more Galileo Gen2 linksLee Leahy
Add datasheet links for the components supporting GPIO. This includes I2C I/O ports, I2C PWMs, bus buffers and multiplexers. TEST=None Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14114 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21Documentation: x86 shadow ROM disableLee Leahy
Add documentation on disabling the SPI flash which is mapped (shadowed) into the x86 address space at 0x000e0000 - 0x000fffff. TEST=None Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/14112 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21soc/intel/quark: Disable the ROM shadowLee Leahy
Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing successful display of 0x000ffff0 - 0x000fffff does not match the end of the SPI flash. Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14110 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21mainboard/intel/galileo: Enable SPI controllersLee Leahy
Enable the SPI controllers on the Quark SoC. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Load the SPI driver stack * Testing is successful when the time is able to be displayed on a set of seven-segment displays controlled by a Maxim MAX6950 SPI display controller. Change-Id: Ic9c4575730c5a9a27cf9a38a41e82d8462467f3f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21device/dram/ddr3: fix debug outputPatrick Rudolph
Add missing punctuation and align output. No functionality is changed. Old logging output: Revision: 11 Type : b Key : 2 Banks : 8 Capacity: 4 Gb Supported voltages: 1.5V SDRAM width : 8 Bus extension : 0 bits Bus width : 64 Optional features : DLL-Off_mode RZQ/7 RZQ/6 Thermal features : ASR ext_temp_range Thermal sensor : no Standard SDRAM : yes DIMM Rank1 Address bits mirrored!!! DIMM Reference card B DIMM Manufacturer ID cd04 DIMM Part number F3-1866C9-8GSR XMP Profile 1 Max DIMMs per channel: 4 XMP Revision: 1.3 Requested voltage: 1500 mV New logging output: Revision : 11 Type : b Key : 2 Banks : 8 Capacity : 4 Gb Supported voltages : 1.5V SDRAM width : 8 Bus extension : 0 bits Bus width : 64 Optional features : DLL-Off_mode RZQ/7 RZQ/6 Thermal features : ASR ext_temp_range Thermal sensor : no Standard SDRAM : yes Rank1 Address bits : mirrored DIMM Reference card: B Manufacturer ID : cd04 Part number : F3-1866C9-8GSR XMP Profile : 1 Max DIMMs/channel : 4 XMP Revision : 1.3 Requested voltage : 1500 mV Change-Id: Iee4d7a7c0e1070706fb60d7316fad49813963b51 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14083 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-21arch/x86: honor CONFIG_X86_TOP4G_BOOTMEDIA_MAP for verstageAaron Durbin
When CONFIG_X86_TOP4G_BOOTMEDIA_MAP was introduced verstage was not updated. Correct this oversight. Change-Id: I2775c08798906ba0ba55a361407d7d2b52313229 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14142 Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Tested-by: build bot (Jenkins)
2016-03-21MAINTAINERS: Add maintainers for power8 architectureMartin Roth
Change-Id: I0eedda5f31c2809db7871b81ceb3045b782f9df1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14126 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-03-21MAINTAINERS: Add maintainer to lint scripts, board status & payloadsMartin Roth
Change-Id: I3efd4116da1ffda2dbc768d1a447141d8ec76f81 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21payloads: Add a target to print payload git urls and directoriesMartin Roth
Being able to fetch this list will allow the jenkins builder to securely fetch the external payloads so we can start testing payload builds. Change-Id: I777229216b2f11f0f427cd5f8cfa003da4171a77 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21payloads/Makefile.inc: Clean up MakefileMartin Roth
- Instead of adding each payload to each common target, create a list and loop through the list for all of the payloads - '.phony' doesn't work - the target needs to be uppercase '.PHONY' Change-Id: I4a7712c94d0f127c2fff8cb8fada4b8132a4ab3b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14131 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-21payloads/external: Rename Makefile.inc to MakefileMartin Roth
These makefiles are not included by anything, so they shouldn't be named Makefile.inc. Also, having them all be named 'Makefile' makes some other consolidation work I'm doing much easier. Change-Id: I1234539ba6a0a6f47d2eb0c21de3da3607c6b8de Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14130 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-18coreinfo: Allow numbers in addition to F keysStefan Reinauer
When using coreinfo on a serial console (at least with gtkterm, picocom and minicom on Ubuntu 15.10) you can't send F keys to the payload. Allow 1..9 for F1..F9 Change-Id: Ie3a11fa1de57c7345737a1ccaff177f407cd5e48 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14065 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-18src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI tableJacob Laska
The previous implementation assumed the CPU physical address size to be 40 which is not true of all platforms. Use an existing function to obtain the correct CPU physical address to report in the DMAR ACPI table. Change-Id: Ia79e9dadecc3f5f6a86ce3789b213222bef482b3 Signed-off-by: Jacob Laska <jlaska91@gmail.com> Reviewed-on: https://review.coreboot.org/14102 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-03-18mtrr: Define a function for obtaining free var mtrrFurquan Shaikh
Instead of hard-coding var mtrr numbers in code, use this function to identify the first available variable mtrr. If no such mtrr is available, the function will return -1. Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/14115 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-18google/oak: Enable RAM_CODE_SUPPORTYidi Lin
BRANCH=none BUG=chrome-os-partner:50820 TEST=check /proc/device-tree/firmware/coreboot/ram-code Change-Id: I5ecf45cada7f8999ad607487d5d9281c4fb659ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 79d2f0e183a2bde70817d673ae315709f46e3361 Original-Change-Id: I35e91b4e29f8e09acd74770715c96cf7320ac22c Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332564 Original-Reviewed-by: Milton Chiang <milton.chiang@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14104 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-18mediatek/mt8173: mt6391: set VSRMCA7 to HW control by SRCVOLTENhenryc.chen
When system enters suspend, SPM will pull SRCVOLTEN low to turn off some power rails. VSRMCA7 should follow this pin to turn on/off the power. BRANCH=none BUG=none TEST=verified on Oak rev5 Change-Id: I9d81f855a74fe02a59246ce0c6a7f0e162b9fd0a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d92fb1029b810028138eb91b064b63a58b82602f Original-Change-Id: I37ff0694cbd7b17d5a1ae172c463b4e6aae2b99c Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332345 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14103 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-17build system: Allow overriding the path to the futility binaryPatrick Georgi
Change-Id: I84e68e8407149780769c3e6a1148c175e42d1025 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/14100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16cpu/x86: compile earlymtrr.c code for romstage as wellAndrey Petrov
In order to make this work earlymtrr.c needed to be removed from intel/truxton/romstage.c. It's not a ROMCC board so there's no reason to be including .c files. Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/14094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16cpu/x86/mtrr: remove early_mtrr_* functionsAaron Durbin
I see no user of any of this code. Remove it. Change-Id: I776cd3d9ac6578ecb0fe6d98f15611e4463afb7a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14098 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-16libpayload: recreate config filesStefan Reinauer
Add all the default options with: for i in configs/* do cp $i .config make savedefconfig mv defconfig $i done This also switches to minimal config files instead of the full configuration files that were previously checked in. Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14077 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-03-16coreinfo: Rename libpayload variablesStefan Reinauer
LIBCONFIG_PATH -> LIBPAYLOAD_PATH LIBPAYLOAD_DIR -> LIBPAYLOAD_OBJ Change-Id: Idd9947bac594f5b109b877aefac70b1a1d2336eb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14099 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-16rockchip: update make_idb.pyhuang lin
make_idb.py only support RK3288 before, add chip parameter, so we can support RK3399 either. Change-Id: I6811acb7f0cdaf1930af9942a70db54765d544d5 Signed-off-by: huang lin <hl@rock-chips.com> Reviewed-on: https://review.coreboot.org/13913 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-16skylake mainboards: Configure gpio PADRSTCFG to PLTRSTNaresh G Solanki
With gpio PADRSTCFG set to DEEP & GPIROUTIOXAPIC=1 & PADRSTCFG, causes IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over pltrst and hence configuring PADRSTCFG to PLTRST to prevent IRQ strom after S3 resume. BRANCH=glados BUG=chrome-os-partner:50536 TEST=Build for kunimitsu and Boot on FAB4, no irq storm observed after S3 resume. Change-Id: I7f1ae90aed03778e7d6cb2d79de0efe9a6d9e20d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aff91da4feaf8f7e42cfeee756cf468288cbfd68 Original-Change-Id: I7cac60fb0144e090b8decb05d948b2d8d2f8deac Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/329453 Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331174 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13992 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16util/nvidia/cbootimage: update to latest masterPatrick Georgi
This includes a fix that allows using cbootimage with paths containing the "@" sign, which happens sometimes in jenkins configurations. Change-Id: I83154afa35b6d24449e713e57031b1a93d7ac748 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14090 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-16parade/ps8640: Clean upPatrick Georgi
Sort out some style issues that were identified by Paul. Change-Id: I9ed946ae613c87234f8c9824eb14b8d28909dfcf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14064 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-15coreinfo: Use tinycursesStefan Reinauer
When using PDcurses over a serial line, the background of coreinfo is not properly cleared. Hence use tinycurses, which was the only option when coreinfo was developed. Change-Id: I15bb6eb552cf924de98d09ef63be33ecf336c526 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14067 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-03-15pcengines/apu1: Enable USB overcurrent detection.Tobias Diedrich
The two external USB ports and the internal USB header have overcurrent protection chips with the low-active overcurrent signal connected to the chipset. The power-on default for this register disables the software detection of overcurrent conditions. After setting the register Linux correctly shows the overcurrent condition in the kernel log (tested by shorting the 5v and gnd lines on J14 / the internal USB header): [ 2015.229921] usb usb1-port3: over-current condition [ 2015.449925] usb usb1-port4: over-current condition Simlar for the external ports: [ 256.237916] usb usb1-port1: over-current condition [ 256.458084] usb usb1-port5: over-current condition Note that each signal is shared between two ports: usboc0#: External ports (port1/5) usboc1#: Internal ports (port3/4) Change-Id: I02d498053b8ec61dc206e74a96c4a1dcfd4fae92 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/14084 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15lenovo: add config ONBOARD_VGA_IS_PRIMARYPatrick Rudolph
Fix for the T4xx and T5xx series. It does not apply to X2xx/X6x series as those have only one GPU, which is always connected to the display. The T6x series needs special care not handled with this patch. Without ONBOARD_VGA_IS_PRIMARY the onboard GPU would be deactivated in case a dedicated GPU is found and active, leaving the system without a working display. Change-Id: I94d1700e9afb75de83a4f2ed1ff53ba3b0559ae1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14031 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2016-03-15google/oak: add table for 4GB configurationPH Hsu
BRANCH=none BUG=chrome-os-partner:49229 BUG=chrome-os-partner:50806 TEST=power on to kernel on Oak Rev3 with 4GB dram Change-Id: I32fa881df12eb9b7f66086904aebde3dd1483fbf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275 Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331811 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14089 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15mediatek/mt8173: Enable 4GB modePH Hsu
If the system is using 4GB of memory, enable 4GB mode in the memory controller. Change-Id: I4d0f8ad8d43ff45dd786f4244b11c0879d2088cd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94c8b7ad911c93c4325113e7afc009f2f81d2275 Original-Change-Id: Ia3640882a46e695550e679dc70611855b64a560f Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331811 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14088 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15google/oak: Remove EC_SUSPEND_L from APKoro Chen
This pin is not used anymore since Rev5. BRANCH=none BUG=chrome-os-partner:49375 TEST=make and boot on Rev4/5 Change-Id: I3c775eb2b5e05256523bfd8be814e516944a2f90 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a87e3babe28413bd879a2d95d4612a5b6b541419 Original-Change-Id: I87972ff8961309ecdad03639e1b6fac1da119cd7 Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/331810 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14087 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15Makefile.inc: Add toupper, tolower, and ws_to_under macrosMartin Roth
Add a few additional macros that can be used throughout the coreboot makefiles. tolower: returns the value in all lowercase toupper: returns the value in all uppercase ws_to_under: returns the value with any whitespace changed to underscores Change-Id: Icd0e6586481d8f229af0e899e0c94ef7c5c672c3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14093 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-15payloads: Enable building depthcharge as part of the coreboot buildStefan Reinauer
For CHROMEOS builds, depthcharge can be built automatically. This dependency exists because depthcharge without vboot and subsequent signing of the image doesn't work very well, and both are keyed to that flag as well. Change-Id: Id0195bd3b4e454f382782106d6512469106daac5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/10924 Tested-by: build bot (Jenkins)
2016-03-15x86: Drop CONFIG_COMPILE_IN_DSDTStefan Reinauer
This option is no longer needed, as FMAP support has been fully integrated in coreboot Change-Id: I6121b31bf946532717ba15e12f5c63d2baa95ab2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14078 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-15libpayload: Move base address, stack and heap size to KconfigStefan Reinauer
This will allow more payloads to use the standard linker script instead of implementing their own. Change-Id: Ie60120769829f427ceb722109d85859b61dbde31 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-07 23:10:35 +0000