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2008-07-23This patch fixes the kernel EBDA mislocation problem. Thank you, Yinghai.Roman Kononov
The change in tables.c protects the legacy x86 BIOS data segment (0x400-0x4ff) from being used for storing coreboot tables. Some bytes from the segment are used by the kernel and should not be garbled. The change in coreboot_table.c is not strictly necessary. It removes some redundancy and confusion. Signed-off-by: Roman Kononov <kononov@dls.net> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Fix r3434 check-in. Added missing end to Options.lb. Not entirely sure how itMarc Jones
went missing.... Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Add AMD Fam10 B3 default settings to match AMD example code.Marc Jones
Includes setting for most recent errata. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Update to the latest AMD Fam10 microcode patches.Marc Jones
Add platform option for patch file name. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-23Memory initialization support for AMD Fam10 B3 (B0-B2 already supported).Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21Missed a const in my previous checkin, r3426 (trivial).Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21flashrom: Winbond W39V040C and MSI K8T Neo2-FPeter Stuge
W39V040C does standard JEDEC commands except chip erase so add a small driver. probe_w39v040c() prints the block lock pin status when a chip is found. The Neo2 board enable matches on 8237-internal IDE and onboard NIC PCI IDs. Many thanks to Daniel McLellan for testing all of this on hardware! Build tested by Uwe. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-21Add support for the Winbond W83697HF Super I/O.Sean Nelson
Signed-off-by: Sean Nelson <snelson@nmt.edu> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-19superiotool: add support for SMSC SIO10N268 (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-19add support for 2 new SMSC superio chips. Information is a bit ambiguousStefan Reinauer
and scattered within the datasheets. (trivial patch) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-18Random coding style fixes and simplifications (trivial).Uwe Hermann
This will even reduce the final payload size a bit. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3427 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17Add manual HT BUID fixup to detect previously set BUIDs in early init. This ↵Marc Jones
fixes the non-coherent(sb) link running at default speed. Fix HT event notify to output useful information. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17Clean up AMD FAM10 HT variable initialization. The structure init is ↵Marc Jones
cleaner, avoid compiler warnings, and matches the AMD example code more closely. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-17Add Fam10 Gart table walk enable for MCA reporting to match AMD example code.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-16Clean up comments, whitespace, and copyright date in the AMD HT code.Marc Jones
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-15Add missing Intel CPU (trivial).Uwe Hermann
Tested by me on actual hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-12There was a programming error which made most USB port4 setup wrong. This ↵Marc Jones
patch uses byte pointer and the MMIO read and write functions. Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-11Fix and clean up coreboot image detection heuristic.Carl-Daniel Hailfinger
Additional compile fix for NetBSD. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-08Add a coreinfo module which can hexdump arbitrary RAM regions andUwe Hermann
allows you to scroll through the RAM contents. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07flashrom: Trivial SPI cleanupsPeter Stuge
While writing a new SPI driver I fixed some things in the SPI code: All calls to spi_command() had unneccessary #define duplications, and in some cases the read count define could theoretically become harmful because NULL was passed for the read buffer. Avoid a crash, should someone change the #defines. I also noticed that the only caller of spi_page_program() was the it87 driver, and spi_page_program() could only call back into the it87 driver. Removed the function for easier-to-follow code and made it8716f_spi_page_program() static. The ichspi driver's static page functions are already static. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-07flashrom: Trivial indent fix in ichspi.cPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06r3415 removed symbolic constants for device IDs by accident.Carl-Daniel Hailfinger
flash.h is a database of known IDs, whereas flashchips.c is a database of chips for which support has been implemented. Keep it that way. Trivial. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3416 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-06flashrom: Add AMIC A29002Andreas Thienemann
This patch adds support to the AMIC A29002 chip in its top and bottom configuration to flashrom. Additionally, the alphabetic order of the AMIC chips was fixed. The datasheet is at <http://www.amictechnology.com/pdf/A29002.pdf>. A29002T PREW functionality was tested and works. This flash chip has asymmetric sector layout so it is important to use the mx29f002 driver, which does chip erase before writing, rather than am29f040b, which uses sector erase. Signed-off-by: Andreas Thienemann <andreas@bawue.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-05Adding support for flashing system with Nvidia MCP67Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-05flashrom: Add PCI IDs for EPIA-CNPeter Stuge
Uses the 0.0 Host bridge CN700/VN800/P4M800CE/Pro and 11.0 ISA bridge devices with their 1106:aa08 subsystem id:s for autodetection. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03Minor cosmetics, e.g. make stuff fit in 80 chars/line etc. (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03Mark SST49LF040B as tested.Carl-Daniel Hailfinger
Thanks to Paul Seidler and Ward Vandewege for testing. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03Mark the SST SST49LF040 as OK (tested by me), all operations (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03flashrom: Winbond W25x80 TEST_OK PROBE READ ERASE WRITEPeter Stuge
Per test report from Björn Gerhart. Thanks! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-03Improve coreboot image detection heuristic in flashrom. It's notCarl-Daniel Hailfinger
absolutely perfect, but the likelihood of this check to fail is 0.000000000000000000000000013 (1.3*10^-26) which is good enough for me. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02flashrom: probe_flash() cleanup for better code readabilityPeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02set w39v080fa to fully supported. I'm am flashing this chip several times aStefan Reinauer
day. Also enable unlocking which is only needed when running coreboot, that slipped in the original commit and through the original review ;-) So it must be trivial enough. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02flashrom: Update to TEST_OK for Winbond W39V040FA PROBE READPeter Stuge
Thanks to Jake for the test report! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02flashrom: Don't rm *~ in make clean, who knows what files that could bePeter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02flashrom: Unknown vendor:board message can be triggered by -m tooPeter Stuge
Thanks to Stefan for pointing this one out. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-02flashrom: Case insensitive matching of vendor:board strings in coreboot tablePeter Stuge
Needed at least for GIGABYTE:m57sli in coreboot to match gigabyte:m57sli in flashrom. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30First attempt to clean up SPI probing and create a commonStefan Reinauer
construct: the flash bus. At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30Mine AMIC flash chip needs 4 bytes RDID. This enables to use the new probing ↵Rudolf Marek
code. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30Mine AMIC flash chip needs 4 bytes RDID. Following patch adds support for that.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-30This patch adds support for VIA SPI controller on VT8237S. It is similar withRudolf Marek
few documented exceptions to ICH7 SPI controller. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29Add a debug marker after ICH SPI opcode programming.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29Adds a field to the serial port descriptor about the configured line speed.Patrick Georgi
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-29flashrom: Fix ICH7 non-SPI that broke in r3393Peter Stuge
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back to 0 when BOOT BIOS Straps indicate something else than SPI. Also fixes a build error in ichspi.c with gcc 4.2.2. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-28Use symbolic constants for PCI subsystem probing in flashrom.Carl-Daniel Hailfinger
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-27* ICH7 SPI supportStefan Reinauer
* fix some variable names in ichspi.c (Offset -> offset) * Dump ICH7 SPI bar with -V * Improve error message in case IOPL goes wrong. (It might not even be an IOPL) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-27indent according to development guidelines (trivial)Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-26Initial support for the A-Trend ATC-6240 board.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-26Winbond W39V080FA: Probe and Read are OK.Jens Kühnel
Signed-off-by: Jens Kühnel <coreboot@jens.kuehnel.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3390 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24flashrom: Test status OK for ST M50FW040 PROBE READPeter Stuge
Per test report from Alex Perez. Thanks Alex! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-24flashrom: Test status OK for Macronix MX25L8005 PROBE READ ERASE WRITEPeter Stuge
Per test report from Andrew Paprocki. Thanks Andrew! Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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