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2014-02-11Move hexdump32() to lib/hexdump.Kyösti Mälkki
Needs printk and is not a console core function. Change-Id: Id90a363eca133af4469663c1e8b504baa70471e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5155 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-11Kconfig: Move vendorcode menu up from the bottom to above Chipset menuPeter Stuge
Change-Id: Ic97a497a634533f44d94df297ca6e35d94c34565 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/5160 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-11cbfstool/lzma: Remove code which depends on commented out definesAlexandru Gagniuc
These options seem to control the behavior of the encoder/decoder, with comments citing a trade-off between memory usage and performance. I removed these in a separate patch to make reverting in the future easier, if we find these options are useful. Change-Id: I24cb7101b89e60f4fb96777e3681c03d2a62e3d5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5084 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-11cbfstool: Deserialize CBFS master header when reading imageAlexandru Gagniuc
Rather than using [hn]to[nh] whenever accessing a member of the CBFS header, deserialize the header when opening the CBFS image. The header is no longer a pointer inside the CBFS buffer, but a separate struct, a copy of the original header in a host-friendly format. This kills more of the ntohl usage. Change-Id: I5f8a5818b9d5a2d1152b1906249c4a5847d02bac Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5121 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-11hp/dl145_g1: Adding ACPI supportOskar Enoksson
Basic ACPI support for this old platform. Created by copying and tweaking similar motherboard ACPI implementations in coreboot. Works reasonably well under Linux, providing HPET-timers and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44). Not tested under Windows. Change-Id: I69431be962a0d272db398ecf4ac9f0249de8ebab Signed-off-by: Oskar Enoksson <enok@lysator.liu.se> Reviewed-on: http://review.coreboot.org/5185 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-10usbdebug: Split PCI EHCI partKyösti Mälkki
There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5175 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10usbdebug: Fix data toggle on receiveKyösti Mälkki
USB device end toggles data PID when we ACK'd the zero-length data packet. As USB host we need to toggle data PID too or the next data received would get discarded. Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4775 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10usbdebug: Remove duplicate port claimKyösti Mälkki
This claim is useless when done before EHCI controller reset. Code in usbdebug_init_() already sets this properly after reset, see use of DBGP_OWNER. Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4709 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10usbdebug: Improve receive speedKyösti Mälkki
Read from USB endpoint_in 8 bytes at a time, the maximum what EHCI debug port capability has to offer. Change-Id: I3d012d758a24b24f894e587b301f620933331407 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4700 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-10cbfstool/lzma: Remove LITTLE_ENDIAN_AND_UNALIGNED_ACCESS_OKAlexandru Gagniuc
This was designed as a micro-optimization for x86, but it is only used once. Let the compiler decide if optimizing this is worth the effort. Change-Id: I5939efa34f0e9d16643893ca04675247842e7db5 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5085 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-10cbfstool: Fix LzmaEnc.c and build with -WshadowAlexandru Gagniuc
LzmaEnc.c was full of shadow definitions. Luckily, shadow definitions were not used after the scope in which they were redefined, so it is possible to just remove them. Tested by successfully booting qemu i440fx to grub2 payload. Change-Id: I01d44db59882114ffe64434b655b931f3beec8e2 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5082 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-10cbfstool: Fix build errors when building with clangAlexandru Gagniuc
Now that we can set CC to an arbitrary compiler, fix issues that clang finds. Luckily, there were only two trivial errors. Change-Id: I0fd1f0f263a8ab7004f39cd36ed42d1a1cba5c04 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5081 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-09device_util: Make device in dev_find_slot_pnp u16.Vladimir Serbinenko
LDN is 8-bit but coreboot squeezes unrelated info: VLDN in this field. Increase to 16-bit to handle this. Change-Id: I97af1b32dcfaed84980fa3aa4c317dfab6fad6d8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5165 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-09mtrr: only add prefetchable resources as WRCOMB for VGA devicesAaron Durbin
Be more conservative and only add VGA devices' prefetchable resources as write-combining in the address space. Previously all prefetchable memory was added as a write-combining memory type. Some hardware incorrectly advertises its BAR as prefetchable when it shouldn't be. A new memranges_add_resources_filter() function is added to provide additional filtering on device and resource. Change-Id: I3fc55b90d8c5b694c5aa9e2f34db1b4ef845ce10 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5169 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-02-07boardstatus/towiki: Fix 1st gen i3/i5/i7 codenameVladimir Serbinenko
It was a typo. Change-Id: I82964b5ed7e7749ba141aeb3ee8dc4c107bcd7a9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5127 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCsVladimir Serbinenko
Change-Id: I3a38ca834606bb53e6f82cbe79c3a99288429aee Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5124 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-07device_util: Add dev_find_slot_pnp.Vladimir Serbinenko
Change-Id: I5223c54c8ddbc60a176e4d718730e99decc772a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5112 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-06ARMv7: Remove static CBMEM allocationKyösti Mälkki
The calculations for static allocation are no longer valid. Change-Id: I6740cdcec789abddf78485a0edaf24882ef8c2a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4569 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-02-06console: Drop IO and Oxford (PCI) UARTs on armv7Kyösti Mälkki
Change-Id: Ia410b61c4babdfa3c984539527a9739462d3ad80 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5141 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-02-06console: Drop extra uart_init()Kyösti Mälkki
This call is already in console_init(). Change-Id: Ie0cb3595af514e37efac5ac5d474f52ba551bf22 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5140 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06uart8250: Drop includes in superioKyösti Mälkki
Change-Id: If723896cc31da75dbb3a63d5dc959764e96fded1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06uart8250: Drop unused declarationsKyösti Mälkki
Change-Id: Ie915ef9dbc45604bd5ca1b610acb12af634fdebe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5138 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06uart8250: Drop xmodem supportKyösti Mälkki
Unused and hard-coded to use uart8250 on IO. Change-Id: I3f84c50039a450a2ae97a5fd2af89992f8567e6c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5137 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-06QEMU debugcon: Move under drivers/emulation/qemuKyösti Mälkki
Also prepare this console for use in romstage. Change-Id: I26a4d4b5db1e44a261396a21bb0f0574d72aa86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5136 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
2014-02-06ne2k: Move under drivers/netKyösti Mälkki
Change-Id: I978b6009c09c31be4429f57be40ef82f438f7574 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5135 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-06spkmodem: Move under drivers/pc80Kyösti Mälkki
Change-Id: I46eb17ab19cea8759b3e4822019285cbe907e83a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5134 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-06usbdebug: Move under drivers/usbKyösti Mälkki
Also relocate and split header files, there is some interest for EHCI debug support without PCI. Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06usbdebug: Drop obsolete codeKyösti Mälkki
Change-Id: I918ca1d0d0d7bcb7e16d41a12830a0357f15b8ed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5130 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-06MTRR: Mark all prefetchable resources as WRCOMB.Vladimir Serbinenko
Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06lib/memrange: Skip 0-sized resources.Vladimir Serbinenko
Change-Id: I44194153817b8e6b641e407fc4a9e0fd5bc3f318 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5152 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocationAaron Durbin
If the MTRR usage exceeds the BIOS allocation for MTRR usage re-try without the WRCOMB type. Change-Id: Ie70ce84994428ff6700c36310264c3c44d9ed128 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5151 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2014-02-06memranges: add memranges_update_tag() functionalityAaron Durbin
The memranges_update_tag() function replaces all instances that are tagged with old_tag and update to new_tag. This can be helpful in the MTRR code by adjusting the address space if certain memory types cause the MTRR usage to become too large. Change-Id: Ie5c405204de2fdd9fd1dd5d6190b223925d6d318 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5150 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-05load_payload: Use 32-bit accesses to speed up decompression.Vladimir Serbinenko
Flash prefers 32-bit sequential access. On some platforms ROM is not cached due to i.a. MTRR shortage. Moreover ROM caching is not currently enabled by default. With this patch payload decompression is sped up by theoretical factor of 4. Test on X201, with caching disabled: Before: 90:load payload 4,470,841 (24,505) 99:selfboot jump 6,073,812 (1,602,971) After: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) Change-Id: Id17e61316dbbf73f4a837bf173f88bf26c01c62b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5144 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-02-05lenovo/x201: Enable flash prefetching.Vladimir Serbinenko
Speeds up coreboot and especially payload load. Before: 90:load payload 4,530,979 (17,728) 99:selfboot jump 5,103,408 (572,429) After: 90:load payload 4,390,051 (14,849) 99:selfboot jump 4,505,966 (115,915) Change-Id: I45c3042594cda16ab3adde6472e00ec1b2d2a688 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-05Add an xdr function for the cbfs_file headerRonald G. Minnich
And use it in fit.c and remove one more use of htonl. Change-Id: Ibf18dcc0a7f08d75c2374115de0db7a4bf64ec1e Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/5120 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-05mainboard/google: add initial rambi mainboard supportAaron Durbin
BUG=chrome-os-partner:23121 BRANCH=None TEST=None Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171940 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/4865 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-05baytrail: initialize punitAaron Durbin
The punit is responsible for a number of things. Without performing the sequence included it won't change processor frequency when requested and apparently there are some bizarre hangs introduced if this sequence isn't included either. Lastly, this needs to come after microcode has been loaded. As that is done in bootblock the ordering is correct. One other side effect is that this fixes the graphics devices' device id. Before it was showing up as the same device id of the SoC transaction router. BUG=chrome-os-partner:22880 BUG=chrome-os-partner:23085 BUG=chrome-os-partner:22876 BRANCH=None TEST=Built and booted. Change-Id: Ib7be1d4b365e9a45647c778ee5f91de497c55bf1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171862 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4864 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05baytrail: load microcode in bootblockAaron Durbin
Start loading microcode in the bootblock. This way no caching has been set up and cache-as-ram mode will be running in a validated configruation (with ucode patch). BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and booted. Confirmed microcode is loaded. Change-Id: I6fd1d8e55bcc9d799b11d9faed771ac50dc120a2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171861 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4863 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05baytrail: disable tco timerAaron Durbin
The TCO timer always starts ticking out of reset. However, depending on microcode loading and punit initialization the TCO timing out has a different impact on the sytem. Without loading microcode or initializing the punit the tco times out and nothing happens. However, when microcode is loaded a timeout will reset the system. Lastly, if the punit is initialized but the microcode isn't loaded the TCO timeout will shut down the system. To fix all the weird symptoms disable the TCO. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and booted with microcode loading. Reset doesn't occur. Change-Id: I49cd62f510726a96bf734ae728a352c671d1561e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171860 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4862 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05baytrail: program PUNIT memory-mapped base addressAaron Durbin
Apparently there was another BAR living at 0x5c in the LPC bridge that mapped the PUNIT registers. EDS 2.0 released and this register is now documented. BUG=chrome-os-partner:23085 BRANCH=None TEST=Built and booted. Change-Id: I5892c2a14923b57826060e92b4335cb1952ea057 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171612 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4861 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05baytrail: add 316 microcodeAaron Durbin
The 316 microcode is the newest version. Include that in the build. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and partially booted with microcode loading. Noted 316 loaded. Change-Id: Iba01dd58688737ae38bc58a84014ee9526540db1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171611 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4860 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05baytrail: additional iosf changesAaron Durbin
Allow for one to write an individual byte of a 32-bit register when sending a read/write through the IOSF messaging system. Add PUNIT registers and fields for early sequencing. BUG=chrome-os-partner:23085 BRANCH=None TEST=Built and partially booted with changes that use PUNIT registers and individual byte en fields. Change-Id: I929fb5c51d805c55c478cab884e3572254987fc7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171710 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4859 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05baytrail: import and use updated mrc_wrapper.hAaron Durbin
The mrc_wrapper.h was changed to protect against ABI differences between the two sets of compilers and flags used. This requires a prope shim for the console output funciton. BUG=chrome-os-partner:23048 BRANCH=None TEST=Built and booted successfully. Change-Id: I976e692e66dcfc0eacadae6173abfd9b81e31137 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171580 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4858 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05baytrail: Rearrange config options alphanumericallyVadim Bendebury
This is a no-op change for easier maintenance. BUG=none TEST=manual . baitrail coreboot still builds and runs Change-Id: I0c0bd78c6f361e8f81979f19cce148e7f51865ee Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171002 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4857 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05baytrail: start collecting timestampsAaron Durbin
This commit always selects COLLECT_TIMESTAMPS and starts tracking TSC values from the early stages of bootblock. The initial timestamp value is saved in mm0 and mm1 while in bootlbock. This approach works because romcc is not configured to use mmx registers for its compilation. Additionally, the romstage api with the mainboard was changed to always pass around a pointer to a romstage_params structure as the timestamps are saved in there until ram is up. BUG=chrome-os-partner:22873 BRANCH=None TEST=Built and booted with added code to print out timestamps at end of ramstage. Everything looks legit. Change-Id: Iba8d5fff1654afa6471088c46a357474ba533236 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170950 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4856 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-05Change the linux payload generator to use the standard header generatorRonald G. Minnich
When I changed mkpayload, I did not realize we had a duplicate block of code in the linux payload code. Have it use the same header generator as the standard payload code does. Change-Id: Ie39540089ce89b704290c89127da4c7b051ecb0e Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: http://review.coreboot.org/5115 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-04cbfstool: Eliminate global variable "arch"Alexandru Gagniuc
Now that unused functions have been removed, the global "arch" is only used in very few places. We can pack "arch" in the "param" structure and pass it down to where it is actually used. Change-Id: I255d1e2bc6b5ead91b6b4e94a0202523c4ab53dc Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5105 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-04cbfstool: Remove more unused functions from common.cAlexandru Gagniuc
A lot of the early functions have been re-implemented in a context- centric mode, rather than relying on global variables. Removing these has the nice side-effect of allowing us to remove more global variables. Change-Id: Iee716ef38729705432dd10d12758c886d38701a8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5104 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-04cbfstool: Hide cbfstool_offset from the global namespaceAlexandru Gagniuc
This is part of a larger effort to reduce global variable usage in cbfstool. cbfstool_offset is particularly easy to hide since it's only used in common.c . Change-Id: Ic45349b5148d4407f31e12682ea0ad4b68136711 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5102 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-04pcengines/alix2c: Add ALIX.2C as a clone of ALIX.2D.Vladimir Serbinenko
According to vendor (Pascal Dornier) they're the same from coreboot perspective. Change-Id: I43aeb77f21c251b3d9c5c2dcfa01d4d1de0bc87b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5114 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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