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2015-08-20crossgcc: Update gcc to 5.2.0Patrick Georgi
All compilers built, incl. x86_64-elf as multilib and riscv-elf. Change-Id: Iafa61b1d2ffc9c737ab67a417c62417593b69372 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10975 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19libpayload: Fix default_memmove() implementationNico Huber
If I wanted to fill the whole memory address space with one byte, I wouldn't try it that subtle. With size_t beeing unsigned the loop condition >= 0 was always true. Change-Id: Idee6a4901f6697093c88bda354b5e43066c0d948 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11286 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-19Store the payload config and revision in CBFSMartin Roth
Store the payload config and version files in CBFS if using a SeaBIOS or filo payload if INCLUDE_CONFIG_FILE is enabled. Change-Id: I0c1b4da8f6179b9cee06cecfa76bc631b43196e0 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10607 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-19Skylake: update cbmem_topRizwan Qureshi
cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory regions reserved by fsp for chipset use. With that being removed, the function needs to properly walk though the memory map resulted from fsp memory init to find out the usable address for cbmem root. Refer the FSP 1.3.0 Integartion guide for more details on the Memory Map. systemagent should also use the same mechanism to create the reserved RAM resource. BRANCH=None BUG=None TEST=Build and Boot kunimitsu (FAB3) CQ-DEPEND=CL:*226035,CL:*226045,CL:291573 Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291611 Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com> Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: http://review.coreboot.org/11239 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19skylake: Update Memory and Silicon Init paramsRizwan Qureshi
Update the MemoryInit and SilicoInit params as per FSP 1.3.0 release. Note: add SvGv and Rmt to Upd. BRANCH=None BUG=None TEST=Build and Boot FAB3 (Kunimitsu) CQ-DEPEND=CL:*226035, CL:*226045 Original-Change-Id: I62000f6a485fee42ef733c3b548192f2bedfce49 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291573 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Change-Id: Iaafa658b4e710fe512526a521cf6c529efb19bf0 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: http://review.coreboot.org/11238 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19Kunimitsu: Fix Wifi, kepler RP mapping and enable ClkReqSupportPratik Prajapati
(1) Wifi is connected on RP1 which is 1c.0 , so enabling 1c.0 and disabling 1d.0 (2) kepler is on RP5 which is 1c.4, so enabling it (3) enabling ClkReqSupport for RP1 and RP5 so that L1 substates can get enabled. BRANCH=None BUG=chrome-os-partner:43738 TEST=Built and boot for Kunimitsu. checked all PCIe powersaving states (LTR, L1, L1S) are enabled Original-Change-Id: I525661399d1a4d939b53d5ed5f7991598b84ddcd Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293482 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ib9a771a6ec137217668fb0385efc13b1824772b4 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/11237 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19libpayload: usb: dwc2: fix usb plug/unplug bugYunzhi Li
Check device connect status while waiting for usb transfer complete Avoid coreboot get stuck when usb device unplugged BUG=chrome-os-partner:35525 TEST=None BRANCH=None Original-Change-Id: Id103501aa0d8b31b0b81bef773679c0fad79f689 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292630 Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292966 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Commit-Queue: David Hendricks <dhendrix@chromium.org> Change-Id: I49396b74131dbfda505d9d3de5adbdc87eb92ce1 Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Reviewed-on: http://review.coreboot.org/11236 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19skylake: correct IO-APIC redirection entry countAaron Durbin
The skylake IO-APIC supports up to 120 redirection entries. In practice it seems FSP has already written to this write-once register. However, it doesn't hurt to actually be correct within the source. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I666b1b6034f0d37a37ea918f802317f9d5f15718 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293251 Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I6ddbc89c98c262e2dd0f9f0b76adb092d3043602 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11235 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19glados: use macros for magic numbers in ASLAaron Durbin
The skylake SoC code now has macros for the previously hard-code numbers for IRQs and GPEs. Switch over to using those as they bring a little more clarity. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Ic8fcc59d680cdddec9dfbc3bf679731f6d786793 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293411 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I594907005372100a3c9d17dda9d17769844ad272 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11234 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19skylake: add gpe.h for ASL generationAaron Durbin
One thing that is brittle is lining up GPE0 bits in ASL and with a board's design proper. This results in open calculated magic numbers. To help alleviate this provide just #defines that C preprocessor can use before handing the source off to the ASL compiler. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Everything's intact. Original-Change-Id: I359616ebe4bfc83c05bafe0ca36b766efd16dcca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293410 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I32513c324b923fa0adbd6a0ee920c27e9b97dd1b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11233 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19Kunimitsu: Enable root ports and clkreqsPravin Angolkar
This patch enables the root ports and configures the clock req numbers as per the design On kunimitsu FAB3 board with D0 MCP Root port 1 --> Wifi card --> clkreq 1 Root port 4 --> Kepler VP8/VP9--> clkreq 2 BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for Kunimitsu and Boot Kunimitsu board with D0 MCP Original-Change-Id: I4e110d2d07efbfa7a306852301cd1cd89027b2ba Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290051 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Original-Tested-by: Naveenkrishna Ch <naveenkrishna.ch@intel.com> Change-Id: I6d66c78496ac3f43e07d96feefed35cf50da6aa1 Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com> Reviewed-on: http://review.coreboot.org/11232 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19Kunimitsu: Update Mainboard ASL for Kunimitsu FAB3 with D0 MCPNaveen Krishna Chatradhi
This patch updates the mainboard.asl file to support Kunimitsu FAB3 board which is based on SKL D0 MCP. BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for kunimitsu; booted on kunimitsu FAB3 with D0 MCP Original-Change-Id: I31a315740d49125591591b20c296babe49004166 Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290050 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I81c22e407d1b3d420744eaf1d3f7ff4e8e749bcb Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11231 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19Kunimitsu: Update Gpio table for kunimitsu FAB3 variantNaveen Krishna Chatradhi
This patch updates the GPIO table to support Kunimitsu FAB3 variant, based on SKL D0 MCP. BRANCH=None BUG=chrome-os-partner:43324 CQ-DEPEND=CL:*224327, CL:*224328 TEST=Built for kunimitsu; booted on kunimitsu with D0 MCP. Original-Change-Id: I2343187a919f6d29161069135d97484191198056 Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com> Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/289939 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I47302062788a90550fd38cb113e418b21d3f756c Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com> Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> Reviewed-on: http://review.coreboot.org/11230 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19ifdtool: handle region masks correctlyAaron Durbin
The get_region() function was using fixed masks for the base and limit. However, newer descriptors (on skylake, e.g.) use a 15-bit mask -- not a 12-bit one. Choose the right mask based on ifd_version. BUG=chrome-os-partner:43461 BRANCH=None TEST=Built glados bootimage. Original-Change-Id: Ibcbfd649a561d36b17ea2cc8fbeb30ffdbbb2c96 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293250 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I7f2ef9fb8e5b6c7114225fecc2798668d6507ac3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11229 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19ifdtool: Update to support Skylake+ descriptor formatDuncan Laurie
The descriptor format has changed with Skylake and some fields have moved or been expanded. This includes new SPI frequencies and chip densities, though unfortunately 30MHz in the new format conflicts with 50MHz in the old format... There are also new regions with a few reserved regions inserted before a new embedded controller region. Unfortunately there does not seem to be a documented version field so there does not seem to be an official way to determine if a specific descriptor is new or old. To work around this ifdtool checks the hardcoded "SPI Read Frequency" to see if it set for 20MHz (old descriptor) or 17MHz (new descriptor). BUG=chrome-os-partner:40635 BUG=chrome-os-partner:43461 BRANCH=none TEST=run ifdtool on skylake and broadwell images Original-Change-Id: I0561b3c65fcb3e77c0a24be58b01db9b3a36e5a9 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/281001 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: I9a08c26432e13c4000afc50de9d8473e6f911805 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293240 Reviewed-on: http://review.coreboot.org/11228 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19AMD ROMSIG: Only check location if ROMSIG is usedMartin Roth
The location of the AMD ROMSIG binary was being checked and warnings were being printed even when the ROMSIG file wasn't being used. These false warnings are avoided by moving the warnings into the block where the CBFS file for the ROMSIG is generated. Change-Id: Ie44a2ad97ff3b15df6dc9b8166992de6ed837997 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11161 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-18northbridge/amd/amdfam10: Redirect legacy VGA memory access to MMIOTimothy Pearson
Commit 27baa32 (cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled) deactivated TSeg SMRAM, which had the side effect of routing legacy VGA memory access to DRAM. Restore the correct MMIO mapping via the MMIO configuration registers. TEST: Booted KGPE-D16 with nVidia 7300LE card and verified proper VGA functionality. Change-Id: Ie4b7c0b2d6f9a02af9a022565fe514119513190a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11240 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-17Fix Kconfig: ALWAYS_LOAD_OPROM has unmet dependency VGA_ROM_RUNMartin Roth
Broadwell and Skylake chipsets, along with a few mainboards were selecting ALWAYS_LOAD_OPROM without making sure that the dependency for that symbol was met as well. Looking at the dependencies for VGA_RUN_ROM, we see: PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT Since ARCH_X86 selects PCI, that's always met here. Since Broadwell and Skylake don't have native VGA init yet, that's not needed. - Make sure that VGA_RUN_ROM is selected as well. - Add dependency on !PAYLOAD_SEABIOS for both ALWAYS_LOAD_OPROM and VGA_RUN_ROM symbols where they're selected. Fixes Kconfig warning for these boards and chipsets: warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS) selects ALWAYS_LOAD_OPROM which has unmet direct dependencies (VGA_ROM_RUN) Change-Id: I787a87e9467e1fc7afe8b04864b2a89b54824b9f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11246 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-17soc/intel/skylake/Kconfig: Fix recursive Kconfig dependencyMartin Roth
Change the dependency on CONSOLE_SERIAL to select CONSOLE_SERIAL based on this question. The dependency was causing multiple warnings on every platform tested. src/console/Kconfig:21:error: recursive dependency detected! src/console/Kconfig:21: symbol CONSOLE_SERIAL depends on DRIVERS_UART_8250MEM src/drivers/uart/Kconfig:16: symbol DRIVERS_UART_8250MEM is selected by UART_DEBUG src/soc/intel/skylake/Kconfig:198: symbol UART_DEBUG depends on CONSOLE_SERIAL Change-Id: Ia0426cd150561694081b5ea7c6797d36022c1f57 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11243 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-08-17AMD Binary PI: Fix the build when the user's group has a spaceDan Christensen
When the user's primary group contains a space ls -l and awk get the wrong value for the file size. This results in padding the coreboot_psp_directory_combine_pubkey.bin file too much which ultimately means RtmPubSigned.key can not be placed at the necessary offset. Changing from ls -l to ls -ln seemed like the most minimal, POSIX-friendly way to effect this change. Change-Id: Icbeaad476753924626adb6de53dc9a30052d91a6 Signed-off-by: Dan Christensen <opello@opello.org> Reviewed-on: http://review.coreboot.org/11242 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao <zheng.bao@amd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-08-15seabios integration: deal with ccache woes some morePatrick Georgi
seabios integration interprets the CC variable with a special case when ccache is prepended to the compiler. Since the integration also tries to extract compiler flags (which I'm not sure we still add to CC _ever_), that also needs to look at only the part of the string that contains compiler and (maybe) flags, so skip the first word if it was determined to be the path to the ccache binary. Change-Id: I717863f456bf4fd6f08427d86633079ecda039df Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/11227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-14acpi: 64bit fixesStefan Reinauer
Change-Id: I5d0c95af7d35115b5ac4141489caceef4ee1c8bb Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/11088 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14emulation/qemu: Serialize IQCR methodPaul Menzel
Fix the remark below for the mainboards qemu-i440x and qemu-q35. Intel ACPI Component Architecture ASL+ Optimizing Compiler version 20150717-32 Copyright (c) 2000 - 2015 Intel Corporation dsdt.aml 336: Method(IQCR, 1, NotSerialized) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) ASL Input: dsdt.aml - 399 lines, 16756 bytes, 245 keywords AML Output: dsdt.aml - 4000 bytes, 146 named objects, 99 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 1 Remarks, 233 Optimizations Change-Id: Ibe48f872768ab8295d6fed3359d9eef04b736a05 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11162 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-14glados: make EC_SCI_L workAaron Durbin
In order for the EC_SCI_L to work the GPE0 route needs to be set along w/ the GPE event for the EC. As the GPE0 route is dynamic the EC_SCI_GPI needs to be set along with the route so everything lines up. In this case, the GPE0 route is set to the defaults such that GPP_C, GPP_D, and GPP_E are routed to GPE0 block 0, 1, and 2, respectively. This works out for glados because the EC_SCI_L is connected to GPP_E16. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. The 'acpi' interrupt in /proc/interrupts is incrementing as well as /sys/firmware/acpi/interrupts/gpe50. Original-Change-Id: I71fc4bec124f3ac87453a099412154e67aba6280 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292011 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Idbb6d29364655537abc9ae6f012b3abb38edf138 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11210 Tested-by: build bot (Jenkins)
2015-08-14glados: make EC_SMI_L functionalAaron Durbin
Set the EC_SMI_GPI define to be GPP_E15 and route that GPIO for SMI generation. Also, the mainboard_smi_gpi_handler() was introduced on skylake in order to process any GPI that could generate an SMI. Switch to this handler so one can process the appropriate events. BUG=chrome-os-partner:43778 BRANCH=None TEST=Used 'lidclose' on EC command line during depthcharge to confirm EC_SMI_L generates SMI and shutdown happens. Original-Change-Id: Ia365b86161670a809e3fa99dde38fccc612d5e77 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291934 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ic16ea8e8d6ff564977ed2081d2353c82af71adea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11209 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: fix SMI GPI status handlingAaron Durbin
The current construction for processing SMI GPI events didn't allow for the mainboard to query the state of a particular GPI for the snapshotted SMI event. The skylake part can route GPIs from any (there are design limitations) GPIO group. Those status and enable registers are within the GPIO community so one needs to gather all the possibilities in order to query the state. The call chain did this: southbridge_smi_gpi( clear_alt_smi_status() -> reset_alt_smi_status() -> print_all_smi_status() -> return 0) As a replacement the following functions and types are introduced: struct gpi_status - represent gpi status. gpi_status_get() - per gpi query on struct gpi_status gpi_clear_get_smi_status() - clear and retrieve SMI GPI status mainboard_smi_gpi_handler() - mainboard handler using gpi_status Also remove gpio_enable_all_smi() as that construct was never used, but it also is quite heavy handed in that it would enable SMI generation for all GPIs. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built. Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291933 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: enable SMI routed GPIsAaron Durbin
The first pass of the GPIO configuration patch didn't enable the SMI# generation for GPIs marked as SMI routed. Now when a pad is configured as SMI routed the bit for the SMI enablement is set accordingly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Confirmed SMI_EN being set for SMI routed GPIOs. Original-Change-Id: I796b68accb7a49b03ef18539861e72fa9d169c26 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292010 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I3be770234d3f605ae630ecd5cd4cfe4867243999 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: clarify and fix gpio macrosAaron Durbin
The gpio pad configuration currently defaults to ACPI owned GPIs. A '0' was used which wasn't so clear. Add a comment and explicitly set it to ACPI. Also, PAD_CFG_GPI_ACPI_SMI wasn't using the _PAD_CFG_ATTRS macro which causes compliation errors if attempted to be instantiated. No piece of code tried to use it so the error was overlooked. Lastly, allow for soc/gpio.h to be included during ASL compilation. That allows for gpio_defs.h to be included and those macros utilized without needing to know the file name and where it lives; just use the generic gpio.h. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I9dbadb0b494683ab38babfc1ac5e13093ee37730 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291935 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id4fa8b65ec1e1537dbf09824c2155119a768807e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: provide clarification for FADT gpe0_blk_lenAaron Durbin
Instead of using a hard-coded value leverage the existing definitions to perform GPE0 block length calculations. There are 4 pairs of 32-bit status/enable registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291932 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11205 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: remove ec_smi_gpio and alt_gp_smi_enAaron Durbin
The ec_smi_gpio and alt_gp_smi_en devicetree options are goign to be removed. The plan for skylake is to set the settings by the mainboard through either gpio pad configuration or through helper functions. Moreover, these values only allow *1* SMI GPIO configuration in that the following has to be true: alt_gp_smi_en = 1 << (ec_smi_gpio % 24) If not, then another gpio(s) from the same group has the SMI_EN bit set for it. Lastly, remove all the subsequent dependencies as they are no longer used: enable_alt_smi() and gpio_enable_group(). BUG=chrome-os-partner:43778 BRANCH=None TEST=None Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291931 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: provide GPE0 routing devicetree configurationAaron Durbin
On skylake the GPE0 routing can be dynamically changed to a particular GPIO group. Provide the ability for the mainboard to set the route accordingly. If any of the values in the devicetree are the same the current setting in the PMC register is used. The GPIO communities need to have matching configuration for the plumbing to work properly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados w/ and w/o devicetree changes. Fields are set accordingly. Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291930 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14util/cbmem: accumulate total time for all entriesAaron Durbin
Display the total accumulated time using each timestamp entry. It purposefully doesn't take into account the first timestamp because that can be a platform dependent value that may not contribute to the concept of "total". BUG=None BRANCH=None TEST=Ran cbmem on glados where TSC doesn't reset to 0 on reboots. Clear total value given at end. Original-Change-Id: Idddb8b88d3aaad11d72c58b18e8fd9fd1447a30e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291480 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I79a0954d3b738323aaebb3e05171bcf639e5d977 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11202 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: remove IedSize from chip.hAaron Durbin
IedSize is not used in replace of IED_REGION_SIZE. Drop it from chip.h. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I38f6518701306c0ffc6d2b2e3fe01624a5eadf54 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290933 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I9dd9e689d4d4f7b4770369dcd042d3325990ae32 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11201 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14kunimitsu sklrvp: remove unused IedSizeAaron Durbin
The skylake code is using IED_REGION_SIZE instead of devicetree.cb. Drop the the option from the device trees. BUG=chrome-os-partner:43636 BRANCH=None TEST=None Original-Change-Id: Ib252266060fbc6ed0eeaac19a6b79c173c6c9a13 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290932 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: Ib08628e163ac27d4c49eddcbec6cab3252abd4aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11200 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: pass IED_REGION_SIZE Kconfig to FSPAaron Durbin
Ignore the devicetree.cb setting and use the already existing IED_REGION_SIZE Kconfig option. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ic1e760493635218faddeee4003303949305bc529 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290931 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I416d4eb186a42d3258682e02a0a2e1db5bb668ac Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14intel/common: fix stage_cache_external_region()Aaron Durbin
The stage_cache_external_region() calculation is actually dependennt on the properties of the chipset. The reason is that certain regions within the SMRAM are used for chipset-specific features. Therefore, provide an API for abstracting the querying of subregions within the SMRAM. The 3 subregions introduced are: SMM_SUBREGION_HANDLER - SMM handler area SMM_SUBREGION_CACHE - SMM cache region SMM_SUBREGION_CHIPSET - Chipset specific area. The subregions can be queried using the newly added smm_subregion() function. Now stage_cache_external_region() uses smm_subregion() to query the external stage cache in SMRAM, and this patch also eliminates 2 separate implementations of stage_cache_external_region() between romstage and ramstage. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290833 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: use smm_subregion() during SMM relocationAaron Durbin
The smm_subregion() support allows the SMM relocation to not use duplicated math by calling out the specific regions it wants. IED base is now correct and not pointing outside from SMRAM. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ief8940c2ab6320449500ced2121d0cd7ed73af4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290930 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Trybot-Ready: David James <davidjames@chromium.org> Change-Id: I00c3284cfacb2a73942640ccfa7912b7d65efb9d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11198 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14intel/common: use external stage cache for fsp_ramstageAaron Durbin
The fsp_ramstage.c code was not taking advantage of the stage cache which does all the accounting and calculation work for the caller. Remove the open coded logic and use the provided infrastructure. Using said infrastructure means there's no need for the FSP_CACHE_SIZE Kconfig variable. Therefore, remove it. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4363823c825b4a700205769f109ff9cf0d78b897 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290831 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ifd3cc4a538daac687949c5f4cab2c687368d6787 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11196 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: clean up SMM region calculationsAaron Durbin
The TSEG is defined to be from TSEG->BGSM in the host bridge registers. Use those registers at runtime to calculate the correct TSEG size. Lastly, use a few helper macros to make constants more readable. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290832 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11195 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14libpayload: usb: xhci: Fix list of cleared port change bitsJulius Werner
The xhci_rh_port_status_changed() function tries to always clear all port status bits, even though most of them don't interest us. This is generally a smart thing to do since not clearing a status bit may cause the controller to not generate any more Port Status Change Events. However, the bitmask we currently use doesn't cover bit 23 (Port Config Error Change) and instead covers bit 16 (Port Link State Write Strobe) which is not really related to this and not a W1C bit. Probably a typo, so let's fix that. BRANCH=None BUG=None TEST=Plugged/unplugged a bunch of USB devices on an XHCI Falco. Original-Change-Id: Ia83f5b72cce094859c0f0e730752d7b5cfa6e1c6 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291842 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I11f5fe38cb70055daf6e866a8ee84ca80488e3bf Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11194 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14fsp1_1: fsp_relocate: use struct region_device and struct progAaron Durbin
Using struct prog and struct region_device allows for the caller to be none-the-wiser about where FSP gets placed. It also allows for the source location to be abstracted away such that it doesn't require a large mapping up front to do the relocation. Lastly, it allows for simplifying the intel/commmon FSP support in that it can pass around a struct prog. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I034b04ab2b7e9e01f5ee14fcc190f04b90517d30 Original-Signed-off-by: Aaron Durbin <adurbin@chroumium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290830 Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: Ibe1f206a9541902103551afaf212418fcc90e73c Signed-off-by: Aaron Durbin <adurbin@chroumium.org> Reviewed-on: http://review.coreboot.org/11193 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14stage_cache: make prog const in stage_cache_add()Aaron Durbin
The stage_cache_add() function should not be manipulating the struct prog argument in anyway. Therefore, mark it as const. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4509e478d3c98247b9d776f6534b949d9ba6282c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290721 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ibadc00a9e1cbbf12119def92d77a79077625fb85 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11192 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14Skylake: Add ASL code to enable GPIO controllerArchana Patni
This patch enables GPIO controller for skylake. It adds community base addresses and offset for Community0, Community1, and Community3. Community2 is not exposed in BIOS or enabled in the kernel driver. Also, clean up the carry over GWAK implementation from BDW. BRANCH=None BUG=chrome-os-partner:42393 TEST=cat /sys/kernel/debug/gpio should list of GPIOs TEST=export a GPIO pin using /sys/class/gpio/export Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291230 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9 Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Reviewed-on: http://review.coreboot.org/11191 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.cAaron Durbin
acpi_is_wakeup_s3() was introduced in upstream coreboot while the FSP support code was written. Move to using that instead of using the romstage_handoff structure directly. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290720 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14libpayload: Do not gate USB_DWC2 on USB_HIDDavid Hendricks
This forward-ports the change from CL:277155 since the Kconfig file was renamed from Config.in. BUG=chrome-os-partner:41416 BRANCH=none TEST=built and booted on Mickey, keyboard works at dev screen Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: Ibffa5188df51ecd7b8bdd631d4b767ec64130819 Original-Reviewed-on: https://chromium-review.googlesource.com/291138 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Change-Id: Iebb1da6ec8c7886a6eb9ebcc67b59d617496c555 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/11188 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@google.com>
2015-08-14libpayload: usb: xhci: Count new Max Scratchpad Bufs bits from XHCI 1.1Julius Werner
The 1.1 revision of the XHCI specification added an extra 5 bits to the Max Scratchpad Bufs field of HCSPARAMS2 that newer controllers make use of. Not honoring these bits means we're not allocating as many scratchpad buffers as the controller expects, which means it will interpret some uninitialized values from the end of the pointer array as scratchpad buffer pointers, which obviously doesn't end well. Let's fix that. BRANCH=none BUG=chrome-os-partner:42279 TEST=Makes a USB-related memory corruption issue disappear. Original-Change-Id: I7c907492339262bda31cdd2b5c0b588de7df8544 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iba1007bfebffe1f564f78bb875fff9ba0fe11a38 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11189 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14libpayload: usb: dwc2: fix short packet transferYunzhi Li
If short packet detected, stop this transfer and return the actual transferred size BUG=chrome-os-partner:42817 TEST=Netboot could run well BRANCH=None Original-Change-Id: Icb4317f48aa04ac15bb1886b81d2e3c472d123d0 Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288215 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Original-(cherry picked from commit d372343b4e3d664ce2d76dbf55a5061b5d496bba) Original-Reviewed-on: https://chromium-review.googlesource.com/291064 Original-Commit-Queue: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Change-Id: I43d9edffe2074c037f2df203621863e54d2597fa Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Reviewed-on: http://review.coreboot.org/11187 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: clear write-1-to-clear fields in power regsAaron Durbin
Explicitly clear all write-1-to-clear fields in the appropriate power state registers. That way stale state isn't left around from boot to boot. The MMIO PMC registers are always added such that the resource can be accessed from reg_script. It doesn't hurt to add the resource, and it's actually more informative by attaching the actual resources owned by the device. BUG=chrome-os-partner:43625 BRANCH=None TEST=Built and boot glados. Did global reset. Noticed bits set. Did normal reset and saw those same bits no longer set. Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290339 Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11186 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: fix invalid GNVS base addressAaron Durbin
Leaving a sentinel 0xC0DEBABE and fixing it up is is the old way of setting the correct base address for GNVS. One just needs to reference NVSA which is already filled in by the skylake ACPI code. BUG=chrome-os-partner:43611 BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. /sys/firmware/log shows up as well as ramoops using the correct address. Original-Change-Id: I1d4979b1bb65faa76316a4ec4c551a7b9b9eed32 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290338 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I25efea73a383215f9365ce91230f79516b0201a6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11185 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14skylake: enumerate the SMI status fieldsAaron Durbin
Provide #defines for the bit fields in the SMI status register. This allows for one to set the callback accordingly without hard coding the index. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289802 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11184 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 02:34:20 +0000